2018-07-05 21:16:46 +08:00
|
|
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
|
|
|
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
|
|
|
|
|
|
|
|
|
|
; If positive...
|
|
|
|
|
|
|
|
|
|
define i32 @zext_ifpos(i32 %x) {
|
|
|
|
|
; CHECK-LABEL: zext_ifpos:
|
|
|
|
|
; CHECK: # %bb.0:
|
[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)
This is almost the same as an existing IR canonicalization in instcombine,
so I'm assuming this is a good early generic DAG combine too.
The motivation comes from reduced bit-hacking for select-of-constants in IR
after rL331486. We want to restore that functionality in the DAG as noted in
the commit comments for that change and the llvm-dev discussion here:
http://lists.llvm.org/pipermail/llvm-dev/2018-July/124433.html
The PPC and AArch tests show that those targets are already doing something
similar. x86 will be neutral in the minimal case and generally better when
this pattern is extended with other ops as shown in the signbit-shift.ll tests.
Note the asymmetry: we don't include the (extend (ifneg X)) transform because
it already exists in SimplifySelectCC(), and that is verified in the later
unchanged tests in the signbit-shift.ll files. Without the 'not' op, the
general transform to use a shift is always a win because that's a single
instruction.
Alive proofs:
https://rise4fun.com/Alive/ysli
Name: if pos, get -1
%c = icmp sgt i16 %x, -1
%r = sext i1 %c to i16
=>
%n = xor i16 %x, -1
%r = ashr i16 %n, 15
Name: if pos, get 1
%c = icmp sgt i16 %x, -1
%r = zext i1 %c to i16
=>
%n = xor i16 %x, -1
%r = lshr i16 %n, 15
Differential Revision: https://reviews.llvm.org/D48970
llvm-svn: 337130
2018-07-16 00:27:07 +08:00
|
|
|
; CHECK-NEXT: notl %edi
|
|
|
|
|
; CHECK-NEXT: shrl $31, %edi
|
|
|
|
|
; CHECK-NEXT: movl %edi, %eax
|
2018-07-05 21:16:46 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
|
%c = icmp sgt i32 %x, -1
|
|
|
|
|
%e = zext i1 %c to i32
|
|
|
|
|
ret i32 %e
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @add_zext_ifpos(i32 %x) {
|
|
|
|
|
; CHECK-LABEL: add_zext_ifpos:
|
|
|
|
|
; CHECK: # %bb.0:
|
[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)
This is almost the same as an existing IR canonicalization in instcombine,
so I'm assuming this is a good early generic DAG combine too.
The motivation comes from reduced bit-hacking for select-of-constants in IR
after rL331486. We want to restore that functionality in the DAG as noted in
the commit comments for that change and the llvm-dev discussion here:
http://lists.llvm.org/pipermail/llvm-dev/2018-July/124433.html
The PPC and AArch tests show that those targets are already doing something
similar. x86 will be neutral in the minimal case and generally better when
this pattern is extended with other ops as shown in the signbit-shift.ll tests.
Note the asymmetry: we don't include the (extend (ifneg X)) transform because
it already exists in SimplifySelectCC(), and that is verified in the later
unchanged tests in the signbit-shift.ll files. Without the 'not' op, the
general transform to use a shift is always a win because that's a single
instruction.
Alive proofs:
https://rise4fun.com/Alive/ysli
Name: if pos, get -1
%c = icmp sgt i16 %x, -1
%r = sext i1 %c to i16
=>
%n = xor i16 %x, -1
%r = ashr i16 %n, 15
Name: if pos, get 1
%c = icmp sgt i16 %x, -1
%r = zext i1 %c to i16
=>
%n = xor i16 %x, -1
%r = lshr i16 %n, 15
Differential Revision: https://reviews.llvm.org/D48970
llvm-svn: 337130
2018-07-16 00:27:07 +08:00
|
|
|
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
|
|
|
|
|
; CHECK-NEXT: notl %edi
|
|
|
|
|
; CHECK-NEXT: shrl $31, %edi
|
|
|
|
|
; CHECK-NEXT: leal 41(%rdi), %eax
|
2018-07-05 21:16:46 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
|
%c = icmp sgt i32 %x, -1
|
|
|
|
|
%e = zext i1 %c to i32
|
|
|
|
|
%r = add i32 %e, 41
|
|
|
|
|
ret i32 %r
|
|
|
|
|
}
|
|
|
|
|
|
2018-07-28 00:22:40 +08:00
|
|
|
define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) {
|
|
|
|
|
; CHECK-LABEL: add_zext_ifpos_vec_splat:
|
|
|
|
|
; CHECK: # %bb.0:
|
|
|
|
|
; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
|
|
|
|
|
; CHECK-NEXT: pcmpgtd %xmm1, %xmm0
|
|
|
|
|
; CHECK-NEXT: psrld $31, %xmm0
|
|
|
|
|
; CHECK-NEXT: por {{.*}}(%rip), %xmm0
|
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
|
%c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
|
|
|
|
|
%e = zext <4 x i1> %c to <4 x i32>
|
|
|
|
|
%r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
|
|
|
|
|
ret <4 x i32> %r
|
|
|
|
|
}
|
|
|
|
|
|
2018-07-05 21:16:46 +08:00
|
|
|
define i32 @sel_ifpos_tval_bigger(i32 %x) {
|
|
|
|
|
; CHECK-LABEL: sel_ifpos_tval_bigger:
|
|
|
|
|
; CHECK: # %bb.0:
|
[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)
This is almost the same as an existing IR canonicalization in instcombine,
so I'm assuming this is a good early generic DAG combine too.
The motivation comes from reduced bit-hacking for select-of-constants in IR
after rL331486. We want to restore that functionality in the DAG as noted in
the commit comments for that change and the llvm-dev discussion here:
http://lists.llvm.org/pipermail/llvm-dev/2018-July/124433.html
The PPC and AArch tests show that those targets are already doing something
similar. x86 will be neutral in the minimal case and generally better when
this pattern is extended with other ops as shown in the signbit-shift.ll tests.
Note the asymmetry: we don't include the (extend (ifneg X)) transform because
it already exists in SimplifySelectCC(), and that is verified in the later
unchanged tests in the signbit-shift.ll files. Without the 'not' op, the
general transform to use a shift is always a win because that's a single
instruction.
Alive proofs:
https://rise4fun.com/Alive/ysli
Name: if pos, get -1
%c = icmp sgt i16 %x, -1
%r = sext i1 %c to i16
=>
%n = xor i16 %x, -1
%r = ashr i16 %n, 15
Name: if pos, get 1
%c = icmp sgt i16 %x, -1
%r = zext i1 %c to i16
=>
%n = xor i16 %x, -1
%r = lshr i16 %n, 15
Differential Revision: https://reviews.llvm.org/D48970
llvm-svn: 337130
2018-07-16 00:27:07 +08:00
|
|
|
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
|
|
|
|
|
; CHECK-NEXT: notl %edi
|
|
|
|
|
; CHECK-NEXT: shrl $31, %edi
|
|
|
|
|
; CHECK-NEXT: leal 41(%rdi), %eax
|
2018-07-05 21:16:46 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
|
%c = icmp sgt i32 %x, -1
|
|
|
|
|
%r = select i1 %c, i32 42, i32 41
|
|
|
|
|
ret i32 %r
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @sext_ifpos(i32 %x) {
|
|
|
|
|
; CHECK-LABEL: sext_ifpos:
|
|
|
|
|
; CHECK: # %bb.0:
|
[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)
This is almost the same as an existing IR canonicalization in instcombine,
so I'm assuming this is a good early generic DAG combine too.
The motivation comes from reduced bit-hacking for select-of-constants in IR
after rL331486. We want to restore that functionality in the DAG as noted in
the commit comments for that change and the llvm-dev discussion here:
http://lists.llvm.org/pipermail/llvm-dev/2018-July/124433.html
The PPC and AArch tests show that those targets are already doing something
similar. x86 will be neutral in the minimal case and generally better when
this pattern is extended with other ops as shown in the signbit-shift.ll tests.
Note the asymmetry: we don't include the (extend (ifneg X)) transform because
it already exists in SimplifySelectCC(), and that is verified in the later
unchanged tests in the signbit-shift.ll files. Without the 'not' op, the
general transform to use a shift is always a win because that's a single
instruction.
Alive proofs:
https://rise4fun.com/Alive/ysli
Name: if pos, get -1
%c = icmp sgt i16 %x, -1
%r = sext i1 %c to i16
=>
%n = xor i16 %x, -1
%r = ashr i16 %n, 15
Name: if pos, get 1
%c = icmp sgt i16 %x, -1
%r = zext i1 %c to i16
=>
%n = xor i16 %x, -1
%r = lshr i16 %n, 15
Differential Revision: https://reviews.llvm.org/D48970
llvm-svn: 337130
2018-07-16 00:27:07 +08:00
|
|
|
; CHECK-NEXT: notl %edi
|
|
|
|
|
; CHECK-NEXT: sarl $31, %edi
|
|
|
|
|
; CHECK-NEXT: movl %edi, %eax
|
2018-07-05 21:16:46 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
|
%c = icmp sgt i32 %x, -1
|
|
|
|
|
%e = sext i1 %c to i32
|
|
|
|
|
ret i32 %e
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @add_sext_ifpos(i32 %x) {
|
|
|
|
|
; CHECK-LABEL: add_sext_ifpos:
|
|
|
|
|
; CHECK: # %bb.0:
|
[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)
This is almost the same as an existing IR canonicalization in instcombine,
so I'm assuming this is a good early generic DAG combine too.
The motivation comes from reduced bit-hacking for select-of-constants in IR
after rL331486. We want to restore that functionality in the DAG as noted in
the commit comments for that change and the llvm-dev discussion here:
http://lists.llvm.org/pipermail/llvm-dev/2018-July/124433.html
The PPC and AArch tests show that those targets are already doing something
similar. x86 will be neutral in the minimal case and generally better when
this pattern is extended with other ops as shown in the signbit-shift.ll tests.
Note the asymmetry: we don't include the (extend (ifneg X)) transform because
it already exists in SimplifySelectCC(), and that is verified in the later
unchanged tests in the signbit-shift.ll files. Without the 'not' op, the
general transform to use a shift is always a win because that's a single
instruction.
Alive proofs:
https://rise4fun.com/Alive/ysli
Name: if pos, get -1
%c = icmp sgt i16 %x, -1
%r = sext i1 %c to i16
=>
%n = xor i16 %x, -1
%r = ashr i16 %n, 15
Name: if pos, get 1
%c = icmp sgt i16 %x, -1
%r = zext i1 %c to i16
=>
%n = xor i16 %x, -1
%r = lshr i16 %n, 15
Differential Revision: https://reviews.llvm.org/D48970
llvm-svn: 337130
2018-07-16 00:27:07 +08:00
|
|
|
; CHECK-NEXT: notl %edi
|
|
|
|
|
; CHECK-NEXT: shrl $31, %edi
|
2018-07-05 21:16:46 +08:00
|
|
|
; CHECK-NEXT: movl $42, %eax
|
[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)
This is almost the same as an existing IR canonicalization in instcombine,
so I'm assuming this is a good early generic DAG combine too.
The motivation comes from reduced bit-hacking for select-of-constants in IR
after rL331486. We want to restore that functionality in the DAG as noted in
the commit comments for that change and the llvm-dev discussion here:
http://lists.llvm.org/pipermail/llvm-dev/2018-July/124433.html
The PPC and AArch tests show that those targets are already doing something
similar. x86 will be neutral in the minimal case and generally better when
this pattern is extended with other ops as shown in the signbit-shift.ll tests.
Note the asymmetry: we don't include the (extend (ifneg X)) transform because
it already exists in SimplifySelectCC(), and that is verified in the later
unchanged tests in the signbit-shift.ll files. Without the 'not' op, the
general transform to use a shift is always a win because that's a single
instruction.
Alive proofs:
https://rise4fun.com/Alive/ysli
Name: if pos, get -1
%c = icmp sgt i16 %x, -1
%r = sext i1 %c to i16
=>
%n = xor i16 %x, -1
%r = ashr i16 %n, 15
Name: if pos, get 1
%c = icmp sgt i16 %x, -1
%r = zext i1 %c to i16
=>
%n = xor i16 %x, -1
%r = lshr i16 %n, 15
Differential Revision: https://reviews.llvm.org/D48970
llvm-svn: 337130
2018-07-16 00:27:07 +08:00
|
|
|
; CHECK-NEXT: subl %edi, %eax
|
2018-07-05 21:16:46 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
|
%c = icmp sgt i32 %x, -1
|
|
|
|
|
%e = sext i1 %c to i32
|
|
|
|
|
%r = add i32 %e, 42
|
|
|
|
|
ret i32 %r
|
|
|
|
|
}
|
|
|
|
|
|
2018-07-28 00:22:40 +08:00
|
|
|
define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {
|
|
|
|
|
; CHECK-LABEL: add_sext_ifpos_vec_splat:
|
|
|
|
|
; CHECK: # %bb.0:
|
|
|
|
|
; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
|
|
|
|
|
; CHECK-NEXT: pcmpgtd %xmm1, %xmm0
|
|
|
|
|
; CHECK-NEXT: paddd {{.*}}(%rip), %xmm0
|
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
|
%c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
|
|
|
|
|
%e = sext <4 x i1> %c to <4 x i32>
|
|
|
|
|
%r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
|
|
|
|
|
ret <4 x i32> %r
|
|
|
|
|
}
|
|
|
|
|
|
2018-07-05 21:16:46 +08:00
|
|
|
define i32 @sel_ifpos_fval_bigger(i32 %x) {
|
|
|
|
|
; CHECK-LABEL: sel_ifpos_fval_bigger:
|
|
|
|
|
; CHECK: # %bb.0:
|
[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)
This is almost the same as an existing IR canonicalization in instcombine,
so I'm assuming this is a good early generic DAG combine too.
The motivation comes from reduced bit-hacking for select-of-constants in IR
after rL331486. We want to restore that functionality in the DAG as noted in
the commit comments for that change and the llvm-dev discussion here:
http://lists.llvm.org/pipermail/llvm-dev/2018-July/124433.html
The PPC and AArch tests show that those targets are already doing something
similar. x86 will be neutral in the minimal case and generally better when
this pattern is extended with other ops as shown in the signbit-shift.ll tests.
Note the asymmetry: we don't include the (extend (ifneg X)) transform because
it already exists in SimplifySelectCC(), and that is verified in the later
unchanged tests in the signbit-shift.ll files. Without the 'not' op, the
general transform to use a shift is always a win because that's a single
instruction.
Alive proofs:
https://rise4fun.com/Alive/ysli
Name: if pos, get -1
%c = icmp sgt i16 %x, -1
%r = sext i1 %c to i16
=>
%n = xor i16 %x, -1
%r = ashr i16 %n, 15
Name: if pos, get 1
%c = icmp sgt i16 %x, -1
%r = zext i1 %c to i16
=>
%n = xor i16 %x, -1
%r = lshr i16 %n, 15
Differential Revision: https://reviews.llvm.org/D48970
llvm-svn: 337130
2018-07-16 00:27:07 +08:00
|
|
|
; CHECK-NEXT: notl %edi
|
|
|
|
|
; CHECK-NEXT: shrl $31, %edi
|
2018-07-05 21:16:46 +08:00
|
|
|
; CHECK-NEXT: movl $42, %eax
|
[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)
This is almost the same as an existing IR canonicalization in instcombine,
so I'm assuming this is a good early generic DAG combine too.
The motivation comes from reduced bit-hacking for select-of-constants in IR
after rL331486. We want to restore that functionality in the DAG as noted in
the commit comments for that change and the llvm-dev discussion here:
http://lists.llvm.org/pipermail/llvm-dev/2018-July/124433.html
The PPC and AArch tests show that those targets are already doing something
similar. x86 will be neutral in the minimal case and generally better when
this pattern is extended with other ops as shown in the signbit-shift.ll tests.
Note the asymmetry: we don't include the (extend (ifneg X)) transform because
it already exists in SimplifySelectCC(), and that is verified in the later
unchanged tests in the signbit-shift.ll files. Without the 'not' op, the
general transform to use a shift is always a win because that's a single
instruction.
Alive proofs:
https://rise4fun.com/Alive/ysli
Name: if pos, get -1
%c = icmp sgt i16 %x, -1
%r = sext i1 %c to i16
=>
%n = xor i16 %x, -1
%r = ashr i16 %n, 15
Name: if pos, get 1
%c = icmp sgt i16 %x, -1
%r = zext i1 %c to i16
=>
%n = xor i16 %x, -1
%r = lshr i16 %n, 15
Differential Revision: https://reviews.llvm.org/D48970
llvm-svn: 337130
2018-07-16 00:27:07 +08:00
|
|
|
; CHECK-NEXT: subl %edi, %eax
|
2018-07-05 21:16:46 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
|
%c = icmp sgt i32 %x, -1
|
|
|
|
|
%r = select i1 %c, i32 41, i32 42
|
|
|
|
|
ret i32 %r
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; If negative...
|
|
|
|
|
|
|
|
|
|
define i32 @zext_ifneg(i32 %x) {
|
|
|
|
|
; CHECK-LABEL: zext_ifneg:
|
|
|
|
|
; CHECK: # %bb.0:
|
|
|
|
|
; CHECK-NEXT: shrl $31, %edi
|
|
|
|
|
; CHECK-NEXT: movl %edi, %eax
|
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
|
%c = icmp slt i32 %x, 0
|
|
|
|
|
%r = zext i1 %c to i32
|
|
|
|
|
ret i32 %r
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @add_zext_ifneg(i32 %x) {
|
|
|
|
|
; CHECK-LABEL: add_zext_ifneg:
|
|
|
|
|
; CHECK: # %bb.0:
|
|
|
|
|
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
|
|
|
|
|
; CHECK-NEXT: shrl $31, %edi
|
|
|
|
|
; CHECK-NEXT: leal 41(%rdi), %eax
|
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
|
%c = icmp slt i32 %x, 0
|
|
|
|
|
%e = zext i1 %c to i32
|
|
|
|
|
%r = add i32 %e, 41
|
|
|
|
|
ret i32 %r
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @sel_ifneg_tval_bigger(i32 %x) {
|
|
|
|
|
; CHECK-LABEL: sel_ifneg_tval_bigger:
|
|
|
|
|
; CHECK: # %bb.0:
|
|
|
|
|
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
|
|
|
|
|
; CHECK-NEXT: shrl $31, %edi
|
|
|
|
|
; CHECK-NEXT: leal 41(%rdi), %eax
|
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
|
%c = icmp slt i32 %x, 0
|
|
|
|
|
%r = select i1 %c, i32 42, i32 41
|
|
|
|
|
ret i32 %r
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @sext_ifneg(i32 %x) {
|
|
|
|
|
; CHECK-LABEL: sext_ifneg:
|
|
|
|
|
; CHECK: # %bb.0:
|
|
|
|
|
; CHECK-NEXT: sarl $31, %edi
|
|
|
|
|
; CHECK-NEXT: movl %edi, %eax
|
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
|
%c = icmp slt i32 %x, 0
|
|
|
|
|
%r = sext i1 %c to i32
|
|
|
|
|
ret i32 %r
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @add_sext_ifneg(i32 %x) {
|
|
|
|
|
; CHECK-LABEL: add_sext_ifneg:
|
|
|
|
|
; CHECK: # %bb.0:
|
|
|
|
|
; CHECK-NEXT: shrl $31, %edi
|
|
|
|
|
; CHECK-NEXT: movl $42, %eax
|
|
|
|
|
; CHECK-NEXT: subl %edi, %eax
|
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
|
%c = icmp slt i32 %x, 0
|
|
|
|
|
%e = sext i1 %c to i32
|
|
|
|
|
%r = add i32 %e, 42
|
|
|
|
|
ret i32 %r
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @sel_ifneg_fval_bigger(i32 %x) {
|
|
|
|
|
; CHECK-LABEL: sel_ifneg_fval_bigger:
|
|
|
|
|
; CHECK: # %bb.0:
|
|
|
|
|
; CHECK-NEXT: shrl $31, %edi
|
|
|
|
|
; CHECK-NEXT: movl $42, %eax
|
|
|
|
|
; CHECK-NEXT: subl %edi, %eax
|
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
|
%c = icmp slt i32 %x, 0
|
|
|
|
|
%r = select i1 %c, i32 41, i32 42
|
|
|
|
|
ret i32 %r
|
|
|
|
|
}
|
|
|
|
|
|
2018-07-28 00:22:40 +08:00
|
|
|
define i32 @add_lshr_not(i32 %x) {
|
|
|
|
|
; CHECK-LABEL: add_lshr_not:
|
|
|
|
|
; CHECK: # %bb.0:
|
|
|
|
|
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
|
|
|
|
|
; CHECK-NEXT: notl %edi
|
|
|
|
|
; CHECK-NEXT: shrl $31, %edi
|
|
|
|
|
; CHECK-NEXT: leal 41(%rdi), %eax
|
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
|
%not = xor i32 %x, -1
|
|
|
|
|
%sh = lshr i32 %not, 31
|
|
|
|
|
%r = add i32 %sh, 41
|
|
|
|
|
ret i32 %r
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <4 x i32> @add_lshr_not_vec_splat(<4 x i32> %x) {
|
|
|
|
|
; CHECK-LABEL: add_lshr_not_vec_splat:
|
|
|
|
|
; CHECK: # %bb.0:
|
|
|
|
|
; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
|
|
|
|
|
; CHECK-NEXT: pxor %xmm1, %xmm0
|
|
|
|
|
; CHECK-NEXT: psrld $31, %xmm0
|
|
|
|
|
; CHECK-NEXT: por {{.*}}(%rip), %xmm0
|
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
|
%c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
|
|
|
|
|
%e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
|
|
|
|
|
%r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
|
|
|
|
|
ret <4 x i32> %r
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @sub_lshr_not(i32 %x) {
|
|
|
|
|
; CHECK-LABEL: sub_lshr_not:
|
|
|
|
|
; CHECK: # %bb.0:
|
|
|
|
|
; CHECK-NEXT: notl %edi
|
|
|
|
|
; CHECK-NEXT: shrl $31, %edi
|
|
|
|
|
; CHECK-NEXT: xorl $43, %edi
|
|
|
|
|
; CHECK-NEXT: movl %edi, %eax
|
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
|
%not = xor i32 %x, -1
|
|
|
|
|
%sh = lshr i32 %not, 31
|
|
|
|
|
%r = sub i32 43, %sh
|
|
|
|
|
ret i32 %r
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {
|
|
|
|
|
; CHECK-LABEL: sub_lshr_not_vec_splat:
|
|
|
|
|
; CHECK: # %bb.0:
|
|
|
|
|
; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
|
|
|
|
|
; CHECK-NEXT: pxor %xmm0, %xmm1
|
|
|
|
|
; CHECK-NEXT: psrld $31, %xmm1
|
|
|
|
|
; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [42,42,42,42]
|
|
|
|
|
; CHECK-NEXT: psubd %xmm1, %xmm0
|
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
|
%c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
|
|
|
|
|
%e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
|
|
|
|
|
%r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e
|
|
|
|
|
ret <4 x i32> %r
|
|
|
|
|
}
|
|
|
|
|
|