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DAG: Fix extract_subvector combine for a single element This would fail before because 1x vectors aren't legal, so instead just use the scalar type. Avoids regressions in a future AMDGPU commit to add v4i16/v4f16 as legal types. Test update is just the one test that this triggers on in tree now. It wasn't checking anything before. The result is completely changed since the selects are eliminated. Not sure if it's considered better or not. llvm-svn: 334440
2018-06-12 05:27:41 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=armv7-none-linux-gnueabi < %s | FileCheck %s
Fix PR15950 A bug in DAG Combiner about undef mask llvm-svn: 181682
2013-05-13 10:07:05 +08:00
define <3 x i64> @shuffle(i1 %dec1, i1 %dec0, <3 x i64> %b) {
DAG: Fix extract_subvector combine for a single element This would fail before because 1x vectors aren't legal, so instead just use the scalar type. Avoids regressions in a future AMDGPU commit to add v4i16/v4f16 as legal types. Test update is just the one test that this triggers on in tree now. It wasn't checking anything before. The result is completely changed since the selects are eliminated. Not sure if it's considered better or not. llvm-svn: 334440
2018-06-12 05:27:41 +08:00
; CHECK-LABEL: shuffle:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: tst r1, #1
; CHECK-NEXT: moveq r1, #0
; CHECK-NEXT: vmoveq d16, r1, r1
; CHECK-NEXT: vldrne d16, [sp]
; CHECK-NEXT: tst r2, #1
; CHECK-NEXT: moveq r1, #0
; CHECK-NEXT: vmoveq d18, r1, r1
; CHECK-NEXT: vldrne d18, [sp, #8]
; CHECK-NEXT: vorr d17, d18, d18
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: bx lr
Fix PR15950 A bug in DAG Combiner about undef mask llvm-svn: 181682
2013-05-13 10:07:05 +08:00
entry:
%.sink = select i1 %dec1, <3 x i64> %b, <3 x i64> zeroinitializer
%.sink15 = select i1 %dec0, <3 x i64> %b, <3 x i64> zeroinitializer
%vecinit7 = shufflevector <3 x i64> %.sink, <3 x i64> %.sink15, <3 x i32> <i32 0, i32 4, i32 undef>
ret <3 x i64> %vecinit7
}