2018-06-25 21:46:41 +08:00
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# RUN: llc -march=amdgcn -run-pass simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
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#
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# See bug http://llvm.org/PR33152 for details of the bug this test is checking
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# for.
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# This test will provoke a subrange join during simple register
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# coalescing. Withough a fix for PR33152 this causes an unreachable in SubRange
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# Join
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#
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# The lines where the problem exhibits are the last 2 copy instructions in the
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# BB (bb.25)
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#
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# GCN-LABEL: bb.6:
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# GCN: successors: %bb.7(0x{{[0-9]+}}), %bb.18(0x{{[0-9]+}})
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[AMDGPU] Extend buffer intrinsics with swizzling
Summary:
Extend cachepolicy operand in the new VMEM buffer intrinsics
to supply information whether the buffer data is swizzled.
Also, propagate this information to MIR.
Intrinsics updated:
int_amdgcn_raw_buffer_load
int_amdgcn_raw_buffer_load_format
int_amdgcn_raw_buffer_store
int_amdgcn_raw_buffer_store_format
int_amdgcn_raw_tbuffer_load
int_amdgcn_raw_tbuffer_store
int_amdgcn_struct_buffer_load
int_amdgcn_struct_buffer_load_format
int_amdgcn_struct_buffer_store
int_amdgcn_struct_buffer_store_format
int_amdgcn_struct_tbuffer_load
int_amdgcn_struct_tbuffer_store
Furthermore, disable merging of VMEM buffer instructions
in SI Load/Store optimizer, if the "swizzled" bit on the instruction
is on.
The default value of the bit is 0, meaning that data in buffer
is linear and buffer instructions can be merged.
There is no difference in the generated code with this commit.
However, in the future it will be expected that front-ends
use buffer intrinsics with correct "swizzled" bit set.
Reviewers: arsenm, nhaehnle, tpr
Reviewed By: nhaehnle
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68200
llvm-svn: 373491
2019-10-03 01:22:36 +08:00
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# GCN: %{{[0-9]+}}:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %{{[0-9]+}}, 0, 0, 0, 0, 0, 0, 0, implicit $exec
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2018-06-25 21:46:41 +08:00
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#
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--- |
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target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
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target triple = "amdgcn--amdpal"
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define amdgpu_ps void @main() #0 {
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ret void
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}
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attributes #0 = { "target-cpu"="gfx803" }
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...
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---
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name: main
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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S_CBRANCH_SCC0 %bb.2, implicit undef $scc
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bb.1:
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successors: %bb.9(0x80000000)
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%0:vreg_128 = IMPLICIT_DEF
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S_BRANCH %bb.9
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bb.2:
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successors: %bb.4(0x40000000), %bb.3(0x40000000)
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S_CBRANCH_SCC0 %bb.4, implicit undef $scc
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bb.3:
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successors: %bb.5(0x80000000)
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%1:vreg_128 = IMPLICIT_DEF
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S_BRANCH %bb.5
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bb.4:
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successors: %bb.6(0x80000000)
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%2:sreg_64 = S_MOV_B64 0
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%3:sreg_32_xm0 = S_MOV_B32 61440
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%4:sreg_32_xm0 = S_MOV_B32 -1
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%5:sreg_64 = COPY killed %2
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%6:vreg_128 = IMPLICIT_DEF
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S_BRANCH %bb.6
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bb.5:
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successors: %bb.9(0x80000000)
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%7:vreg_128 = COPY killed %1
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%8:vreg_128 = COPY killed %7
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%0:vreg_128 = COPY killed %8
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S_BRANCH %bb.9
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bb.6:
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successors: %bb.7(0x40000000), %bb.18(0x40000000)
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%9:vreg_128 = COPY killed %6
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%10:sreg_64 = COPY killed %5
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2019-10-10 15:11:33 +08:00
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undef %11.sub2:sgpr_128 = COPY %4
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%11.sub3:sgpr_128 = COPY %3
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[AMDGPU] Extend buffer intrinsics with swizzling
Summary:
Extend cachepolicy operand in the new VMEM buffer intrinsics
to supply information whether the buffer data is swizzled.
Also, propagate this information to MIR.
Intrinsics updated:
int_amdgcn_raw_buffer_load
int_amdgcn_raw_buffer_load_format
int_amdgcn_raw_buffer_store
int_amdgcn_raw_buffer_store_format
int_amdgcn_raw_tbuffer_load
int_amdgcn_raw_tbuffer_store
int_amdgcn_struct_buffer_load
int_amdgcn_struct_buffer_load_format
int_amdgcn_struct_buffer_store
int_amdgcn_struct_buffer_store_format
int_amdgcn_struct_tbuffer_load
int_amdgcn_struct_tbuffer_store
Furthermore, disable merging of VMEM buffer instructions
in SI Load/Store optimizer, if the "swizzled" bit on the instruction
is on.
The default value of the bit is 0, meaning that data in buffer
is linear and buffer instructions can be merged.
There is no difference in the generated code with this commit.
However, in the future it will be expected that front-ends
use buffer intrinsics with correct "swizzled" bit set.
Reviewers: arsenm, nhaehnle, tpr
Reviewed By: nhaehnle
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68200
llvm-svn: 373491
2019-10-03 01:22:36 +08:00
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%12:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET killed %11, 0, 0, 0, 0, 0, 0, 0, implicit $exec
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2018-06-25 21:46:41 +08:00
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undef %13.sub1:vreg_128 = COPY %9.sub1
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%13.sub2:vreg_128 = COPY %9.sub2
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%14:sreg_64 = V_CMP_GT_F32_e64 0, target-flags(amdgpu-rel32-lo) 0, 0, killed %12.sub3, 0, implicit $exec
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%15:vgpr_32 = V_ADD_F32_e32 1065353216, undef %16:vgpr_32, implicit $exec
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%17:sreg_64 = V_CMP_GT_F32_e64 0, 0, 0, killed %15, 0, implicit $exec
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%18:sreg_64 = S_AND_B64 killed %17, killed %14, implicit-def dead $scc
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%19:sreg_64 = COPY %10
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%20:vreg_128 = COPY %13
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%21:vreg_128 = IMPLICIT_DEF
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%22:sreg_64 = COPY $exec, implicit-def $exec
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%23:sreg_64 = S_AND_B64 %22, %18, implicit-def dead $scc
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%24:sreg_64 = S_XOR_B64 %23, %22, implicit-def dead $scc
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$exec = S_MOV_B64_term killed %23
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SI_MASK_BRANCH %bb.7, implicit $exec
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S_BRANCH %bb.18
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bb.7:
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successors: %bb.6(0x40000000), %bb.8(0x40000000)
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$exec = S_OR_B64 $exec, %24, implicit-def $scc
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%25:vreg_128 = COPY killed %21
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%26:vreg_128 = COPY killed %20
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%27:sreg_64 = COPY killed %19
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%28:sreg_64 = S_OR_B64 %24, killed %27, implicit-def dead $scc
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%5:sreg_64 = COPY %28
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%6:vreg_128 = COPY killed %25
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2019-03-28 00:58:22 +08:00
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$exec = S_ANDN2_B64_term $exec, %28, implicit-def $scc
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2018-06-25 21:46:41 +08:00
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S_CBRANCH_EXECNZ %bb.6, implicit $exec
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S_BRANCH %bb.8
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bb.8:
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successors: %bb.5(0x80000000)
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$exec = S_OR_B64 $exec, killed %28, implicit-def $scc
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%29:vreg_128 = COPY killed %26
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%1:vreg_128 = COPY killed %29
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S_BRANCH %bb.5
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bb.9:
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successors: %bb.10(0x80000000)
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%30:vreg_128 = COPY killed %0
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S_BRANCH %bb.10
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bb.10:
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successors: %bb.12(0x40000000), %bb.11(0x40000000)
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S_CBRANCH_SCC0 %bb.12, implicit undef $scc
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bb.11:
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successors: %bb.14(0x80000000)
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%31:vreg_128 = IMPLICIT_DEF
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S_BRANCH %bb.14
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bb.12:
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successors: %bb.13(0x80000000)
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S_CBRANCH_SCC1 %bb.13, implicit undef $scc
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S_BRANCH %bb.13
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bb.13:
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successors: %bb.14(0x80000000)
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%32:vgpr_32 = V_MUL_F32_e32 undef %33:vgpr_32, killed %30.sub1, implicit $exec
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%34:vgpr_32 = V_MUL_F32_e32 undef %35:vgpr_32, killed %32, implicit $exec
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undef %36.sub0:vreg_128 = COPY %34
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%31:vreg_128 = COPY killed %36
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bb.14:
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successors: %bb.16(0x40000000), %bb.15(0x40000000)
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%37:vreg_128 = COPY killed %31
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S_CBRANCH_SCC0 %bb.16, implicit undef $scc
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bb.15:
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successors: %bb.17(0x80000000)
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%38:vreg_128 = IMPLICIT_DEF
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S_BRANCH %bb.17
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bb.16:
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successors: %bb.17(0x80000000)
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%39:vgpr_32 = V_FMA_F32 0, undef %40:vgpr_32, 0, killed %37.sub0, 0, undef %41:vgpr_32, 0, 0, implicit $exec
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%42:vgpr_32 = V_FMA_F32 0, undef %43:vgpr_32, 0, undef %44:vgpr_32, 0, killed %39, 0, 0, implicit $exec
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%45:vgpr_32 = V_FMA_F32 0, undef %46:vgpr_32, 0, undef %47:vgpr_32, 0, killed %42, 0, 0, implicit $exec
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dead %48:vgpr_32 = V_MUL_F32_e32 undef %49:vgpr_32, killed %45, implicit $exec
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%50:vgpr_32 = V_MUL_F32_e32 undef %51:vgpr_32, undef %52:vgpr_32, implicit $exec
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undef %53.sub1:vreg_128 = COPY %50
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%38:vreg_128 = COPY killed %53
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bb.17:
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%54:vreg_128 = COPY killed %38
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%55:vgpr_32 = V_FMA_F32 0, killed %54.sub1, 0, target-flags(amdgpu-gotprel32-lo) 1056964608, 0, 1056964608, 0, 0, implicit $exec
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EXP 1, undef %56:vgpr_32, killed %55, undef %57:vgpr_32, undef %58:vgpr_32, -1, 0, 15, implicit $exec
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[AMDGPU] Add support for immediate operand for S_ENDPGM
Summary:
Add support for immediate operand in S_ENDPGM
Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6
Reviewers: alexshap
Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59213
llvm-svn: 355902
2019-03-12 17:52:58 +08:00
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S_ENDPGM 0
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2018-06-25 21:46:41 +08:00
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bb.18:
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successors: %bb.7(0x80000000)
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dead %59:vgpr_32 = V_FMA_F32 0, killed %9.sub2, 0, undef %60:vgpr_32, 0, undef %61:vgpr_32, 0, 0, implicit $exec
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2019-10-10 15:11:33 +08:00
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dead %62:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN undef %63:vgpr_32, undef %64:sgpr_128, undef %65:sreg_32, 0, 0, 0, 0, 0, 0, implicit $exec
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2018-06-25 21:46:41 +08:00
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undef %66.sub1:vreg_128 = COPY %13.sub1
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%66.sub2:vreg_128 = COPY %13.sub2
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%67:sreg_64 = V_CMP_NGT_F32_e64 0, 0, 0, undef %68:vgpr_32, 0, implicit $exec
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%69:vgpr_32 = V_ADD_F32_e32 1065353216, undef %70:vgpr_32, implicit $exec
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%71:vgpr_32 = V_ADD_F32_e32 1065353216, killed %69, implicit $exec
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%72:sreg_64 = V_CMP_NGT_F32_e64 0, 0, 0, killed %71, 0, implicit $exec
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%73:sreg_64 = S_OR_B64 killed %72, killed %67, implicit-def dead $scc
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%74:sreg_64 = S_OR_B64 killed %73, killed %10, implicit-def dead $scc
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%19:sreg_64 = COPY killed %74
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%20:vreg_128 = COPY %66
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%21:vreg_128 = COPY killed %66
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S_BRANCH %bb.7
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...
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