2008-09-22 09:08:49 +08:00
|
|
|
add_llvm_library(LLVMCodeGen
|
2009-10-27 03:32:42 +08:00
|
|
|
AggressiveAntiDepBreaker.cpp
|
2010-12-11 02:36:02 +08:00
|
|
|
AllocationOrder.cpp
|
2010-06-15 12:08:14 +08:00
|
|
|
Analysis.cpp
|
2014-08-22 05:50:01 +08:00
|
|
|
AtomicExpandPass.cpp
|
Switch TargetTransformInfo from an immutable analysis pass that requires
a TargetMachine to construct (and thus isn't always available), to an
analysis group that supports layered implementations much like
AliasAnalysis does. This is a pretty massive change, with a few parts
that I was unable to easily separate (sorry), so I'll walk through it.
The first step of this conversion was to make TargetTransformInfo an
analysis group, and to sink the nonce implementations in
ScalarTargetTransformInfo and VectorTargetTranformInfo into
a NoTargetTransformInfo pass. This allows other passes to add a hard
requirement on TTI, and assume they will always get at least on
implementation.
The TargetTransformInfo analysis group leverages the delegation chaining
trick that AliasAnalysis uses, where the base class for the analysis
group delegates to the previous analysis *pass*, allowing all but tho
NoFoo analysis passes to only implement the parts of the interfaces they
support. It also introduces a new trick where each pass in the group
retains a pointer to the top-most pass that has been initialized. This
allows passes to implement one API in terms of another API and benefit
when some other pass above them in the stack has more precise results
for the second API.
The second step of this conversion is to create a pass that implements
the TargetTransformInfo analysis using the target-independent
abstractions in the code generator. This replaces the
ScalarTargetTransformImpl and VectorTargetTransformImpl classes in
lib/Target with a single pass in lib/CodeGen called
BasicTargetTransformInfo. This class actually provides most of the TTI
functionality, basing it upon the TargetLowering abstraction and other
information in the target independent code generator.
The third step of the conversion adds support to all TargetMachines to
register custom analysis passes. This allows building those passes with
access to TargetLowering or other target-specific classes, and it also
allows each target to customize the set of analysis passes desired in
the pass manager. The baseline LLVMTargetMachine implements this
interface to add the BasicTTI pass to the pass manager, and all of the
tools that want to support target-aware TTI passes call this routine on
whatever target machine they end up with to add the appropriate passes.
The fourth step of the conversion created target-specific TTI analysis
passes for the X86 and ARM backends. These passes contain the custom
logic that was previously in their extensions of the
ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces.
I separated them into their own file, as now all of the interface bits
are private and they just expose a function to create the pass itself.
Then I extended these target machines to set up a custom set of analysis
passes, first adding BasicTTI as a fallback, and then adding their
customized TTI implementations.
The fourth step required logic that was shared between the target
independent layer and the specific targets to move to a different
interface, as they no longer derive from each other. As a consequence,
a helper functions were added to TargetLowering representing the common
logic needed both in the target implementation and the codegen
implementation of the TTI pass. While technically this is the only
change that could have been committed separately, it would have been
a nightmare to extract.
The final step of the conversion was just to delete all the old
boilerplate. This got rid of the ScalarTargetTransformInfo and
VectorTargetTransformInfo classes, all of the support in all of the
targets for producing instances of them, and all of the support in the
tools for manually constructing a pass based around them.
Now that TTI is a relatively normal analysis group, two things become
straightforward. First, we can sink it into lib/Analysis which is a more
natural layer for it to live. Second, clients of this interface can
depend on it *always* being available which will simplify their code and
behavior. These (and other) simplifications will follow in subsequent
commits, this one is clearly big enough.
Finally, I'm very aware that much of the comments and documentation
needs to be updated. As soon as I had this working, and plausibly well
commented, I wanted to get it committed and in front of the build bots.
I'll be doing a few passes over documentation later if it sticks.
Commits to update DragonEgg and Clang will be made presently.
llvm-svn: 171681
2013-01-07 09:37:14 +08:00
|
|
|
BasicTargetTransformInfo.cpp
|
2017-03-02 04:29:34 +08:00
|
|
|
BranchCoalescing.cpp
|
2008-09-22 09:08:49 +08:00
|
|
|
BranchFolding.cpp
|
2016-10-06 23:38:53 +08:00
|
|
|
BranchRelaxation.cpp
|
2016-01-19 11:57:18 +08:00
|
|
|
BuiltinGCs.cpp
|
2009-12-14 15:43:25 +08:00
|
|
|
CalcSpillWeights.cpp
|
2010-07-07 23:15:27 +08:00
|
|
|
CallingConvLower.cpp
|
2010-10-08 02:41:20 +08:00
|
|
|
CodeGen.cpp
|
2014-02-22 08:07:45 +08:00
|
|
|
CodeGenPrepare.cpp
|
2016-09-01 17:42:39 +08:00
|
|
|
CountingFunctionInserter.cpp
|
2009-10-27 00:59:04 +08:00
|
|
|
CriticalAntiDepBreaker.cpp
|
2013-01-12 04:05:37 +08:00
|
|
|
DeadMachineInstructionElim.cpp
|
2016-04-28 11:07:16 +08:00
|
|
|
DetectDeadLanes.cpp
|
2016-01-28 00:53:42 +08:00
|
|
|
DFAPacketizer.cpp
|
2009-05-23 04:36:31 +08:00
|
|
|
DwarfEHPrepare.cpp
|
2012-07-04 08:09:54 +08:00
|
|
|
EarlyIfConversion.cpp
|
2011-01-05 05:10:05 +08:00
|
|
|
EdgeBundles.cpp
|
2011-09-28 08:01:54 +08:00
|
|
|
ExecutionDepsFix.cpp
|
2010-11-19 02:45:06 +08:00
|
|
|
ExpandISelPseudos.cpp
|
2011-09-26 00:46:00 +08:00
|
|
|
ExpandPostRAPseudos.cpp
|
2017-05-10 17:42:49 +08:00
|
|
|
ExpandReductions.cpp
|
2015-06-16 02:44:08 +08:00
|
|
|
FaultMaps.cpp
|
2017-02-01 01:00:27 +08:00
|
|
|
FEntryInserter.cpp
|
2015-09-18 04:45:18 +08:00
|
|
|
FuncletLayout.cpp
|
2008-09-22 09:08:49 +08:00
|
|
|
GCMetadata.cpp
|
|
|
|
GCMetadataPrinter.cpp
|
2015-01-16 03:29:42 +08:00
|
|
|
GCRootLowering.cpp
|
2015-01-27 02:26:35 +08:00
|
|
|
GCStrategy.cpp
|
2014-06-14 06:57:59 +08:00
|
|
|
GlobalMerge.cpp
|
2008-09-22 09:08:49 +08:00
|
|
|
IfConversion.cpp
|
2015-06-16 02:44:27 +08:00
|
|
|
ImplicitNullChecks.cpp
|
2010-06-30 07:58:39 +08:00
|
|
|
InlineSpiller.cpp
|
2011-04-02 14:03:35 +08:00
|
|
|
InterferenceCache.cpp
|
[InterleavedAccess] Add a pass InterleavedAccess to identify interleaved memory accesses and transform into target specific intrinsics.
E.g. An interleaved load (Factor = 2):
%wide.vec = load <8 x i32>, <8 x i32>* %ptr
%v0 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <0, 2, 4, 6>
%v1 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <1, 3, 5, 7>
It can be transformed into a ld2 intrinsic in AArch64 backend or a vld2 intrinsic in ARM backend.
E.g. An interleaved store (Factor = 3):
%i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
store <12 x i32> %i.vec, <12 x i32>* %ptr
It can be transformed into a st3 intrinsic in AArch64 backend or a vst3 intrinsic in ARM backend.
Differential Revision: http://reviews.llvm.org/D10533
llvm-svn: 240751
2015-06-26 10:10:27 +08:00
|
|
|
InterleavedAccessPass.cpp
|
2008-09-22 09:08:49 +08:00
|
|
|
IntrinsicLowering.cpp
|
2008-11-20 07:18:57 +08:00
|
|
|
LatencyPriorityQueue.cpp
|
2017-02-15 01:21:09 +08:00
|
|
|
LazyMachineBlockFrequencyInfo.cpp
|
2011-08-11 03:04:06 +08:00
|
|
|
LexicalScopes.cpp
|
2016-01-28 00:53:42 +08:00
|
|
|
LiveDebugValues.cpp
|
2010-11-30 10:17:10 +08:00
|
|
|
LiveDebugVariables.cpp
|
2008-09-22 09:08:49 +08:00
|
|
|
LiveIntervalAnalysis.cpp
|
2016-01-28 00:53:42 +08:00
|
|
|
LiveInterval.cpp
|
2010-10-23 07:09:15 +08:00
|
|
|
LiveIntervalUnion.cpp
|
2016-01-28 00:53:42 +08:00
|
|
|
LivePhysRegs.cpp
|
2013-01-12 04:05:37 +08:00
|
|
|
LiveRangeCalc.cpp
|
|
|
|
LiveRangeEdit.cpp
|
Add LiveRangeShrink pass to shrink live range within BB.
Summary: LiveRangeShrink pass moves instruction right after the definition with the same BB if the instruction and its operands all have more than one use. This pass is inexpensive and guarantees optimal live-range within BB.
Reviewers: davidxl, wmi, hfinkel, MatzeB, andreadb
Reviewed By: MatzeB, andreadb
Subscribers: hiraditya, jyknight, sanjoy, skatkov, gberry, jholewinski, qcolombet, javed.absar, krytarowski, atrick, spatel, RKSimon, andreadb, MatzeB, mehdi_amini, mgorny, efriedma, davide, dberlin, llvm-commits
Differential Revision: https://reviews.llvm.org/D32563
llvm-svn: 304371
2017-06-01 07:25:25 +08:00
|
|
|
LiveRangeShrink.cpp
|
2012-06-09 10:13:10 +08:00
|
|
|
LiveRegMatrix.cpp
|
2017-01-20 08:16:14 +08:00
|
|
|
LiveRegUnits.cpp
|
2008-09-22 09:08:49 +08:00
|
|
|
LiveStackAnalysis.cpp
|
|
|
|
LiveVariables.cpp
|
2016-01-28 00:53:42 +08:00
|
|
|
LLVMTargetMachine.cpp
|
2010-08-14 09:55:09 +08:00
|
|
|
LocalStackSlotAllocation.cpp
|
2016-07-21 03:09:30 +08:00
|
|
|
LowLevelType.cpp
|
2016-01-14 07:56:37 +08:00
|
|
|
LowerEmuTLS.cpp
|
2008-09-22 09:08:49 +08:00
|
|
|
MachineBasicBlock.cpp
|
2011-07-26 03:25:40 +08:00
|
|
|
MachineBlockFrequencyInfo.cpp
|
Implement a block placement pass based on the branch probability and
block frequency analyses. This differs substantially from the existing
block-placement pass in LLVM:
1) It operates on the Machine-IR in the CodeGen layer. This exposes much
more (and more precise) information and opportunities. Also, the
results are more stable due to fewer transforms ocurring after the
pass runs.
2) It uses the generalized probability and frequency analyses. These can
model static heuristics, code annotation derived heuristics as well
as eventual profile loading. By basing the optimization on the
analysis interface it can work from any (or a combination) of these
inputs.
3) It uses a more aggressive algorithm, both building chains from tho
bottom up to maximize benefit, and using an SCC-based walk to layout
chains of blocks in a profitable ordering without O(N^2) iterations
which the old pass involves.
The pass is currently gated behind a flag, and not enabled by default
because it still needs to grow some important features. Most notably, it
needs to support loop aligning and careful layout of loop structures
much as done by hand currently in CodePlacementOpt. Once it supports
these, and has sufficient testing and quality tuning, it should replace
both of these passes.
Thanks to Nick Lewycky and Richard Smith for help authoring & debugging
this, and to Jakob, Andy, Eric, Jim, and probably a few others I'm
forgetting for reviewing and answering all my questions. Writing
a backend pass is *sooo* much better now than it used to be. =D
llvm-svn: 142641
2011-10-21 14:46:38 +08:00
|
|
|
MachineBlockPlacement.cpp
|
2011-06-17 04:22:37 +08:00
|
|
|
MachineBranchProbabilityInfo.cpp
|
2014-08-04 05:35:39 +08:00
|
|
|
MachineCombiner.cpp
|
2012-01-07 11:02:36 +08:00
|
|
|
MachineCopyPropagation.cpp
|
2016-01-28 00:53:42 +08:00
|
|
|
MachineCSE.cpp
|
2014-07-13 05:59:52 +08:00
|
|
|
MachineDominanceFrontier.cpp
|
2016-01-28 00:53:42 +08:00
|
|
|
MachineDominators.cpp
|
2017-04-27 07:36:58 +08:00
|
|
|
MachineFrameInfo.cpp
|
2016-01-28 00:53:42 +08:00
|
|
|
MachineFunction.cpp
|
2009-08-01 02:50:22 +08:00
|
|
|
MachineFunctionPass.cpp
|
2010-04-03 07:17:14 +08:00
|
|
|
MachineFunctionPrinterPass.cpp
|
2011-12-14 11:50:53 +08:00
|
|
|
MachineInstrBundle.cpp
|
2016-01-28 00:53:42 +08:00
|
|
|
MachineInstr.cpp
|
2008-09-22 09:08:49 +08:00
|
|
|
MachineLICM.cpp
|
|
|
|
MachineLoopInfo.cpp
|
|
|
|
MachineModuleInfo.cpp
|
2009-09-16 18:18:36 +08:00
|
|
|
MachineModuleInfoImpls.cpp
|
2017-01-26 07:20:33 +08:00
|
|
|
MachineOptimizationRemarkEmitter.cpp
|
2017-03-07 05:31:18 +08:00
|
|
|
MachineOutliner.cpp
|
2008-09-22 09:08:49 +08:00
|
|
|
MachinePassRegistry.cpp
|
2016-07-30 00:44:44 +08:00
|
|
|
MachinePipeliner.cpp
|
2013-01-12 04:05:37 +08:00
|
|
|
MachinePostDominators.cpp
|
2014-07-20 02:29:29 +08:00
|
|
|
MachineRegionInfo.cpp
|
2016-01-28 00:53:42 +08:00
|
|
|
MachineRegisterInfo.cpp
|
2012-01-13 14:30:30 +08:00
|
|
|
MachineScheduler.cpp
|
2010-01-13 09:02:47 +08:00
|
|
|
MachineSink.cpp
|
2016-01-28 00:53:42 +08:00
|
|
|
MachineSSAUpdater.cpp
|
2012-07-27 02:38:11 +08:00
|
|
|
MachineTraceMetrics.cpp
|
2009-05-16 08:33:53 +08:00
|
|
|
MachineVerifier.cpp
|
2016-04-19 13:24:47 +08:00
|
|
|
PatchableFunction.cpp
|
2015-06-16 07:52:35 +08:00
|
|
|
MIRPrinter.cpp
|
2015-05-28 02:02:19 +08:00
|
|
|
MIRPrintingPass.cpp
|
2017-06-19 20:53:31 +08:00
|
|
|
MacroFusion.cpp
|
2010-02-12 09:30:21 +08:00
|
|
|
OptimizePHIs.cpp
|
2015-08-28 07:37:36 +08:00
|
|
|
ParallelCG.cpp
|
2010-08-10 13:16:06 +08:00
|
|
|
PeepholeOptimizer.cpp
|
2016-01-28 00:53:42 +08:00
|
|
|
PHIElimination.cpp
|
|
|
|
PHIEliminationUtils.cpp
|
2016-04-22 22:43:50 +08:00
|
|
|
PostRAHazardRecognizer.cpp
|
2008-09-22 09:08:49 +08:00
|
|
|
PostRASchedulerList.cpp
|
2016-04-23 05:18:02 +08:00
|
|
|
PreISelIntrinsicLowering.cpp
|
2009-11-04 09:32:06 +08:00
|
|
|
ProcessImplicitDefs.cpp
|
2008-09-22 09:08:49 +08:00
|
|
|
PrologEpilogInserter.cpp
|
|
|
|
PseudoSourceValue.cpp
|
2012-01-12 06:28:30 +08:00
|
|
|
RegAllocBase.cpp
|
2010-10-23 07:09:15 +08:00
|
|
|
RegAllocBasic.cpp
|
2010-04-22 02:02:42 +08:00
|
|
|
RegAllocFast.cpp
|
2010-12-08 11:26:16 +08:00
|
|
|
RegAllocGreedy.cpp
|
2008-10-05 05:18:50 +08:00
|
|
|
RegAllocPBQP.cpp
|
2011-06-02 10:19:35 +08:00
|
|
|
RegisterClassInfo.cpp
|
2008-09-22 09:08:49 +08:00
|
|
|
RegisterCoalescer.cpp
|
2012-04-25 02:06:49 +08:00
|
|
|
RegisterPressure.cpp
|
2008-09-22 09:08:49 +08:00
|
|
|
RegisterScavenging.cpp
|
2016-06-01 06:38:06 +08:00
|
|
|
RenameIndependentSubregs.cpp
|
2016-06-11 00:19:46 +08:00
|
|
|
RegisterUsageInfo.cpp
|
|
|
|
RegUsageInfoCollector.cpp
|
2016-06-11 02:37:21 +08:00
|
|
|
RegUsageInfoPropagate.cpp
|
2016-08-27 08:18:31 +08:00
|
|
|
ResetMachineFunctionPass.cpp
|
2016-01-28 00:53:42 +08:00
|
|
|
SafeStack.cpp
|
2016-06-30 04:37:43 +08:00
|
|
|
SafeStackColoring.cpp
|
|
|
|
SafeStackLayout.cpp
|
2017-05-15 19:30:54 +08:00
|
|
|
ScalarizeMaskedMemIntrin.cpp
|
2008-11-20 07:18:57 +08:00
|
|
|
ScheduleDAG.cpp
|
|
|
|
ScheduleDAGInstrs.cpp
|
|
|
|
ScheduleDAGPrinter.cpp
|
2011-01-10 05:31:39 +08:00
|
|
|
ScoreboardHazardRecognizer.cpp
|
2015-01-29 03:28:03 +08:00
|
|
|
ShadowStackGCLowering.cpp
|
2016-01-28 00:53:42 +08:00
|
|
|
ShrinkWrap.cpp
|
2009-08-18 02:47:11 +08:00
|
|
|
SjLjEHPrepare.cpp
|
2009-11-04 09:32:06 +08:00
|
|
|
SlotIndexes.cpp
|
2011-01-06 09:21:53 +08:00
|
|
|
SpillPlacement.cpp
|
2010-07-20 23:41:07 +08:00
|
|
|
SplitKit.cpp
|
2013-01-12 04:05:37 +08:00
|
|
|
StackColoring.cpp
|
2013-12-14 14:53:06 +08:00
|
|
|
StackMapLivenessAnalysis.cpp
|
2013-11-01 06:11:56 +08:00
|
|
|
StackMaps.cpp
|
2016-01-28 00:53:42 +08:00
|
|
|
StackProtector.cpp
|
|
|
|
StackSlotColoring.cpp
|
2009-11-26 08:32:21 +08:00
|
|
|
TailDuplication.cpp
|
2016-04-09 04:35:01 +08:00
|
|
|
TailDuplicator.cpp
|
2011-12-16 06:58:58 +08:00
|
|
|
TargetFrameLoweringImpl.cpp
|
2012-11-28 10:35:09 +08:00
|
|
|
TargetInstrInfo.cpp
|
2013-01-12 04:05:37 +08:00
|
|
|
TargetLoweringBase.cpp
|
2010-02-16 06:55:13 +08:00
|
|
|
TargetLoweringObjectFileImpl.cpp
|
2011-12-16 06:58:58 +08:00
|
|
|
TargetOptionsImpl.cpp
|
2016-05-10 11:21:59 +08:00
|
|
|
TargetPassConfig.cpp
|
2012-11-28 10:35:09 +08:00
|
|
|
TargetRegisterInfo.cpp
|
2012-09-15 04:26:46 +08:00
|
|
|
TargetSchedule.cpp
|
2016-11-23 06:09:03 +08:00
|
|
|
TargetSubtargetInfo.cpp
|
2008-09-22 09:08:49 +08:00
|
|
|
TwoAddressInstructionPass.cpp
|
|
|
|
UnreachableBlockElim.cpp
|
|
|
|
VirtRegMap.cpp
|
2015-01-29 08:41:44 +08:00
|
|
|
WinEHPrepare.cpp
|
XRay: Add entry and exit sleds
Summary:
In this patch we implement the following parts of XRay:
- Supporting a function attribute named 'function-instrument' which currently only supports 'xray-always'. We should be able to use this attribute for other instrumentation approaches.
- Supporting a function attribute named 'xray-instruction-threshold' used to determine whether a function is instrumented with a minimum number of instructions (IR instruction counts).
- X86-specific nop sleds as described in the white paper.
- A machine function pass that adds the different instrumentation marker instructions at a very late stage.
- A way of identifying which return opcode is considered "normal" for each architecture.
There are some caveats here:
1) We don't handle PATCHABLE_RET in platforms other than x86_64 yet -- this means if IR used PATCHABLE_RET directly instead of a normal ret, instruction lowering for that platform might do the wrong thing. We think this should be handled at instruction selection time to by default be unpacked for platforms where XRay is not availble yet.
2) The generated section for X86 is different from what is described from the white paper for the sole reason that LLVM allows us to do this neatly. We're taking the opportunity to deviate from the white paper from this perspective to allow us to get richer information from the runtime library.
Reviewers: sanjoy, eugenis, kcc, pcc, echristo, rnk
Subscribers: niravd, majnemer, atrick, rnk, emaste, bmakam, mcrosier, mehdi_amini, llvm-commits
Differential Revision: http://reviews.llvm.org/D19904
llvm-svn: 275367
2016-07-14 12:06:33 +08:00
|
|
|
XRayInstrumentation.cpp
|
2015-02-11 11:28:02 +08:00
|
|
|
|
|
|
|
ADDITIONAL_HEADER_DIRS
|
|
|
|
${LLVM_MAIN_INCLUDE_DIR}/llvm/CodeGen
|
|
|
|
${LLVM_MAIN_INCLUDE_DIR}/llvm/CodeGen/PBQP
|
2015-08-30 06:34:34 +08:00
|
|
|
|
2017-02-10 09:59:20 +08:00
|
|
|
LINK_LIBS ${LLVM_PTHREAD_LIB}
|
2011-02-19 06:06:14 +08:00
|
|
|
|
2016-11-17 12:36:50 +08:00
|
|
|
DEPENDS
|
|
|
|
intrinsics_gen
|
|
|
|
)
|
2012-06-24 21:32:01 +08:00
|
|
|
|
2011-02-19 06:06:14 +08:00
|
|
|
add_subdirectory(SelectionDAG)
|
|
|
|
add_subdirectory(AsmPrinter)
|
2015-05-28 02:02:19 +08:00
|
|
|
add_subdirectory(MIRParser)
|
2016-02-12 03:18:27 +08:00
|
|
|
add_subdirectory(GlobalISel)
|