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llvm-project/llvm/test/CodeGen/X86/vec_insert-3.ll

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[X86][SSE] Regenerated the vec_insert tests. llvm-svn: 265179
2016-04-02 03:42:23 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2,-sse4.1 | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2,-sse4.1 | FileCheck %s --check-prefix=X64
Use shuffles to implement insert_vector_elt for i32, i64, f32, and f64. llvm-svn: 44929
2007-12-12 15:55:34 +08:00
Implement vector shift up / down and insert zero with ps{rl}lq / ps{rl}ldq. llvm-svn: 51667
2008-05-29 16:22:04 +08:00
define <2 x i64> @t1(i64 %s, <2 x i64> %tmp) nounwind {
[X86][SSE] Regenerated the vec_insert tests. llvm-svn: 265179
2016-04-02 03:42:23 +08:00
; X32-LABEL: t1:
; X32: # BB#0:
[X86][SSE] Fix domains for VZEXT_LOAD type instructions Add the missing domain equivalences for movss, movsd, movd and movq zero extending loading instructions. Differential Revision: https://reviews.llvm.org/D27684 llvm-svn: 289825
2016-12-16 00:05:29 +08:00
; X32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
[X86][SSE] Regenerated the vec_insert tests. llvm-svn: 265179
2016-04-02 03:42:23 +08:00
; X32-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
; X32-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
[X86][SSE] Fix domains for VZEXT_LOAD type instructions Add the missing domain equivalences for movss, movsd, movd and movq zero extending loading instructions. Differential Revision: https://reviews.llvm.org/D27684 llvm-svn: 289825
2016-12-16 00:05:29 +08:00
; X32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
[X86][SSE] Regenerated the vec_insert tests. llvm-svn: 265179
2016-04-02 03:42:23 +08:00
; X32-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
; X32-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
; X32-NEXT: retl
;
; X64-LABEL: t1:
; X64: # BB#0:
; X64-NEXT: movd %rdi, %xmm1
; X64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; X64-NEXT: retq
fixed test to use FileCheck llvm-svn: 231519
2015-03-07 05:16:15 +08:00
%tmp1 = insertelement <2 x i64> %tmp, i64 %s, i32 1
ret <2 x i64> %tmp1
Use shuffles to implement insert_vector_elt for i32, i64, f32, and f64. llvm-svn: 44929
2007-12-12 15:55:34 +08:00
}