maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/X86/twoaddr-lea.ll

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

104 lines
2.6 KiB
LLVM
Raw Normal View History

Add some tests and update an existing test to reflect recent x86 isel peeps. llvm-svn: 92509
2010-01-05 04:53:54 +08:00
;; X's live range extends beyond the shift, so the register allocator
;; cannot coalesce it with Y. Because of this, a copy needs to be
;; emitted before the shift to save the register value before it is
;; clobbered. However, this copy is not needed if the register
;; allocator turns the shift into an LEA. This also occurs for ADD.
; Check that the shift gets turned into an LEA.
Instruction scheduling itinerary for Intel Atom. Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558
2012-02-02 07:20:51 +08:00
; RUN: llc < %s -mcpu=generic -mtriple=x86_64-apple-darwin | FileCheck %s
Add some tests and update an existing test to reflect recent x86 isel peeps. llvm-svn: 92509
2010-01-05 04:53:54 +08:00
After 3-addressifying a two-address instruction, update the register maps; add a missing check when considering whether it's profitable to commute. rdar://8977508. llvm-svn: 125259
2011-02-10 10:20:55 +08:00
@G = external global i32
Add some tests and update an existing test to reflect recent x86 isel peeps. llvm-svn: 92509
2010-01-05 04:53:54 +08:00
After 3-addressifying a two-address instruction, update the register maps; add a missing check when considering whether it's profitable to commute. rdar://8977508. llvm-svn: 125259
2011-02-10 10:20:55 +08:00
define i32 @test1(i32 %X) nounwind {
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
2013-07-14 04:38:47 +08:00
; CHECK-LABEL: test1:
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; CHECK: movl %edi, %eax
; CHECK: leal 1(%rax)
After 3-addressifying a two-address instruction, update the register maps; add a missing check when considering whether it's profitable to commute. rdar://8977508. llvm-svn: 125259
2011-02-10 10:20:55 +08:00
%Z = add i32 %X, 1
Upgrade syntax of tests using volatile instructions to use 'load volatile' instead of 'volatile load', which is archaic. llvm-svn: 145171
2011-11-27 14:54:59 +08:00
store volatile i32 %Z, i32* @G
Add some tests and update an existing test to reflect recent x86 isel peeps. llvm-svn: 92509
2010-01-05 04:53:54 +08:00
ret i32 %X
}
After 3-addressifying a two-address instruction, update the register maps; add a missing check when considering whether it's profitable to commute. rdar://8977508. llvm-svn: 125259
2011-02-10 10:20:55 +08:00
; rdar://8977508
; The second add should not be transformed to leal nor should it be
; commutted (which would require inserting a copy).
define i32 @test2(i32 inreg %a, i32 inreg %b, i32 %c, i32 %d) nounwind {
entry:
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
2013-07-14 04:38:47 +08:00
; CHECK-LABEL: test2:
After 3-addressifying a two-address instruction, update the register maps; add a missing check when considering whether it's profitable to commute. rdar://8977508. llvm-svn: 125259
2011-02-10 10:20:55 +08:00
; CHECK: leal
[TwoAddressInstructionPass] Try 3 Addr Conversion After Commuting. TwoAddressInstructionPass stops after a successful commuting but 3 Addr conversion might be good for some cases. Consider: int foo(int a, int b) { return a + b; } Before this commit, we emit: addl %esi, %edi movl %edi, %eax ret After this commit, we try 3 Addr conversion: leal (%rsi,%rdi), %eax ret Patch by Volkan Keles <vkeles@apple.com>! Differential Revision: http://reviews.llvm.org/D10851 llvm-svn: 241206
2015-07-02 07:12:13 +08:00
; CHECK-NEXT: addl
After 3-addressifying a two-address instruction, update the register maps; add a missing check when considering whether it's profitable to commute. rdar://8977508. llvm-svn: 125259
2011-02-10 10:20:55 +08:00
; CHECK-NEXT: addl
; CHECK-NEXT: ret
%add = add i32 %b, %a
%add3 = add i32 %add, %c
%add5 = add i32 %add3, %d
ret i32 %add5
Add some tests and update an existing test to reflect recent x86 isel peeps. llvm-svn: 92509
2010-01-05 04:53:54 +08:00
}
Catch more cases where 2-address pass should 3-addressify instructions. rdar://9002648. llvm-svn: 126811
2011-03-02 09:08:17 +08:00
; rdar://9002648
define i64 @test3(i64 %x) nounwind readnone ssp {
entry:
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
2013-07-14 04:38:47 +08:00
; CHECK-LABEL: test3:
Catch more cases where 2-address pass should 3-addressify instructions. rdar://9002648. llvm-svn: 126811
2011-03-02 09:08:17 +08:00
; CHECK: leaq (%rdi,%rdi), %rax
; CHECK-NOT: addq
; CHECK-NEXT: ret
%0 = shl i64 %x, 1
ret i64 %0
}
X86InstrInfo: Update liveness in classifyLea() We need to update liveness information when we create COPYs in classifyLea(). This fixes http://llvm.org/28301 llvm-svn: 278086
2016-08-09 09:47:26 +08:00
@global = external global i32, align 4
@global2 = external global i64, align 8
; Test that liveness is properly updated and we do not encounter the
; assert/crash from http://llvm.org/PR28301
; CHECK-LABEL: ham
define void @ham() {
bb:
br label %bb1
bb1:
%tmp = phi i64 [ %tmp40, %bb9 ], [ 0, %bb ]
%tmp2 = phi i32 [ %tmp39, %bb9 ], [ 0, %bb ]
%tmp3 = icmp sgt i32 undef, 10
br i1 %tmp3, label %bb2, label %bb3
bb2:
%tmp6 = load i32, i32* @global, align 4
%tmp8 = add nsw i32 %tmp6, %tmp2
%tmp9 = sext i32 %tmp8 to i64
br label %bb6
bb3:
; CHECK: subl %e[[REG0:[a-z0-9]+]],
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly. INC/DEC is really a special case of a more generic issue. We should also turn leas into add reg/reg or add reg/imm regardless of the slow lea flags. This also supports LEA64_32 which has 64 bit input registers and 32 bit output registers. So we need to convert the 64 bit inputs to their 32 bit equivalents to check if they are equal to base reg. One thing to note, the original code preserved the kill flags by adding operands to the new instruction instead of using addReg. But I think tied operands aren't supposed to have the kill flag set. I dropped the kill flags, but I could probably try to preserve it in the add reg/reg case if we think its important. Not sure which operand its supposed to go on for the LEA64_32r instruction due to the super reg implicit uses. Though I'm also not sure those are needed since they were probably just created by an INSERT_SUBREG from a 32-bit input. Differential Revision: https://reviews.llvm.org/D61472 llvm-svn: 361691
2019-05-25 14:17:47 +08:00
; CHECK: addq $4, %r[[REG0]]
X86InstrInfo: Update liveness in classifyLea() We need to update liveness information when we create COPYs in classifyLea(). This fixes http://llvm.org/28301 llvm-svn: 278086
2016-08-09 09:47:26 +08:00
%tmp14 = phi i64 [ %tmp15, %bb5 ], [ 0, %bb1 ]
%tmp15 = add nuw i64 %tmp14, 4
%tmp16 = trunc i64 %tmp14 to i32
%tmp17 = sub i32 %tmp2, %tmp16
br label %bb4
bb4:
%tmp20 = phi i64 [ %tmp14, %bb3 ], [ %tmp34, %bb5 ]
%tmp28 = icmp eq i32 %tmp17, 0
br i1 %tmp28, label %bb5, label %bb8
bb5:
%tmp34 = add nuw nsw i64 %tmp20, 1
%tmp35 = icmp slt i64 %tmp34, %tmp15
br i1 %tmp35, label %bb4, label %bb3
bb6:
store volatile i64 %tmp, i64* @global2, align 8
store volatile i64 %tmp9, i64* @global2, align 8
store volatile i32 %tmp6, i32* @global, align 4
%tmp45 = icmp slt i32 undef, undef
br i1 %tmp45, label %bb6, label %bb9
bb8:
unreachable
bb9:
%tmp39 = add nuw nsw i32 %tmp2, 4
%tmp40 = add nuw i64 %tmp, 4
br label %bb1
}