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llvm-project/llvm/test/CodeGen/X86/sse3-intrinsics-x86.ll

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[AVX-512] Add -show-mc-encoding to legacy vector intrinsic tests so we can see when VEX or EVEX encoded instructions are being emitted. Make sure the tests all have an avx2 command line and an skx command line. llvm-svn: 286055
2016-11-06 10:03:58 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary llvm-svn: 333831
2018-06-03 02:41:46 +08:00
; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse3 -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X86,SSE,X86-SSE
; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X86,AVX,X86-AVX,AVX1,X86-AVX1
; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X86,AVX,X86-AVX,AVX512,X86-AVX512
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse3 -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X64,SSE,X64-SSE
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X64,AVX,X64-AVX,AVX1,X64-AVX1
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X64,AVX,X64-AVX,AVX512,X64-AVX512
Add tests for SSE intrinsics in non-avx mode by copying from the AVX test cases. Some of these may have been tested by other tests, but most weren't. Patch by Cameron McInally. llvm-svn: 193309
2013-10-24 14:45:13 +08:00
define <2 x double> @test_x86_sse3_addsub_pd(<2 x double> %a0, <2 x double> %a1) {
[AVX-512] Add -show-mc-encoding to legacy vector intrinsic tests so we can see when VEX or EVEX encoded instructions are being emitted. Make sure the tests all have an avx2 command line and an skx command line. llvm-svn: 286055
2016-11-06 10:03:58 +08:00
; SSE-LABEL: test_x86_sse3_addsub_pd:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SSE: ## %bb.0:
[AVX-512] Add -show-mc-encoding to legacy vector intrinsic tests so we can see when VEX or EVEX encoded instructions are being emitted. Make sure the tests all have an avx2 command line and an skx command line. llvm-svn: 286055
2016-11-06 10:03:58 +08:00
; SSE-NEXT: addsubpd %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xd0,0xc1]
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary llvm-svn: 333831
2018-06-03 02:41:46 +08:00
; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
[AVX-512] Add -show-mc-encoding to legacy vector intrinsic tests so we can see when VEX or EVEX encoded instructions are being emitted. Make sure the tests all have an avx2 command line and an skx command line. llvm-svn: 286055
2016-11-06 10:03:58 +08:00
;
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary llvm-svn: 333831
2018-06-03 02:41:46 +08:00
; AVX-LABEL: test_x86_sse3_addsub_pd:
; AVX: ## %bb.0:
; AVX-NEXT: vaddsubpd %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xd0,0xc1]
; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
Add tests for SSE intrinsics in non-avx mode by copying from the AVX test cases. Some of these may have been tested by other tests, but most weren't. Patch by Cameron McInally. llvm-svn: 193309
2013-10-24 14:45:13 +08:00
%res = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
ret <2 x double> %res
}
declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>) nounwind readnone
define <4 x float> @test_x86_sse3_addsub_ps(<4 x float> %a0, <4 x float> %a1) {
[AVX-512] Add -show-mc-encoding to legacy vector intrinsic tests so we can see when VEX or EVEX encoded instructions are being emitted. Make sure the tests all have an avx2 command line and an skx command line. llvm-svn: 286055
2016-11-06 10:03:58 +08:00
; SSE-LABEL: test_x86_sse3_addsub_ps:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SSE: ## %bb.0:
[AVX-512] Add -show-mc-encoding to legacy vector intrinsic tests so we can see when VEX or EVEX encoded instructions are being emitted. Make sure the tests all have an avx2 command line and an skx command line. llvm-svn: 286055
2016-11-06 10:03:58 +08:00
; SSE-NEXT: addsubps %xmm1, %xmm0 ## encoding: [0xf2,0x0f,0xd0,0xc1]
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary llvm-svn: 333831
2018-06-03 02:41:46 +08:00
; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
[AVX-512] Add -show-mc-encoding to legacy vector intrinsic tests so we can see when VEX or EVEX encoded instructions are being emitted. Make sure the tests all have an avx2 command line and an skx command line. llvm-svn: 286055
2016-11-06 10:03:58 +08:00
;
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary llvm-svn: 333831
2018-06-03 02:41:46 +08:00
; AVX-LABEL: test_x86_sse3_addsub_ps:
; AVX: ## %bb.0:
; AVX-NEXT: vaddsubps %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0xd0,0xc1]
; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
Add tests for SSE intrinsics in non-avx mode by copying from the AVX test cases. Some of these may have been tested by other tests, but most weren't. Patch by Cameron McInally. llvm-svn: 193309
2013-10-24 14:45:13 +08:00
%res = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
ret <4 x float> %res
}
declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>) nounwind readnone
define <2 x double> @test_x86_sse3_hadd_pd(<2 x double> %a0, <2 x double> %a1) {
[AVX-512] Add -show-mc-encoding to legacy vector intrinsic tests so we can see when VEX or EVEX encoded instructions are being emitted. Make sure the tests all have an avx2 command line and an skx command line. llvm-svn: 286055
2016-11-06 10:03:58 +08:00
; SSE-LABEL: test_x86_sse3_hadd_pd:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SSE: ## %bb.0:
[AVX-512] Add -show-mc-encoding to legacy vector intrinsic tests so we can see when VEX or EVEX encoded instructions are being emitted. Make sure the tests all have an avx2 command line and an skx command line. llvm-svn: 286055
2016-11-06 10:03:58 +08:00
; SSE-NEXT: haddpd %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x7c,0xc1]
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary llvm-svn: 333831
2018-06-03 02:41:46 +08:00
; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
[AVX-512] Add -show-mc-encoding to legacy vector intrinsic tests so we can see when VEX or EVEX encoded instructions are being emitted. Make sure the tests all have an avx2 command line and an skx command line. llvm-svn: 286055
2016-11-06 10:03:58 +08:00
;
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary llvm-svn: 333831
2018-06-03 02:41:46 +08:00
; AVX-LABEL: test_x86_sse3_hadd_pd:
; AVX: ## %bb.0:
; AVX-NEXT: vhaddpd %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x7c,0xc1]
; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
Add tests for SSE intrinsics in non-avx mode by copying from the AVX test cases. Some of these may have been tested by other tests, but most weren't. Patch by Cameron McInally. llvm-svn: 193309
2013-10-24 14:45:13 +08:00
%res = call <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
ret <2 x double> %res
}
declare <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double>, <2 x double>) nounwind readnone
define <4 x float> @test_x86_sse3_hadd_ps(<4 x float> %a0, <4 x float> %a1) {
[AVX-512] Add -show-mc-encoding to legacy vector intrinsic tests so we can see when VEX or EVEX encoded instructions are being emitted. Make sure the tests all have an avx2 command line and an skx command line. llvm-svn: 286055
2016-11-06 10:03:58 +08:00
; SSE-LABEL: test_x86_sse3_hadd_ps:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SSE: ## %bb.0:
[AVX-512] Add -show-mc-encoding to legacy vector intrinsic tests so we can see when VEX or EVEX encoded instructions are being emitted. Make sure the tests all have an avx2 command line and an skx command line. llvm-svn: 286055
2016-11-06 10:03:58 +08:00
; SSE-NEXT: haddps %xmm1, %xmm0 ## encoding: [0xf2,0x0f,0x7c,0xc1]
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary llvm-svn: 333831
2018-06-03 02:41:46 +08:00
; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
[AVX-512] Add -show-mc-encoding to legacy vector intrinsic tests so we can see when VEX or EVEX encoded instructions are being emitted. Make sure the tests all have an avx2 command line and an skx command line. llvm-svn: 286055
2016-11-06 10:03:58 +08:00
;
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary llvm-svn: 333831
2018-06-03 02:41:46 +08:00
; AVX-LABEL: test_x86_sse3_hadd_ps:
; AVX: ## %bb.0:
; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x7c,0xc1]
; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
Add tests for SSE intrinsics in non-avx mode by copying from the AVX test cases. Some of these may have been tested by other tests, but most weren't. Patch by Cameron McInally. llvm-svn: 193309
2013-10-24 14:45:13 +08:00
%res = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
ret <4 x float> %res
}
declare <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float>, <4 x float>) nounwind readnone
define <2 x double> @test_x86_sse3_hsub_pd(<2 x double> %a0, <2 x double> %a1) {
[AVX-512] Add -show-mc-encoding to legacy vector intrinsic tests so we can see when VEX or EVEX encoded instructions are being emitted. Make sure the tests all have an avx2 command line and an skx command line. llvm-svn: 286055
2016-11-06 10:03:58 +08:00
; SSE-LABEL: test_x86_sse3_hsub_pd:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SSE: ## %bb.0:
[AVX-512] Add -show-mc-encoding to legacy vector intrinsic tests so we can see when VEX or EVEX encoded instructions are being emitted. Make sure the tests all have an avx2 command line and an skx command line. llvm-svn: 286055
2016-11-06 10:03:58 +08:00
; SSE-NEXT: hsubpd %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x7d,0xc1]
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary llvm-svn: 333831
2018-06-03 02:41:46 +08:00
; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
[AVX-512] Add -show-mc-encoding to legacy vector intrinsic tests so we can see when VEX or EVEX encoded instructions are being emitted. Make sure the tests all have an avx2 command line and an skx command line. llvm-svn: 286055
2016-11-06 10:03:58 +08:00
;
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary llvm-svn: 333831
2018-06-03 02:41:46 +08:00
; AVX-LABEL: test_x86_sse3_hsub_pd:
; AVX: ## %bb.0:
; AVX-NEXT: vhsubpd %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x7d,0xc1]
; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
Add tests for SSE intrinsics in non-avx mode by copying from the AVX test cases. Some of these may have been tested by other tests, but most weren't. Patch by Cameron McInally. llvm-svn: 193309
2013-10-24 14:45:13 +08:00
%res = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
ret <2 x double> %res
}
declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) nounwind readnone
define <4 x float> @test_x86_sse3_hsub_ps(<4 x float> %a0, <4 x float> %a1) {
[AVX-512] Add -show-mc-encoding to legacy vector intrinsic tests so we can see when VEX or EVEX encoded instructions are being emitted. Make sure the tests all have an avx2 command line and an skx command line. llvm-svn: 286055
2016-11-06 10:03:58 +08:00
; SSE-LABEL: test_x86_sse3_hsub_ps:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SSE: ## %bb.0:
[AVX-512] Add -show-mc-encoding to legacy vector intrinsic tests so we can see when VEX or EVEX encoded instructions are being emitted. Make sure the tests all have an avx2 command line and an skx command line. llvm-svn: 286055
2016-11-06 10:03:58 +08:00
; SSE-NEXT: hsubps %xmm1, %xmm0 ## encoding: [0xf2,0x0f,0x7d,0xc1]
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary llvm-svn: 333831
2018-06-03 02:41:46 +08:00
; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
[AVX-512] Add -show-mc-encoding to legacy vector intrinsic tests so we can see when VEX or EVEX encoded instructions are being emitted. Make sure the tests all have an avx2 command line and an skx command line. llvm-svn: 286055
2016-11-06 10:03:58 +08:00
;
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary llvm-svn: 333831
2018-06-03 02:41:46 +08:00
; AVX-LABEL: test_x86_sse3_hsub_ps:
; AVX: ## %bb.0:
; AVX-NEXT: vhsubps %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x7d,0xc1]
; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
Add tests for SSE intrinsics in non-avx mode by copying from the AVX test cases. Some of these may have been tested by other tests, but most weren't. Patch by Cameron McInally. llvm-svn: 193309
2013-10-24 14:45:13 +08:00
%res = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
ret <4 x float> %res
}
declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>) nounwind readnone
define <16 x i8> @test_x86_sse3_ldu_dq(i8* %a0) {
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary llvm-svn: 333831
2018-06-03 02:41:46 +08:00
; X86-SSE-LABEL: test_x86_sse3_ldu_dq:
; X86-SSE: ## %bb.0:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-SSE-NEXT: lddqu (%eax), %xmm0 ## encoding: [0xf2,0x0f,0xf0,0x00]
; X86-SSE-NEXT: retl ## encoding: [0xc3]
;
; X86-AVX-LABEL: test_x86_sse3_ldu_dq:
; X86-AVX: ## %bb.0:
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-AVX-NEXT: vlddqu (%eax), %xmm0 ## encoding: [0xc5,0xfb,0xf0,0x00]
; X86-AVX-NEXT: retl ## encoding: [0xc3]
;
; X64-SSE-LABEL: test_x86_sse3_ldu_dq:
; X64-SSE: ## %bb.0:
; X64-SSE-NEXT: lddqu (%rdi), %xmm0 ## encoding: [0xf2,0x0f,0xf0,0x07]
; X64-SSE-NEXT: retq ## encoding: [0xc3]
[AVX-512] Add -show-mc-encoding to legacy vector intrinsic tests so we can see when VEX or EVEX encoded instructions are being emitted. Make sure the tests all have an avx2 command line and an skx command line. llvm-svn: 286055
2016-11-06 10:03:58 +08:00
;
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary llvm-svn: 333831
2018-06-03 02:41:46 +08:00
; X64-AVX-LABEL: test_x86_sse3_ldu_dq:
; X64-AVX: ## %bb.0:
; X64-AVX-NEXT: vlddqu (%rdi), %xmm0 ## encoding: [0xc5,0xfb,0xf0,0x07]
; X64-AVX-NEXT: retq ## encoding: [0xc3]
Add tests for SSE intrinsics in non-avx mode by copying from the AVX test cases. Some of these may have been tested by other tests, but most weren't. Patch by Cameron McInally. llvm-svn: 193309
2013-10-24 14:45:13 +08:00
%res = call <16 x i8> @llvm.x86.sse3.ldu.dq(i8* %a0) ; <<16 x i8>> [#uses=1]
ret <16 x i8> %res
}
declare <16 x i8> @llvm.x86.sse3.ldu.dq(i8*) nounwind readonly
[X86] Remove sse3 intrinsic tests from the avx intrinsics test file. They are all covered by the SSE3 intrinsics test with SSE2, AVX, and AVX512 command lines. llvm-svn: 295705
2017-02-21 16:05:59 +08:00
; Make sure instructions with no AVX equivalents, but are associated with SSEX feature flags still work
define void @monitor(i8* %P, i32 %E, i32 %H) nounwind {
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary llvm-svn: 333831
2018-06-03 02:41:46 +08:00
; X86-LABEL: monitor:
; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
[X86] Remove CustomInserter pseudos for MONITOR/MONITORX/CLZERO. Use custom instruction selection instead. This custom inserter existed so we could do a weird thing where we pretended that the instructions support a full address mode instead of taking a pointer in EAX/RAX. I think was largely so we could be pointer size agnostic in the isel pattern. To make this work we would then put the address into an LEA into EAX/RAX in front of the instruction after isel. But the LEA is overkill when we just have a base pointer. So we end up using the LEA as a slower MOV instruction. With this change we now just do custom selection during isel instead and just assign the incoming address of the intrinsic into EAX/RAX based on its size. After the intrinsic is selected, we can let isel take care of selecting an LEA or other operation to do any address computation needed in this basic block. I've also split the instruction into a 32-bit mode version and a 64-bit mode version so the implicit use is properly sized based on the pointer. Without this we get comments in the assembly output about killing eax and defing rax or vice versa depending on whether we define the instruction to use EAX/RAX. llvm-svn: 357652
2019-04-04 07:28:30 +08:00
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ## encoding: [0x8b,0x4c,0x24,0x08]
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ## encoding: [0x8b,0x54,0x24,0x0c]
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary llvm-svn: 333831
2018-06-03 02:41:46 +08:00
; X86-NEXT: monitor ## encoding: [0x0f,0x01,0xc8]
; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: monitor:
; X64: ## %bb.0:
; X64-NEXT: movl %esi, %ecx ## encoding: [0x89,0xf1]
[X86] Remove CustomInserter pseudos for MONITOR/MONITORX/CLZERO. Use custom instruction selection instead. This custom inserter existed so we could do a weird thing where we pretended that the instructions support a full address mode instead of taking a pointer in EAX/RAX. I think was largely so we could be pointer size agnostic in the isel pattern. To make this work we would then put the address into an LEA into EAX/RAX in front of the instruction after isel. But the LEA is overkill when we just have a base pointer. So we end up using the LEA as a slower MOV instruction. With this change we now just do custom selection during isel instead and just assign the incoming address of the intrinsic into EAX/RAX based on its size. After the intrinsic is selected, we can let isel take care of selecting an LEA or other operation to do any address computation needed in this basic block. I've also split the instruction into a 32-bit mode version and a 64-bit mode version so the implicit use is properly sized based on the pointer. Without this we get comments in the assembly output about killing eax and defing rax or vice versa depending on whether we define the instruction to use EAX/RAX. llvm-svn: 357652
2019-04-04 07:28:30 +08:00
; X64-NEXT: movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary llvm-svn: 333831
2018-06-03 02:41:46 +08:00
; X64-NEXT: monitor ## encoding: [0x0f,0x01,0xc8]
; X64-NEXT: retq ## encoding: [0xc3]
[X86] Remove sse3 intrinsic tests from the avx intrinsics test file. They are all covered by the SSE3 intrinsics test with SSE2, AVX, and AVX512 command lines. llvm-svn: 295705
2017-02-21 16:05:59 +08:00
tail call void @llvm.x86.sse3.monitor(i8* %P, i32 %E, i32 %H)
ret void
}
declare void @llvm.x86.sse3.monitor(i8*, i32, i32) nounwind
define void @mwait(i32 %E, i32 %H) nounwind {
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary llvm-svn: 333831
2018-06-03 02:41:46 +08:00
; X86-LABEL: mwait:
; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ## encoding: [0x8b,0x4c,0x24,0x04]
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08]
; X86-NEXT: mwait ## encoding: [0x0f,0x01,0xc9]
; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: mwait:
; X64: ## %bb.0:
; X64-NEXT: movl %esi, %eax ## encoding: [0x89,0xf0]
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-NEXT: movl %edi, %ecx ## encoding: [0x89,0xf9]
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary llvm-svn: 333831
2018-06-03 02:41:46 +08:00
; X64-NEXT: mwait ## encoding: [0x0f,0x01,0xc9]
; X64-NEXT: retq ## encoding: [0xc3]
[X86] Remove sse3 intrinsic tests from the avx intrinsics test file. They are all covered by the SSE3 intrinsics test with SSE2, AVX, and AVX512 command lines. llvm-svn: 295705
2017-02-21 16:05:59 +08:00
tail call void @llvm.x86.sse3.mwait(i32 %E, i32 %H)
ret void
}
declare void @llvm.x86.sse3.mwait(i32, i32) nounwind