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llvm-project/llvm/test/CodeGen/X86/sse-intrinsics-x86_64-upgra...

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[X86] Remove and autoupgrade cvtsi2ss/cvtsi2sd intrinsics to match what clang has used for a very long time. llvm-svn: 332186
2018-05-13 07:14:39 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86][SSE] Cleanup SSE1 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary llvm-svn: 333833
2018-06-03 04:25:56 +08:00
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-sse2 -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,SSE
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,AVX,AVX1
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
[X86] Remove and autoupgrade cvtsi2ss/cvtsi2sd intrinsics to match what clang has used for a very long time. llvm-svn: 332186
2018-05-13 07:14:39 +08:00
define <4 x float> @test_x86_sse_cvtsi642ss(<4 x float> %a0, i64 %a1) {
; SSE-LABEL: test_x86_sse_cvtsi642ss:
; SSE: ## %bb.0:
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing. We require d/q suffixes on the memory form of these instructions to disambiguate the memory size. We don't require it on the register forms, but need to support parsing both with and without it. Previously we always printed the d/q suffix on the register forms, but it's redundant and inconsistent with gcc and objdump. After this patch we should support the d/q for parsing, but not print it when its unneeded. llvm-svn: 360085
2019-05-07 05:39:51 +08:00
; SSE-NEXT: cvtsi2ss %rdi, %xmm0 ## encoding: [0xf3,0x48,0x0f,0x2a,0xc7]
[X86] Remove and autoupgrade cvtsi2ss/cvtsi2sd intrinsics to match what clang has used for a very long time. llvm-svn: 332186
2018-05-13 07:14:39 +08:00
; SSE-NEXT: retq ## encoding: [0xc3]
;
[X86][SSE] Cleanup SSE1 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary llvm-svn: 333833
2018-06-03 04:25:56 +08:00
; AVX1-LABEL: test_x86_sse_cvtsi642ss:
; AVX1: ## %bb.0:
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing. We require d/q suffixes on the memory form of these instructions to disambiguate the memory size. We don't require it on the register forms, but need to support parsing both with and without it. Previously we always printed the d/q suffix on the register forms, but it's redundant and inconsistent with gcc and objdump. After this patch we should support the d/q for parsing, but not print it when its unneeded. llvm-svn: 360085
2019-05-07 05:39:51 +08:00
; AVX1-NEXT: vcvtsi2ss %rdi, %xmm0, %xmm0 ## encoding: [0xc4,0xe1,0xfa,0x2a,0xc7]
[X86][SSE] Cleanup SSE1 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary llvm-svn: 333833
2018-06-03 04:25:56 +08:00
; AVX1-NEXT: retq ## encoding: [0xc3]
[X86] Remove and autoupgrade cvtsi2ss/cvtsi2sd intrinsics to match what clang has used for a very long time. llvm-svn: 332186
2018-05-13 07:14:39 +08:00
;
[X86][SSE] Cleanup SSE1 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary llvm-svn: 333833
2018-06-03 04:25:56 +08:00
; AVX512-LABEL: test_x86_sse_cvtsi642ss:
; AVX512: ## %bb.0:
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing. We require d/q suffixes on the memory form of these instructions to disambiguate the memory size. We don't require it on the register forms, but need to support parsing both with and without it. Previously we always printed the d/q suffix on the register forms, but it's redundant and inconsistent with gcc and objdump. After this patch we should support the d/q for parsing, but not print it when its unneeded. llvm-svn: 360085
2019-05-07 05:39:51 +08:00
; AVX512-NEXT: vcvtsi2ss %rdi, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe1,0xfa,0x2a,0xc7]
[X86][SSE] Cleanup SSE1 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary llvm-svn: 333833
2018-06-03 04:25:56 +08:00
; AVX512-NEXT: retq ## encoding: [0xc3]
[X86] Remove and autoupgrade cvtsi2ss/cvtsi2sd intrinsics to match what clang has used for a very long time. llvm-svn: 332186
2018-05-13 07:14:39 +08:00
%res = call <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float> %a0, i64 %a1) ; <<4 x float>> [#uses=1]
ret <4 x float> %res
}
declare <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float>, i64) nounwind readnone