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llvm-project/llvm/test/CodeGen/X86/fp128-select.ll

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[X86] Accept SELECT op code for x86-64 fp128 type DAGTypeLegalizer::CanSkipSoftenFloatOperand should allow SELECT op code for x86_64 fp128 type for MME targets, so SoftenFloatOperand does not abort on SELECT op code. Differential Revision: http://reviews.llvm.org/D21758 llvm-svn: 275818
2016-07-19 01:20:09 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86] Enable fp128 as a legal type with SSE1 rather than with MMX. FP128 values are passed in xmm registers so should be asssociated with an SSE feature rather than MMX which uses a different set of registers. llc enables sse1 and sse2 by default with x86_64. But does not enable mmx. Clang enables all 3 features by default. I've tried to add command lines to test with -sse where possible, but any test that returns a value in an xmm register fails with a fatal error with -sse since we have no defined ABI for that scenario. llvm-svn: 370682
2019-09-03 04:16:30 +08:00
; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=+sse \
; RUN: -enable-legalize-types-checking | FileCheck %s --check-prefix=SSE
; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=+sse \
; RUN: -enable-legalize-types-checking | FileCheck %s --check-prefix=SSE
; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=-sse \
; RUN: -enable-legalize-types-checking | FileCheck %s --check-prefix=NOSSE
; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=-sse \
; RUN: -enable-legalize-types-checking | FileCheck %s --check-prefix=NOSSE
[X86] Accept SELECT op code for x86-64 fp128 type DAGTypeLegalizer::CanSkipSoftenFloatOperand should allow SELECT op code for x86_64 fp128 type for MME targets, so SoftenFloatOperand does not abort on SELECT op code. Differential Revision: http://reviews.llvm.org/D21758 llvm-svn: 275818
2016-07-19 01:20:09 +08:00
define void @test_select(fp128* %p, fp128* %q, i1 zeroext %c) {
[X86] Enable fp128 as a legal type with SSE1 rather than with MMX. FP128 values are passed in xmm registers so should be asssociated with an SSE feature rather than MMX which uses a different set of registers. llc enables sse1 and sse2 by default with x86_64. But does not enable mmx. Clang enables all 3 features by default. I've tried to add command lines to test with -sse where possible, but any test that returns a value in an xmm register fails with a fatal error with -sse since we have no defined ABI for that scenario. llvm-svn: 370682
2019-09-03 04:16:30 +08:00
; SSE-LABEL: test_select:
; SSE: # %bb.0:
; SSE-NEXT: testl %edx, %edx
; SSE-NEXT: jne .LBB0_1
; SSE-NEXT: # %bb.2:
; SSE-NEXT: movaps {{.*}}(%rip), %xmm0
; SSE-NEXT: movaps %xmm0, (%rsi)
; SSE-NEXT: retq
; SSE-NEXT: .LBB0_1:
; SSE-NEXT: movups (%rdi), %xmm0
; SSE-NEXT: movaps %xmm0, (%rsi)
; SSE-NEXT: retq
[X86] Accept SELECT op code for x86-64 fp128 type DAGTypeLegalizer::CanSkipSoftenFloatOperand should allow SELECT op code for x86_64 fp128 type for MME targets, so SoftenFloatOperand does not abort on SELECT op code. Differential Revision: http://reviews.llvm.org/D21758 llvm-svn: 275818
2016-07-19 01:20:09 +08:00
;
[X86] Enable fp128 as a legal type with SSE1 rather than with MMX. FP128 values are passed in xmm registers so should be asssociated with an SSE feature rather than MMX which uses a different set of registers. llc enables sse1 and sse2 by default with x86_64. But does not enable mmx. Clang enables all 3 features by default. I've tried to add command lines to test with -sse where possible, but any test that returns a value in an xmm register fails with a fatal error with -sse since we have no defined ABI for that scenario. llvm-svn: 370682
2019-09-03 04:16:30 +08:00
; NOSSE-LABEL: test_select:
; NOSSE: # %bb.0:
; NOSSE-NEXT: xorl %eax, %eax
; NOSSE-NEXT: testl %edx, %edx
; NOSSE-NEXT: cmovneq (%rdi), %rax
; NOSSE-NEXT: movabsq $9223231299366420480, %rcx # imm = 0x7FFF800000000000
; NOSSE-NEXT: cmovneq 8(%rdi), %rcx
; NOSSE-NEXT: movq %rcx, 8(%rsi)
; NOSSE-NEXT: movq %rax, (%rsi)
; NOSSE-NEXT: retq
[X86] Accept SELECT op code for x86-64 fp128 type DAGTypeLegalizer::CanSkipSoftenFloatOperand should allow SELECT op code for x86_64 fp128 type for MME targets, so SoftenFloatOperand does not abort on SELECT op code. Differential Revision: http://reviews.llvm.org/D21758 llvm-svn: 275818
2016-07-19 01:20:09 +08:00
%a = load fp128, fp128* %p, align 2
%r = select i1 %c, fp128 %a, fp128 0xL00000000000000007FFF800000000000
store fp128 %r, fp128* %q
ret void
}
[LegalizeTypes] Teach SoftenFloatOp_SELECT_CC to handle operand 2 or 3 being softened. This can only happen on X86 when fp128 is a legal type, but we go through softening to generate libcalls. This causes fp128 to be softened to fp128 instead of an integer type. This can be removed if D67128 lands. llvm-svn: 371493
2019-09-10 15:56:02 +08:00
; The uitofp will become a select_cc. This used to crash during type
; legalization because we didn't expect the operands to need to be softened.
define fp128 @test_select_cc(fp128, fp128) {
; SSE-LABEL: test_select_cc:
; SSE: # %bb.0: # %BB0
; SSE-NEXT: pushq %rbx
; SSE-NEXT: .cfi_def_cfa_offset 16
; SSE-NEXT: subq $32, %rsp
; SSE-NEXT: .cfi_def_cfa_offset 48
; SSE-NEXT: .cfi_offset %rbx, -16
; SSE-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; SSE-NEXT: callq __netf2
; SSE-NEXT: movl %eax, %ebx
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; SSE-NEXT: callq __eqtf2
; SSE-NEXT: testl %eax, %eax
; SSE-NEXT: je .LBB1_1
; SSE-NEXT: # %bb.2: # %BB0
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: jmp .LBB1_3
; SSE-NEXT: .LBB1_1:
; SSE-NEXT: movaps {{.*}}(%rip), %xmm1
; SSE-NEXT: .LBB1_3: # %BB0
; SSE-NEXT: testl %ebx, %ebx
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; SSE-NEXT: jne .LBB1_5
; SSE-NEXT: # %bb.4: # %BB1
; SSE-NEXT: movaps %xmm1, %xmm0
; SSE-NEXT: .LBB1_5: # %BB2
; SSE-NEXT: addq $32, %rsp
; SSE-NEXT: .cfi_def_cfa_offset 16
; SSE-NEXT: popq %rbx
; SSE-NEXT: .cfi_def_cfa_offset 8
; SSE-NEXT: retq
;
; NOSSE-LABEL: test_select_cc:
; NOSSE: # %bb.0: # %BB0
; NOSSE-NEXT: pushq %rbp
; NOSSE-NEXT: .cfi_def_cfa_offset 16
; NOSSE-NEXT: pushq %r15
; NOSSE-NEXT: .cfi_def_cfa_offset 24
; NOSSE-NEXT: pushq %r14
; NOSSE-NEXT: .cfi_def_cfa_offset 32
; NOSSE-NEXT: pushq %r12
; NOSSE-NEXT: .cfi_def_cfa_offset 40
; NOSSE-NEXT: pushq %rbx
; NOSSE-NEXT: .cfi_def_cfa_offset 48
; NOSSE-NEXT: .cfi_offset %rbx, -48
; NOSSE-NEXT: .cfi_offset %r12, -40
; NOSSE-NEXT: .cfi_offset %r14, -32
; NOSSE-NEXT: .cfi_offset %r15, -24
; NOSSE-NEXT: .cfi_offset %rbp, -16
; NOSSE-NEXT: movq %rcx, %r12
; NOSSE-NEXT: movq %rdx, %rbx
; NOSSE-NEXT: movq %rsi, %r14
; NOSSE-NEXT: movq %rdi, %r15
; NOSSE-NEXT: callq __netf2
; NOSSE-NEXT: movl %eax, %ebp
; NOSSE-NEXT: movq %r15, %rdi
; NOSSE-NEXT: movq %r14, %rsi
; NOSSE-NEXT: movq %rbx, %rdx
; NOSSE-NEXT: movq %r12, %rcx
; NOSSE-NEXT: callq __eqtf2
; NOSSE-NEXT: movl %eax, %ecx
; NOSSE-NEXT: xorl %eax, %eax
; NOSSE-NEXT: testl %ecx, %ecx
; NOSSE-NEXT: movabsq $4611404543450677248, %rdx # imm = 0x3FFF000000000000
; NOSSE-NEXT: cmovneq %rax, %rdx
; NOSSE-NEXT: testl %ebp, %ebp
; NOSSE-NEXT: je .LBB1_2
; NOSSE-NEXT: # %bb.1:
; NOSSE-NEXT: movq %r15, %rax
; NOSSE-NEXT: movq %r14, %rdx
; NOSSE-NEXT: .LBB1_2: # %BB2
; NOSSE-NEXT: popq %rbx
; NOSSE-NEXT: .cfi_def_cfa_offset 40
; NOSSE-NEXT: popq %r12
; NOSSE-NEXT: .cfi_def_cfa_offset 32
; NOSSE-NEXT: popq %r14
; NOSSE-NEXT: .cfi_def_cfa_offset 24
; NOSSE-NEXT: popq %r15
; NOSSE-NEXT: .cfi_def_cfa_offset 16
; NOSSE-NEXT: popq %rbp
; NOSSE-NEXT: .cfi_def_cfa_offset 8
; NOSSE-NEXT: retq
BB0:
%a = fcmp oeq fp128 %0, %1
%b = uitofp i1 %a to fp128
br i1 %a, label %BB1, label %BB2
BB1:
br label %BB2
BB2:
%c = phi fp128 [ %0, %BB0 ], [ %b, %BB1 ]
ret fp128 %c
}