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llvm-project/llvm/test/CodeGen/X86/avx-bitcast.ll

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[X86] Automatically generate various tests. NFC llvm-svn: 369909
2019-08-26 21:53:29 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
use update_llc_test_checks.py to tighten checking; remove unnecessary testing params llvm-svn: 234024
2015-04-04 01:09:37 +08:00
; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s
Add a AVX version of a simple i64 -> f64 bitcast. This could be triggered using llc with -O0, which wouldn't let it be folded and expose the lack of this pattern. llvm-svn: 139320
2011-09-09 05:52:33 +08:00
define i64 @bitcasti64tof64() {
use update_llc_test_checks.py to tighten checking; remove unnecessary testing params llvm-svn: 234024
2015-04-04 01:09:37 +08:00
; CHECK-LABEL: bitcasti64tof64:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0:
[X86] Automatically generate various tests. NFC llvm-svn: 369909
2019-08-26 21:53:29 +08:00
; CHECK-NEXT: # implicit-def: $rax
; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
use update_llc_test_checks.py to tighten checking; remove unnecessary testing params llvm-svn: 234024
2015-04-04 01:09:37 +08:00
; CHECK-NEXT: vmovq %xmm0, %rax
; CHECK-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%a = load double, double* undef
Add a AVX version of a simple i64 -> f64 bitcast. This could be triggered using llc with -O0, which wouldn't let it be folded and expose the lack of this pattern. llvm-svn: 139320
2011-09-09 05:52:33 +08:00
%b = bitcast double %a to i64
ret i64 %b
}