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llvm-project/llvm/test/CodeGen/SPARC/ctpop.ll

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[SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL does not clear top 32 bit, only SRL does. llvm-svn: 198280
2014-01-02 03:00:10 +08:00
; RUN: llc < %s -march=sparc -mattr=-v9 | FileCheck %s -check-prefix=V8
Only generate the popc instruction for SPARC CPUs that implement it. The popc instruction is defined in the SPARCv9 instruction set architecture, but it was emulated on CPUs older than Niagara 2. llvm-svn: 200131
2014-01-26 14:09:59 +08:00
; RUN: llc < %s -march=sparc -mattr=+v9,+popc | FileCheck %s -check-prefix=V9
; RUN: llc < %s -march=sparc -mcpu=v9 | FileCheck %s -check-prefix=V8
; RUN: llc < %s -march=sparc -mcpu=ultrasparc | FileCheck %s -check-prefix=V8
; RUN: llc < %s -march=sparc -mcpu=ultrasparc3 | FileCheck %s -check-prefix=V8
; RUN: llc < %s -march=sparc -mcpu=niagara | FileCheck %s -check-prefix=V8
[Sparc] Add missing processor types: v7 and niagara llvm-svn: 199024
2014-01-12 07:56:13 +08:00
; RUN: llc < %s -march=sparc -mcpu=niagara2 | FileCheck %s -check-prefix=V9
; RUN: llc < %s -march=sparc -mcpu=niagara3 | FileCheck %s -check-prefix=V9
; RUN: llc < %s -march=sparc -mcpu=niagara4 | FileCheck %s -check-prefix=V9
Only generate the popc instruction for SPARC CPUs that implement it. The popc instruction is defined in the SPARCv9 instruction set architecture, but it was emulated on CPUs older than Niagara 2. llvm-svn: 200131
2014-01-26 14:09:59 +08:00
; RUN: llc < %s -march=sparcv9 -mattr=+popc | FileCheck %s -check-prefix=SPARC64
move V8 testcases here llvm-svn: 25986
2006-02-05 13:52:55 +08:00
Remove llvm-upgrade and update tests. llvm-svn: 47296
2008-02-19 09:41:04 +08:00
declare i32 @llvm.ctpop.i32(i32)
[SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL does not clear top 32 bit, only SRL does. llvm-svn: 198280
2014-01-02 03:00:10 +08:00
; V8-LABEL: test
Fix broken CHECK lines. llvm-svn: 199016
2014-01-12 05:06:00 +08:00
; V8-NOT: popc
[SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL does not clear top 32 bit, only SRL does. llvm-svn: 198280
2014-01-02 03:00:10 +08:00
; V9-LABEL: test
; V9: srl %o0, 0, %o0
[Sparc] Emit retl/ret instead of jmp instruction. It improves the readability of the assembly generated. llvm-svn: 198910
2014-01-10 10:55:27 +08:00
; V9-NEXT: retl
[SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL does not clear top 32 bit, only SRL does. llvm-svn: 198280
2014-01-02 03:00:10 +08:00
; V9-NEXT: popc %o0, %o0
; SPARC64-LABEL: test
; SPARC64: srl %o0, 0, %o0
[Sparc] Emit retl/ret instead of jmp instruction. It improves the readability of the assembly generated. llvm-svn: 198910
2014-01-10 10:55:27 +08:00
; SPARC64: retl
[SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL does not clear top 32 bit, only SRL does. llvm-svn: 198280
2014-01-02 03:00:10 +08:00
; SPARC64: popc %o0, %o0
Remove llvm-upgrade and update tests. llvm-svn: 47296
2008-02-19 09:41:04 +08:00
define i32 @test(i32 %X) {
%Y = call i32 @llvm.ctpop.i32( i32 %X ) ; <i32> [#uses=1]
ret i32 %Y
move V8 testcases here llvm-svn: 25986
2006-02-05 13:52:55 +08:00
}