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llvm-project/llvm/test/CodeGen/PowerPC/bitfieldinsert.ll

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[PowerPC] reduce rotate in BitPermutationSelector BitPermutationSelector builds the output value by repeating rotate-and-mask instructions with input registers. Here, we may avoid one rotate instruction if we start building from an input register that does not require rotation. For example of the test case bitfieldinsert.ll, it first rotates left r4 by 8 bits and then inserts some bits from r5 without rotation. This can be executed by one rlwimi instruction, which rotates r4 by 8 bits and inserts its bits into r5. This patch adds a check for rotation amounts in the comparator used in sorting to process the input without rotation first. Differential Revision: https://reviews.llvm.org/D47765 llvm-svn: 334011
2018-06-05 19:58:01 +08:00
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
[PowerPC] avoid masking already-zero bits in BitPermutationSelector The current BitPermutationSelector generates a code to build a value by tracking two types of bits: ConstZero and Variable. ConstZero means a bit we need to mask off and Variable is a bit we copy from an input value. This patch add third type of bits VariableKnownToBeZero caused by AssertZext node or zero-extending load node. VariableKnownToBeZero means a bit comes from an input value, but it is known to be already zero. So we do not need to mask them. VariableKnownToBeZero enhances flexibility to group bits, since we can avoid redundant masking for these bits. This patch also renames "HasZero" to "NeedMask" since now we may skip masking even when we have zeros (of type VariableKnownToBeZero). Differential Revision: https://reviews.llvm.org/D48025 llvm-svn: 344347
2018-10-12 22:02:20 +08:00
; equivalent C code
; struct s64 {
; int a:5;
; int b:16;
; long c:42;
; };
; void bitfieldinsert64(struct s *p, unsigned short v) {
; p->b = v;
; }
%struct.s64 = type { i64 }
define void @bitfieldinsert64(%struct.s64* nocapture %p, i16 zeroext %v) {
; CHECK-LABEL: @bitfieldinsert64
; CHECK: ld [[REG1:[0-9]+]], 0(3)
; CHECK-NEXT: rlwimi [[REG1]], 4, 5, 11, 26
; CHECK-NEXT: std [[REG1]], 0(3)
; CHECK-NEXT: blr
entry:
%0 = getelementptr inbounds %struct.s64, %struct.s64* %p, i64 0, i32 0
%1 = zext i16 %v to i64
%bf.load = load i64, i64* %0, align 8
%bf.shl = shl nuw nsw i64 %1, 5
%bf.clear = and i64 %bf.load, -2097121
%bf.set = or i64 %bf.clear, %bf.shl
store i64 %bf.set, i64* %0, align 8
ret void
}
[PowerPC] reduce rotate in BitPermutationSelector BitPermutationSelector builds the output value by repeating rotate-and-mask instructions with input registers. Here, we may avoid one rotate instruction if we start building from an input register that does not require rotation. For example of the test case bitfieldinsert.ll, it first rotates left r4 by 8 bits and then inserts some bits from r5 without rotation. This can be executed by one rlwimi instruction, which rotates r4 by 8 bits and inserts its bits into r5. This patch adds a check for rotation amounts in the comparator used in sorting to process the input without rotation first. Differential Revision: https://reviews.llvm.org/D47765 llvm-svn: 334011
2018-06-05 19:58:01 +08:00
; bitfieldinsert32: Test for rlwimi
; equivalent C code
; struct s32 {
; int a:8;
; int b:16;
; int c:8;
; };
; void bitfieldinsert32(struct s32 *p, unsigned int v) {
; p->b = v;
; }
%struct.s32 = type { i32 }
define void @bitfieldinsert32(%struct.s32* nocapture %p, i32 zeroext %v) {
; CHECK-LABEL: @bitfieldinsert32
; CHECK: lwz [[REG1:[0-9]+]], 0(3)
[PowerPC] avoid masking already-zero bits in BitPermutationSelector The current BitPermutationSelector generates a code to build a value by tracking two types of bits: ConstZero and Variable. ConstZero means a bit we need to mask off and Variable is a bit we copy from an input value. This patch add third type of bits VariableKnownToBeZero caused by AssertZext node or zero-extending load node. VariableKnownToBeZero means a bit comes from an input value, but it is known to be already zero. So we do not need to mask them. VariableKnownToBeZero enhances flexibility to group bits, since we can avoid redundant masking for these bits. This patch also renames "HasZero" to "NeedMask" since now we may skip masking even when we have zeros (of type VariableKnownToBeZero). Differential Revision: https://reviews.llvm.org/D48025 llvm-svn: 344347
2018-10-12 22:02:20 +08:00
; CHECK-NEXT: rlwimi [[REG1]], 4, 8, 8, 23
; CHECK-NEXT: stw [[REG1]], 0(3)
; CHECK-NEXT: blr
[PowerPC] reduce rotate in BitPermutationSelector BitPermutationSelector builds the output value by repeating rotate-and-mask instructions with input registers. Here, we may avoid one rotate instruction if we start building from an input register that does not require rotation. For example of the test case bitfieldinsert.ll, it first rotates left r4 by 8 bits and then inserts some bits from r5 without rotation. This can be executed by one rlwimi instruction, which rotates r4 by 8 bits and inserts its bits into r5. This patch adds a check for rotation amounts in the comparator used in sorting to process the input without rotation first. Differential Revision: https://reviews.llvm.org/D47765 llvm-svn: 334011
2018-06-05 19:58:01 +08:00
entry:
%0 = getelementptr inbounds %struct.s32, %struct.s32* %p, i64 0, i32 0
%bf.load = load i32, i32* %0, align 4
%bf.value = shl i32 %v, 8
%bf.shl = and i32 %bf.value, 16776960
%bf.clear = and i32 %bf.load, -16776961
%bf.set = or i32 %bf.clear, %bf.shl
store i32 %bf.set, i32* %0, align 4
ret void
}
[PowerPC] handle ISD:TRUNCATE in BitPermutationSelector This is the last one in a series of patches to support better code generation for bitfield insert. BitPermutationSelector already support ISD::ZERO_EXTEND but not TRUNCATE. This patch adds support for ISD:TRUNCATE in BitPermutationSelector. For example of this test case, struct s64b { int a:4; int b:16; int c:24; }; void bitfieldinsert64b(struct s64b *p, unsigned char v) { p->b = v; } the selection DAG loos like: t14: i32,ch = load<(load 4 from %ir.0)> t0, t2, undef:i64 t18: i32 = and t14, Constant:i32<-1048561> t4: i64,ch = CopyFromReg t0, Register:i64 %1 t22: i64 = AssertZext t4, ValueType:ch:i8 t23: i32 = truncate t22 t16: i32 = shl nuw nsw t23, Constant:i32<4> t19: i32 = or t18, t16 t20: ch = store<(store 4 into %ir.0)> t14:1, t19, t2, undef:i64 By handling truncate in the BitPermutationSelector, we can use information from AssertZext when selecting t19 and skip the mask operation corresponding to t18. So the generated sequences with and without this patch are without this patch rlwinm 5, 5, 0, 28, 11 # corresponding to t18 rlwimi 5, 4, 4, 20, 27 with this patch rlwimi 5, 4, 4, 12, 27 Differential Revision: https://reviews.llvm.org/D49076 llvm-svn: 350118
2018-12-28 16:00:39 +08:00
; test cases which include ISD::TRUNCATE
; equivalent C code
; struct s64b {
; int a:4;
; int b:16;
; int c:24;
; };
; void bitfieldinsert64b(struct s64b *p, unsigned char v) {
; p->b = v;
; }
%struct.s64b = type { i24, i24 }
define void @bitfieldinsert64b(%struct.s64b* nocapture %p, i8 zeroext %v) {
; CHECK-LABEL: @bitfieldinsert64b
; CHECK: lwz [[REG1:[0-9]+]], 0(3)
; CHECK-NEXT: rlwimi [[REG1]], 4, 4, 12, 27
; CHECK-NEXT: stw [[REG1]], 0(3)
; CHECK-NEXT: blr
entry:
%conv = zext i8 %v to i32
%0 = bitcast %struct.s64b* %p to i32*
%bf.load = load i32, i32* %0, align 4
%bf.shl = shl nuw nsw i32 %conv, 4
%bf.clear = and i32 %bf.load, -1048561
%bf.set = or i32 %bf.clear, %bf.shl
store i32 %bf.set, i32* %0, align 4
ret void
}
; equivalent C code
; struct s64c {
; int a:5;
; int b:16;
; long c:10;
; };
; void bitfieldinsert64c(struct s64c *p, unsigned short v) {
; p->b = v;
; }
%struct.s64c = type { i32, [4 x i8] }
define void @bitfieldinsert64c(%struct.s64c* nocapture %p, i16 zeroext %v) {
; CHECK-LABEL: @bitfieldinsert64c
; CHECK: lwz [[REG1:[0-9]+]], 0(3)
; CHECK-NEXT: rlwimi [[REG1]], 4, 5, 11, 26
; CHECK-NEXT: stw [[REG1]], 0(3)
; CHECK-NEXT: blr
entry:
%conv = zext i16 %v to i32
%0 = getelementptr inbounds %struct.s64c, %struct.s64c* %p, i64 0, i32 0
%bf.load = load i32, i32* %0, align 8
%bf.shl = shl nuw nsw i32 %conv, 5
%bf.clear = and i32 %bf.load, -2097121
%bf.set = or i32 %bf.clear, %bf.shl
store i32 %bf.set, i32* %0, align 8
ret void
}