maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/AVR/rot.ll

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

60 lines
1.0 KiB
LLVM
Raw Normal View History

[AVR] Implement non-constant bit rotations This lets us do bit rotations of variable amount. llvm-svn: 301794
2017-05-01 17:48:55 +08:00
; RUN: llc < %s -march=avr | FileCheck %s
; Bit rotation tests.
; CHECK-LABEL: rol8:
define i8 @rol8(i8 %val, i8 %amt) {
; CHECK: andi r22, 7
[AVR] Fix a big in shift operator lowering; Authored by Dr. Gergo Erdi When generating code for a shift loop, check the shift amount against the literal value 0, not R0 llvm-svn: 304284
2017-05-31 14:27:46 +08:00
; CHECK-NEXT: cpi r22, 0
[AVR] Implement non-constant bit rotations This lets us do bit rotations of variable amount. llvm-svn: 301794
2017-05-01 17:48:55 +08:00
; CHECK-NEXT: breq LBB0_2
; CHECK-NEXT: LBB0_1:
[AVR] Fix codegen for rotate instructions Summary: This patch introduces the ROLBRd and RORBRd pseudo-instructions, which implemenent the "traditional" rotate operations; instead of the AVR rotate instructions that use the carry bit. The code is not optimized at all. Especially when dealing with loops of rotate instructions, this codegen should be improved some day. Related bug: 41358 <https://bugs.llvm.org/show_bug.cgi?id=41358> //Note//: This is my first submitted patch. Reviewers: dylanmckay, Jim Reviewed By: dylanmckay Subscribers: hiraditya, llvm-commits, dylanmckay, dsprenkels Tags: #llvm Patched by dsprenkels (Daan Sprenkels) Differential Revision: https://reviews.llvm.org/D60365
2019-12-23 11:24:20 +08:00
; CHECK-NEXT: lsl r24
; CHECK-NEXT: adc r24, r1
[AVR] Implement non-constant bit rotations This lets us do bit rotations of variable amount. llvm-svn: 301794
2017-05-01 17:48:55 +08:00
; CHECK-NEXT: subi r22, 1
; CHECK-NEXT: brne LBB0_1
; CHECK-NEXT:LBB0_2:
; CHECK-NEXT: ret
%mod = urem i8 %amt, 8
%inv = sub i8 8, %mod
%parta = shl i8 %val, %mod
%partb = lshr i8 %val, %inv
%rotl = or i8 %parta, %partb
ret i8 %rotl
}
; CHECK-LABEL: ror8:
define i8 @ror8(i8 %val, i8 %amt) {
; CHECK: andi r22, 7
[AVR] Fix a big in shift operator lowering; Authored by Dr. Gergo Erdi When generating code for a shift loop, check the shift amount against the literal value 0, not R0 llvm-svn: 304284
2017-05-31 14:27:46 +08:00
; CHECK-NEXT: cpi r22, 0
[AVR] Implement non-constant bit rotations This lets us do bit rotations of variable amount. llvm-svn: 301794
2017-05-01 17:48:55 +08:00
; CHECK-NEXT: breq LBB1_2
; CHECK-NEXT: LBB1_1:
[AVR] Fix codegen for rotate instructions Summary: This patch introduces the ROLBRd and RORBRd pseudo-instructions, which implemenent the "traditional" rotate operations; instead of the AVR rotate instructions that use the carry bit. The code is not optimized at all. Especially when dealing with loops of rotate instructions, this codegen should be improved some day. Related bug: 41358 <https://bugs.llvm.org/show_bug.cgi?id=41358> //Note//: This is my first submitted patch. Reviewers: dylanmckay, Jim Reviewed By: dylanmckay Subscribers: hiraditya, llvm-commits, dylanmckay, dsprenkels Tags: #llvm Patched by dsprenkels (Daan Sprenkels) Differential Revision: https://reviews.llvm.org/D60365
2019-12-23 11:24:20 +08:00
; CHECK-NEXT: lsr r24
; CHECK-NEXT: ldi r0, 0
; CHECK-NEXT: ror r0
; CHECK-NEXT: or r24, r0
[AVR] Implement non-constant bit rotations This lets us do bit rotations of variable amount. llvm-svn: 301794
2017-05-01 17:48:55 +08:00
; CHECK-NEXT: subi r22, 1
; CHECK-NEXT: brne LBB1_1
; CHECK-NEXT:LBB1_2:
; CHECK-NEXT: ret
%mod = urem i8 %amt, 8
%inv = sub i8 8, %mod
%parta = lshr i8 %val, %mod
%partb = shl i8 %val, %inv
%rotr = or i8 %parta, %partb
ret i8 %rotr
}