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llvm-project/llvm/test/CodeGen/X86/x86-64-psub.ll

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[X86][MMX] Regenerate MMX PSUB commutation test llvm-svn: 325685
2018-02-21 23:07:47 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
fix test attributes; these are MMX tests, not Nehalem tests llvm-svn: 228535
2015-02-09 04:01:12 +08:00
; RUN: llc -mtriple=x86_64-pc-linux -mattr=mmx < %s | FileCheck %s
Reapply "Subtract isn't commutative, fix this for MMX psub." with a somewhat randomly chosen cpu that will minimize cpu specific differences on bots. llvm-svn: 181814
2013-05-15 02:33:40 +08:00
; MMX packed sub opcodes were wrongly marked as commutative.
; This test checks that the operands of packed sub instructions are
; never interchanged by the "Two-Address instruction pass".
Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
2013-10-16 07:33:07 +08:00
declare { i64, double } @getFirstParam()
declare { i64, double } @getSecondParam()
Reapply "Subtract isn't commutative, fix this for MMX psub." with a somewhat randomly chosen cpu that will minimize cpu specific differences on bots. llvm-svn: 181814
2013-05-15 02:33:40 +08:00
define i64 @test_psubb() {
[X86][MMX] Regenerate MMX PSUB commutation test llvm-svn: 325685
2018-02-21 23:07:47 +08:00
; CHECK-LABEL: test_psubb:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: callq getFirstParam
; CHECK-NEXT: movq %rax, %rbx
; CHECK-NEXT: callq getSecondParam
; CHECK-NEXT: movq %rbx, %mm0
; CHECK-NEXT: movq %rax, %mm1
; CHECK-NEXT: psubb %mm1, %mm0
; CHECK-NEXT: movq %mm0, %rax
; CHECK-NEXT: popq %rbx
Correct dwarf unwind information in function epilogue This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: * CFI instructions do not affect code generation (they are not counted as instructions when tail duplicating or tail merging) * Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Added CFIInstrInserter pass: * analyzes each basic block to determine cfa offset and register are valid at its entry and exit * verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors * inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D42848 llvm-svn: 330706
2018-04-24 18:32:08 +08:00
; CHECK-NEXT: .cfi_def_cfa_offset 8
[X86][MMX] Regenerate MMX PSUB commutation test llvm-svn: 325685
2018-02-21 23:07:47 +08:00
; CHECK-NEXT: retq
Reapply "Subtract isn't commutative, fix this for MMX psub." with a somewhat randomly chosen cpu that will minimize cpu specific differences on bots. llvm-svn: 181814
2013-05-15 02:33:40 +08:00
entry:
%call = tail call { i64, double } @getFirstParam()
%0 = extractvalue { i64, double } %call, 0
%call2 = tail call { i64, double } @getSecondParam()
%1 = extractvalue { i64, double } %call2, 0
%__m1.0.insert.i = insertelement <1 x i64> undef, i64 %0, i32 0
%__m2.0.insert.i = insertelement <1 x i64> undef, i64 %1, i32 0
%2 = bitcast <1 x i64> %__m1.0.insert.i to <8 x i8>
%3 = bitcast <8 x i8> %2 to x86_mmx
%4 = bitcast <1 x i64> %__m2.0.insert.i to <8 x i8>
%5 = bitcast <8 x i8> %4 to x86_mmx
%6 = tail call x86_mmx @llvm.x86.mmx.psub.b(x86_mmx %3, x86_mmx %5) nounwind
%7 = bitcast x86_mmx %6 to <8 x i8>
%8 = bitcast <8 x i8> %7 to <1 x i64>
%retval.0.extract.i15 = extractelement <1 x i64> %8, i32 0
ret i64 %retval.0.extract.i15
}
define i64 @test_psubw() {
[X86][MMX] Regenerate MMX PSUB commutation test llvm-svn: 325685
2018-02-21 23:07:47 +08:00
; CHECK-LABEL: test_psubw:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: callq getFirstParam
; CHECK-NEXT: movq %rax, %rbx
; CHECK-NEXT: callq getSecondParam
; CHECK-NEXT: movq %rbx, %mm0
; CHECK-NEXT: movq %rax, %mm1
; CHECK-NEXT: psubw %mm1, %mm0
; CHECK-NEXT: movq %mm0, %rax
; CHECK-NEXT: popq %rbx
Correct dwarf unwind information in function epilogue This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: * CFI instructions do not affect code generation (they are not counted as instructions when tail duplicating or tail merging) * Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Added CFIInstrInserter pass: * analyzes each basic block to determine cfa offset and register are valid at its entry and exit * verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors * inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D42848 llvm-svn: 330706
2018-04-24 18:32:08 +08:00
; CHECK-NEXT: .cfi_def_cfa_offset 8
[X86][MMX] Regenerate MMX PSUB commutation test llvm-svn: 325685
2018-02-21 23:07:47 +08:00
; CHECK-NEXT: retq
Reapply "Subtract isn't commutative, fix this for MMX psub." with a somewhat randomly chosen cpu that will minimize cpu specific differences on bots. llvm-svn: 181814
2013-05-15 02:33:40 +08:00
entry:
%call = tail call { i64, double } @getFirstParam()
%0 = extractvalue { i64, double } %call, 0
%call2 = tail call { i64, double } @getSecondParam()
%1 = extractvalue { i64, double } %call2, 0
%__m1.0.insert.i = insertelement <1 x i64> undef, i64 %0, i32 0
%__m2.0.insert.i = insertelement <1 x i64> undef, i64 %1, i32 0
%2 = bitcast <1 x i64> %__m1.0.insert.i to <4 x i16>
%3 = bitcast <4 x i16> %2 to x86_mmx
%4 = bitcast <1 x i64> %__m2.0.insert.i to <4 x i16>
%5 = bitcast <4 x i16> %4 to x86_mmx
%6 = tail call x86_mmx @llvm.x86.mmx.psub.w(x86_mmx %3, x86_mmx %5) nounwind
%7 = bitcast x86_mmx %6 to <4 x i16>
%8 = bitcast <4 x i16> %7 to <1 x i64>
%retval.0.extract.i15 = extractelement <1 x i64> %8, i32 0
ret i64 %retval.0.extract.i15
}
define i64 @test_psubd() {
[X86][MMX] Regenerate MMX PSUB commutation test llvm-svn: 325685
2018-02-21 23:07:47 +08:00
; CHECK-LABEL: test_psubd:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: callq getFirstParam
; CHECK-NEXT: movq %rax, %rbx
; CHECK-NEXT: callq getSecondParam
; CHECK-NEXT: movq %rbx, %mm0
; CHECK-NEXT: movq %rax, %mm1
; CHECK-NEXT: psubd %mm1, %mm0
; CHECK-NEXT: movq %mm0, %rax
; CHECK-NEXT: popq %rbx
Correct dwarf unwind information in function epilogue This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: * CFI instructions do not affect code generation (they are not counted as instructions when tail duplicating or tail merging) * Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Added CFIInstrInserter pass: * analyzes each basic block to determine cfa offset and register are valid at its entry and exit * verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors * inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D42848 llvm-svn: 330706
2018-04-24 18:32:08 +08:00
; CHECK-NEXT: .cfi_def_cfa_offset 8
[X86][MMX] Regenerate MMX PSUB commutation test llvm-svn: 325685
2018-02-21 23:07:47 +08:00
; CHECK-NEXT: retq
Reapply "Subtract isn't commutative, fix this for MMX psub." with a somewhat randomly chosen cpu that will minimize cpu specific differences on bots. llvm-svn: 181814
2013-05-15 02:33:40 +08:00
entry:
%call = tail call { i64, double } @getFirstParam()
%0 = extractvalue { i64, double } %call, 0
%call2 = tail call { i64, double } @getSecondParam()
%1 = extractvalue { i64, double } %call2, 0
%__m1.0.insert.i = insertelement <1 x i64> undef, i64 %0, i32 0
%__m2.0.insert.i = insertelement <1 x i64> undef, i64 %1, i32 0
%2 = bitcast <1 x i64> %__m1.0.insert.i to <2 x i32>
%3 = bitcast <2 x i32> %2 to x86_mmx
%4 = bitcast <1 x i64> %__m2.0.insert.i to <2 x i32>
%5 = bitcast <2 x i32> %4 to x86_mmx
%6 = tail call x86_mmx @llvm.x86.mmx.psub.d(x86_mmx %3, x86_mmx %5) nounwind
%7 = bitcast x86_mmx %6 to <2 x i32>
%8 = bitcast <2 x i32> %7 to <1 x i64>
%retval.0.extract.i15 = extractelement <1 x i64> %8, i32 0
ret i64 %retval.0.extract.i15
}
define i64 @test_psubsb() {
[X86][MMX] Regenerate MMX PSUB commutation test llvm-svn: 325685
2018-02-21 23:07:47 +08:00
; CHECK-LABEL: test_psubsb:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: callq getFirstParam
; CHECK-NEXT: movq %rax, %rbx
; CHECK-NEXT: callq getSecondParam
; CHECK-NEXT: movq %rbx, %mm0
; CHECK-NEXT: movq %rax, %mm1
; CHECK-NEXT: psubsb %mm1, %mm0
; CHECK-NEXT: movq %mm0, %rax
; CHECK-NEXT: popq %rbx
Correct dwarf unwind information in function epilogue This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: * CFI instructions do not affect code generation (they are not counted as instructions when tail duplicating or tail merging) * Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Added CFIInstrInserter pass: * analyzes each basic block to determine cfa offset and register are valid at its entry and exit * verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors * inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D42848 llvm-svn: 330706
2018-04-24 18:32:08 +08:00
; CHECK-NEXT: .cfi_def_cfa_offset 8
[X86][MMX] Regenerate MMX PSUB commutation test llvm-svn: 325685
2018-02-21 23:07:47 +08:00
; CHECK-NEXT: retq
Reapply "Subtract isn't commutative, fix this for MMX psub." with a somewhat randomly chosen cpu that will minimize cpu specific differences on bots. llvm-svn: 181814
2013-05-15 02:33:40 +08:00
entry:
%call = tail call { i64, double } @getFirstParam()
%0 = extractvalue { i64, double } %call, 0
%call2 = tail call { i64, double } @getSecondParam()
%1 = extractvalue { i64, double } %call2, 0
%__m1.0.insert.i = insertelement <1 x i64> undef, i64 %0, i32 0
%__m2.0.insert.i = insertelement <1 x i64> undef, i64 %1, i32 0
%2 = bitcast <1 x i64> %__m1.0.insert.i to <8 x i8>
%3 = bitcast <8 x i8> %2 to x86_mmx
%4 = bitcast <1 x i64> %__m2.0.insert.i to <8 x i8>
%5 = bitcast <8 x i8> %4 to x86_mmx
%6 = tail call x86_mmx @llvm.x86.mmx.psubs.b(x86_mmx %3, x86_mmx %5) nounwind
%7 = bitcast x86_mmx %6 to <8 x i8>
%8 = bitcast <8 x i8> %7 to <1 x i64>
%retval.0.extract.i15 = extractelement <1 x i64> %8, i32 0
ret i64 %retval.0.extract.i15
}
define i64 @test_psubswv() {
[X86][MMX] Regenerate MMX PSUB commutation test llvm-svn: 325685
2018-02-21 23:07:47 +08:00
; CHECK-LABEL: test_psubswv:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: callq getFirstParam
; CHECK-NEXT: movq %rax, %rbx
; CHECK-NEXT: callq getSecondParam
; CHECK-NEXT: movq %rbx, %mm0
; CHECK-NEXT: movq %rax, %mm1
; CHECK-NEXT: psubsw %mm1, %mm0
; CHECK-NEXT: movq %mm0, %rax
; CHECK-NEXT: popq %rbx
Correct dwarf unwind information in function epilogue This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: * CFI instructions do not affect code generation (they are not counted as instructions when tail duplicating or tail merging) * Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Added CFIInstrInserter pass: * analyzes each basic block to determine cfa offset and register are valid at its entry and exit * verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors * inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D42848 llvm-svn: 330706
2018-04-24 18:32:08 +08:00
; CHECK-NEXT: .cfi_def_cfa_offset 8
[X86][MMX] Regenerate MMX PSUB commutation test llvm-svn: 325685
2018-02-21 23:07:47 +08:00
; CHECK-NEXT: retq
Reapply "Subtract isn't commutative, fix this for MMX psub." with a somewhat randomly chosen cpu that will minimize cpu specific differences on bots. llvm-svn: 181814
2013-05-15 02:33:40 +08:00
entry:
%call = tail call { i64, double } @getFirstParam()
%0 = extractvalue { i64, double } %call, 0
%call2 = tail call { i64, double } @getSecondParam()
%1 = extractvalue { i64, double } %call2, 0
%__m1.0.insert.i = insertelement <1 x i64> undef, i64 %0, i32 0
%__m2.0.insert.i = insertelement <1 x i64> undef, i64 %1, i32 0
%2 = bitcast <1 x i64> %__m1.0.insert.i to <4 x i16>
%3 = bitcast <4 x i16> %2 to x86_mmx
%4 = bitcast <1 x i64> %__m2.0.insert.i to <4 x i16>
%5 = bitcast <4 x i16> %4 to x86_mmx
%6 = tail call x86_mmx @llvm.x86.mmx.psubs.w(x86_mmx %3, x86_mmx %5) nounwind
%7 = bitcast x86_mmx %6 to <4 x i16>
%8 = bitcast <4 x i16> %7 to <1 x i64>
%retval.0.extract.i15 = extractelement <1 x i64> %8, i32 0
ret i64 %retval.0.extract.i15
}
define i64 @test_psubusbv() {
[X86][MMX] Regenerate MMX PSUB commutation test llvm-svn: 325685
2018-02-21 23:07:47 +08:00
; CHECK-LABEL: test_psubusbv:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: callq getFirstParam
; CHECK-NEXT: movq %rax, %rbx
; CHECK-NEXT: callq getSecondParam
; CHECK-NEXT: movq %rbx, %mm0
; CHECK-NEXT: movq %rax, %mm1
; CHECK-NEXT: psubusb %mm1, %mm0
; CHECK-NEXT: movq %mm0, %rax
; CHECK-NEXT: popq %rbx
Correct dwarf unwind information in function epilogue This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: * CFI instructions do not affect code generation (they are not counted as instructions when tail duplicating or tail merging) * Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Added CFIInstrInserter pass: * analyzes each basic block to determine cfa offset and register are valid at its entry and exit * verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors * inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D42848 llvm-svn: 330706
2018-04-24 18:32:08 +08:00
; CHECK-NEXT: .cfi_def_cfa_offset 8
[X86][MMX] Regenerate MMX PSUB commutation test llvm-svn: 325685
2018-02-21 23:07:47 +08:00
; CHECK-NEXT: retq
Reapply "Subtract isn't commutative, fix this for MMX psub." with a somewhat randomly chosen cpu that will minimize cpu specific differences on bots. llvm-svn: 181814
2013-05-15 02:33:40 +08:00
entry:
%call = tail call { i64, double } @getFirstParam()
%0 = extractvalue { i64, double } %call, 0
%call2 = tail call { i64, double } @getSecondParam()
%1 = extractvalue { i64, double } %call2, 0
%__m1.0.insert.i = insertelement <1 x i64> undef, i64 %0, i32 0
%__m2.0.insert.i = insertelement <1 x i64> undef, i64 %1, i32 0
%2 = bitcast <1 x i64> %__m1.0.insert.i to <8 x i8>
%3 = bitcast <8 x i8> %2 to x86_mmx
%4 = bitcast <1 x i64> %__m2.0.insert.i to <8 x i8>
%5 = bitcast <8 x i8> %4 to x86_mmx
%6 = tail call x86_mmx @llvm.x86.mmx.psubus.b(x86_mmx %3, x86_mmx %5) nounwind
%7 = bitcast x86_mmx %6 to <8 x i8>
%8 = bitcast <8 x i8> %7 to <1 x i64>
%retval.0.extract.i15 = extractelement <1 x i64> %8, i32 0
ret i64 %retval.0.extract.i15
}
define i64 @test_psubuswv() {
[X86][MMX] Regenerate MMX PSUB commutation test llvm-svn: 325685
2018-02-21 23:07:47 +08:00
; CHECK-LABEL: test_psubuswv:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: callq getFirstParam
; CHECK-NEXT: movq %rax, %rbx
; CHECK-NEXT: callq getSecondParam
; CHECK-NEXT: movq %rbx, %mm0
; CHECK-NEXT: movq %rax, %mm1
; CHECK-NEXT: psubusw %mm1, %mm0
; CHECK-NEXT: movq %mm0, %rax
; CHECK-NEXT: popq %rbx
Correct dwarf unwind information in function epilogue This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: * CFI instructions do not affect code generation (they are not counted as instructions when tail duplicating or tail merging) * Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Added CFIInstrInserter pass: * analyzes each basic block to determine cfa offset and register are valid at its entry and exit * verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors * inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D42848 llvm-svn: 330706
2018-04-24 18:32:08 +08:00
; CHECK-NEXT: .cfi_def_cfa_offset 8
[X86][MMX] Regenerate MMX PSUB commutation test llvm-svn: 325685
2018-02-21 23:07:47 +08:00
; CHECK-NEXT: retq
Reapply "Subtract isn't commutative, fix this for MMX psub." with a somewhat randomly chosen cpu that will minimize cpu specific differences on bots. llvm-svn: 181814
2013-05-15 02:33:40 +08:00
entry:
%call = tail call { i64, double } @getFirstParam()
%0 = extractvalue { i64, double } %call, 0
%call2 = tail call { i64, double } @getSecondParam()
%1 = extractvalue { i64, double } %call2, 0
%__m1.0.insert.i = insertelement <1 x i64> undef, i64 %0, i32 0
%__m2.0.insert.i = insertelement <1 x i64> undef, i64 %1, i32 0
%2 = bitcast <1 x i64> %__m1.0.insert.i to <4 x i16>
%3 = bitcast <4 x i16> %2 to x86_mmx
%4 = bitcast <1 x i64> %__m2.0.insert.i to <4 x i16>
%5 = bitcast <4 x i16> %4 to x86_mmx
%6 = tail call x86_mmx @llvm.x86.mmx.psubus.w(x86_mmx %3, x86_mmx %5) nounwind
%7 = bitcast x86_mmx %6 to <4 x i16>
%8 = bitcast <4 x i16> %7 to <1 x i64>
%retval.0.extract.i15 = extractelement <1 x i64> %8, i32 0
ret i64 %retval.0.extract.i15
}
declare x86_mmx @llvm.x86.mmx.psubus.w(x86_mmx, x86_mmx) nounwind readnone
declare x86_mmx @llvm.x86.mmx.psubus.b(x86_mmx, x86_mmx) nounwind readnone
declare x86_mmx @llvm.x86.mmx.psubs.w(x86_mmx, x86_mmx) nounwind readnone
declare x86_mmx @llvm.x86.mmx.psubs.b(x86_mmx, x86_mmx) nounwind readnone
declare x86_mmx @llvm.x86.mmx.psub.d(x86_mmx, x86_mmx) nounwind readnone
declare x86_mmx @llvm.x86.mmx.psub.w(x86_mmx, x86_mmx) nounwind readnone
declare x86_mmx @llvm.x86.mmx.psub.b(x86_mmx, x86_mmx) nounwind readnone