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llvm-project/llvm/test/CodeGen/X86/lzcnt-tzcnt.ll

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[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+bmi,+lzcnt | FileCheck %s
; LZCNT and TZCNT will always produce the operand size when the input operand
; is zero. This test is to verify that we efficiently select LZCNT/TZCNT
; based on the fact that the 'icmp+select' sequence is always redundant
; in every function defined below.
define i16 @test1_ctlz(i16 %v) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test1_ctlz:
; CHECK: # %bb.0:
; CHECK-NEXT: lzcntw %di, %ax
; CHECK-NEXT: retq
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
%cnt = tail call i16 @llvm.ctlz.i16(i16 %v, i1 true)
%tobool = icmp eq i16 %v, 0
%cond = select i1 %tobool, i16 16, i16 %cnt
ret i16 %cond
}
define i32 @test2_ctlz(i32 %v) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test2_ctlz:
; CHECK: # %bb.0:
; CHECK-NEXT: lzcntl %edi, %eax
; CHECK-NEXT: retq
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
%cnt = tail call i32 @llvm.ctlz.i32(i32 %v, i1 true)
%tobool = icmp eq i32 %v, 0
%cond = select i1 %tobool, i32 32, i32 %cnt
ret i32 %cond
}
define i64 @test3_ctlz(i64 %v) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test3_ctlz:
; CHECK: # %bb.0:
; CHECK-NEXT: lzcntq %rdi, %rax
; CHECK-NEXT: retq
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
%cnt = tail call i64 @llvm.ctlz.i64(i64 %v, i1 true)
%tobool = icmp eq i64 %v, 0
%cond = select i1 %tobool, i64 64, i64 %cnt
ret i64 %cond
}
define i16 @test4_ctlz(i16 %v) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test4_ctlz:
; CHECK: # %bb.0:
; CHECK-NEXT: lzcntw %di, %ax
; CHECK-NEXT: retq
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
%cnt = tail call i16 @llvm.ctlz.i16(i16 %v, i1 true)
%tobool = icmp eq i16 0, %v
%cond = select i1 %tobool, i16 16, i16 %cnt
ret i16 %cond
}
define i32 @test5_ctlz(i32 %v) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test5_ctlz:
; CHECK: # %bb.0:
; CHECK-NEXT: lzcntl %edi, %eax
; CHECK-NEXT: retq
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
%cnt = tail call i32 @llvm.ctlz.i32(i32 %v, i1 true)
%tobool = icmp eq i32 0, %v
%cond = select i1 %tobool, i32 32, i32 %cnt
ret i32 %cond
}
define i64 @test6_ctlz(i64 %v) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test6_ctlz:
; CHECK: # %bb.0:
; CHECK-NEXT: lzcntq %rdi, %rax
; CHECK-NEXT: retq
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
%cnt = tail call i64 @llvm.ctlz.i64(i64 %v, i1 true)
%tobool = icmp eq i64 0, %v
%cond = select i1 %tobool, i64 64, i64 %cnt
ret i64 %cond
}
define i16 @test10_ctlz(i16* %ptr) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test10_ctlz:
; CHECK: # %bb.0:
; CHECK-NEXT: lzcntw (%rdi), %ax
; CHECK-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%v = load i16, i16* %ptr
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
%cnt = tail call i16 @llvm.ctlz.i16(i16 %v, i1 true)
%tobool = icmp eq i16 %v, 0
%cond = select i1 %tobool, i16 16, i16 %cnt
ret i16 %cond
}
define i32 @test11_ctlz(i32* %ptr) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test11_ctlz:
; CHECK: # %bb.0:
; CHECK-NEXT: lzcntl (%rdi), %eax
; CHECK-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%v = load i32, i32* %ptr
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
%cnt = tail call i32 @llvm.ctlz.i32(i32 %v, i1 true)
%tobool = icmp eq i32 %v, 0
%cond = select i1 %tobool, i32 32, i32 %cnt
ret i32 %cond
}
define i64 @test12_ctlz(i64* %ptr) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test12_ctlz:
; CHECK: # %bb.0:
; CHECK-NEXT: lzcntq (%rdi), %rax
; CHECK-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%v = load i64, i64* %ptr
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
%cnt = tail call i64 @llvm.ctlz.i64(i64 %v, i1 true)
%tobool = icmp eq i64 %v, 0
%cond = select i1 %tobool, i64 64, i64 %cnt
ret i64 %cond
}
define i16 @test13_ctlz(i16* %ptr) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test13_ctlz:
; CHECK: # %bb.0:
; CHECK-NEXT: lzcntw (%rdi), %ax
; CHECK-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%v = load i16, i16* %ptr
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
%cnt = tail call i16 @llvm.ctlz.i16(i16 %v, i1 true)
%tobool = icmp eq i16 0, %v
%cond = select i1 %tobool, i16 16, i16 %cnt
ret i16 %cond
}
define i32 @test14_ctlz(i32* %ptr) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test14_ctlz:
; CHECK: # %bb.0:
; CHECK-NEXT: lzcntl (%rdi), %eax
; CHECK-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%v = load i32, i32* %ptr
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
%cnt = tail call i32 @llvm.ctlz.i32(i32 %v, i1 true)
%tobool = icmp eq i32 0, %v
%cond = select i1 %tobool, i32 32, i32 %cnt
ret i32 %cond
}
define i64 @test15_ctlz(i64* %ptr) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test15_ctlz:
; CHECK: # %bb.0:
; CHECK-NEXT: lzcntq (%rdi), %rax
; CHECK-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%v = load i64, i64* %ptr
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
%cnt = tail call i64 @llvm.ctlz.i64(i64 %v, i1 true)
%tobool = icmp eq i64 0, %v
%cond = select i1 %tobool, i64 64, i64 %cnt
ret i64 %cond
}
define i16 @test1_cttz(i16 %v) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test1_cttz:
; CHECK: # %bb.0:
; CHECK-NEXT: tzcntw %di, %ax
; CHECK-NEXT: retq
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
%cnt = tail call i16 @llvm.cttz.i16(i16 %v, i1 true)
%tobool = icmp eq i16 %v, 0
%cond = select i1 %tobool, i16 16, i16 %cnt
ret i16 %cond
}
define i32 @test2_cttz(i32 %v) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test2_cttz:
; CHECK: # %bb.0:
; CHECK-NEXT: tzcntl %edi, %eax
; CHECK-NEXT: retq
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
%cnt = tail call i32 @llvm.cttz.i32(i32 %v, i1 true)
%tobool = icmp eq i32 %v, 0
%cond = select i1 %tobool, i32 32, i32 %cnt
ret i32 %cond
}
define i64 @test3_cttz(i64 %v) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test3_cttz:
; CHECK: # %bb.0:
; CHECK-NEXT: tzcntq %rdi, %rax
; CHECK-NEXT: retq
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
%cnt = tail call i64 @llvm.cttz.i64(i64 %v, i1 true)
%tobool = icmp eq i64 %v, 0
%cond = select i1 %tobool, i64 64, i64 %cnt
ret i64 %cond
}
define i16 @test4_cttz(i16 %v) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test4_cttz:
; CHECK: # %bb.0:
; CHECK-NEXT: tzcntw %di, %ax
; CHECK-NEXT: retq
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
%cnt = tail call i16 @llvm.cttz.i16(i16 %v, i1 true)
%tobool = icmp eq i16 0, %v
%cond = select i1 %tobool, i16 16, i16 %cnt
ret i16 %cond
}
define i32 @test5_cttz(i32 %v) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test5_cttz:
; CHECK: # %bb.0:
; CHECK-NEXT: tzcntl %edi, %eax
; CHECK-NEXT: retq
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
%cnt = tail call i32 @llvm.cttz.i32(i32 %v, i1 true)
%tobool = icmp eq i32 0, %v
%cond = select i1 %tobool, i32 32, i32 %cnt
ret i32 %cond
}
define i64 @test6_cttz(i64 %v) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test6_cttz:
; CHECK: # %bb.0:
; CHECK-NEXT: tzcntq %rdi, %rax
; CHECK-NEXT: retq
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
%cnt = tail call i64 @llvm.cttz.i64(i64 %v, i1 true)
%tobool = icmp eq i64 0, %v
%cond = select i1 %tobool, i64 64, i64 %cnt
ret i64 %cond
}
define i16 @test10_cttz(i16* %ptr) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test10_cttz:
; CHECK: # %bb.0:
; CHECK-NEXT: tzcntw (%rdi), %ax
; CHECK-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%v = load i16, i16* %ptr
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
%cnt = tail call i16 @llvm.cttz.i16(i16 %v, i1 true)
%tobool = icmp eq i16 %v, 0
%cond = select i1 %tobool, i16 16, i16 %cnt
ret i16 %cond
}
define i32 @test11_cttz(i32* %ptr) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test11_cttz:
; CHECK: # %bb.0:
; CHECK-NEXT: tzcntl (%rdi), %eax
; CHECK-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%v = load i32, i32* %ptr
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
%cnt = tail call i32 @llvm.cttz.i32(i32 %v, i1 true)
%tobool = icmp eq i32 %v, 0
%cond = select i1 %tobool, i32 32, i32 %cnt
ret i32 %cond
}
define i64 @test12_cttz(i64* %ptr) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test12_cttz:
; CHECK: # %bb.0:
; CHECK-NEXT: tzcntq (%rdi), %rax
; CHECK-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%v = load i64, i64* %ptr
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
%cnt = tail call i64 @llvm.cttz.i64(i64 %v, i1 true)
%tobool = icmp eq i64 %v, 0
%cond = select i1 %tobool, i64 64, i64 %cnt
ret i64 %cond
}
define i16 @test13_cttz(i16* %ptr) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test13_cttz:
; CHECK: # %bb.0:
; CHECK-NEXT: tzcntw (%rdi), %ax
; CHECK-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%v = load i16, i16* %ptr
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
%cnt = tail call i16 @llvm.cttz.i16(i16 %v, i1 true)
%tobool = icmp eq i16 0, %v
%cond = select i1 %tobool, i16 16, i16 %cnt
ret i16 %cond
}
define i32 @test14_cttz(i32* %ptr) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test14_cttz:
; CHECK: # %bb.0:
; CHECK-NEXT: tzcntl (%rdi), %eax
; CHECK-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%v = load i32, i32* %ptr
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
%cnt = tail call i32 @llvm.cttz.i32(i32 %v, i1 true)
%tobool = icmp eq i32 0, %v
%cond = select i1 %tobool, i32 32, i32 %cnt
ret i32 %cond
}
define i64 @test15_cttz(i64* %ptr) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test15_cttz:
; CHECK: # %bb.0:
; CHECK-NEXT: tzcntq (%rdi), %rax
; CHECK-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%v = load i64, i64* %ptr
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
%cnt = tail call i64 @llvm.cttz.i64(i64 %v, i1 true)
%tobool = icmp eq i64 0, %v
%cond = select i1 %tobool, i64 64, i64 %cnt
ret i64 %cond
}
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
define i16 @test4b_ctlz(i16 %v) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test4b_ctlz:
; CHECK: # %bb.0:
; CHECK-NEXT: lzcntw %di, %ax
; CHECK-NEXT: retq
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
%cnt = tail call i16 @llvm.ctlz.i16(i16 %v, i1 true)
%tobool = icmp ne i16 %v, 0
%cond = select i1 %tobool, i16 %cnt, i16 16
ret i16 %cond
}
define i32 @test5b_ctlz(i32 %v) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test5b_ctlz:
; CHECK: # %bb.0:
; CHECK-NEXT: lzcntl %edi, %eax
; CHECK-NEXT: retq
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
%cnt = tail call i32 @llvm.ctlz.i32(i32 %v, i1 true)
%tobool = icmp ne i32 %v, 0
%cond = select i1 %tobool, i32 %cnt, i32 32
ret i32 %cond
}
define i64 @test6b_ctlz(i64 %v) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test6b_ctlz:
; CHECK: # %bb.0:
; CHECK-NEXT: lzcntq %rdi, %rax
; CHECK-NEXT: retq
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
%cnt = tail call i64 @llvm.ctlz.i64(i64 %v, i1 true)
%tobool = icmp ne i64 %v, 0
%cond = select i1 %tobool, i64 %cnt, i64 64
ret i64 %cond
}
define i16 @test4b_cttz(i16 %v) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test4b_cttz:
; CHECK: # %bb.0:
; CHECK-NEXT: tzcntw %di, %ax
; CHECK-NEXT: retq
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
%cnt = tail call i16 @llvm.cttz.i16(i16 %v, i1 true)
%tobool = icmp ne i16 %v, 0
%cond = select i1 %tobool, i16 %cnt, i16 16
ret i16 %cond
}
define i32 @test5b_cttz(i32 %v) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test5b_cttz:
; CHECK: # %bb.0:
; CHECK-NEXT: tzcntl %edi, %eax
; CHECK-NEXT: retq
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
%cnt = tail call i32 @llvm.cttz.i32(i32 %v, i1 true)
%tobool = icmp ne i32 %v, 0
%cond = select i1 %tobool, i32 %cnt, i32 32
ret i32 %cond
}
define i64 @test6b_cttz(i64 %v) {
[X86] Auto-generate checks. NFC llvm-svn: 324367
2018-02-07 02:18:49 +08:00
; CHECK-LABEL: test6b_cttz:
; CHECK: # %bb.0:
; CHECK-NEXT: tzcntq %rdi, %rax
; CHECK-NEXT: retq
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
%cnt = tail call i64 @llvm.cttz.i64(i64 %v, i1 true)
%tobool = icmp ne i64 %v, 0
%cond = select i1 %tobool, i64 %cnt, i64 64
ret i64 %cond
}
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
declare i64 @llvm.cttz.i64(i64, i1)
declare i32 @llvm.cttz.i32(i32, i1)
declare i16 @llvm.cttz.i16(i16, i1)
declare i64 @llvm.ctlz.i64(i64, i1)
declare i32 @llvm.ctlz.i32(i32, i1)
declare i16 @llvm.ctlz.i16(i16, i1)