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llvm-project/llvm/test/CodeGen/X86/combine-udiv.ll

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[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE,SSE41
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX,AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+xop | FileCheck %s --check-prefixes=CHECK,XOP
[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
[X86] Add srem/udiv/urem by one combine tests llvm-svn: 321826
2018-01-05 06:08:36 +08:00
; fold (udiv x, 1) -> x
define i32 @combine_udiv_by_one(i32 %x) {
; CHECK-LABEL: combine_udiv_by_one:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
%1 = udiv i32 %x, 1
ret i32 %1
}
define <4 x i32> @combine_vec_udiv_by_one(<4 x i32> %x) {
; CHECK-LABEL: combine_vec_udiv_by_one:
; CHECK: # %bb.0:
; CHECK-NEXT: retq
%1 = udiv <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %1
}
[DAGCombiner] Add special case fast paths for udiv x,1 and udiv x,-1 udiv x,-1 was going down the (slow) BuildUDIV route resulting in unnecessary shifts. llvm-svn: 336701
2018-07-11 00:33:07 +08:00
; fold (udiv x, -1) -> select((icmp eq x, -1), 1, 0)
[X86] Add srem/udiv/urem by constant tests Match the tests in combine-sdiv.ll llvm-svn: 336694
2018-07-11 00:08:28 +08:00
define i32 @combine_udiv_by_negone(i32 %x) {
; CHECK-LABEL: combine_udiv_by_negone:
; CHECK: # %bb.0:
[DAGCombiner] Add special case fast paths for udiv x,1 and udiv x,-1 udiv x,-1 was going down the (slow) BuildUDIV route resulting in unnecessary shifts. llvm-svn: 336701
2018-07-11 00:33:07 +08:00
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpl $-1, %edi
; CHECK-NEXT: sete %al
[X86] Add srem/udiv/urem by constant tests Match the tests in combine-sdiv.ll llvm-svn: 336694
2018-07-11 00:08:28 +08:00
; CHECK-NEXT: retq
%1 = udiv i32 %x, -1
ret i32 %1
}
define <4 x i32> @combine_vec_udiv_by_negone(<4 x i32> %x) {
; SSE-LABEL: combine_vec_udiv_by_negone:
; SSE: # %bb.0:
[DAGCombiner] Add special case fast paths for udiv x,1 and udiv x,-1 udiv x,-1 was going down the (slow) BuildUDIV route resulting in unnecessary shifts. llvm-svn: 336701
2018-07-11 00:33:07 +08:00
; SSE-NEXT: pcmpeqd %xmm1, %xmm1
; SSE-NEXT: pcmpeqd %xmm1, %xmm0
[X86] Add srem/udiv/urem by constant tests Match the tests in combine-sdiv.ll llvm-svn: 336694
2018-07-11 00:08:28 +08:00
; SSE-NEXT: psrld $31, %xmm0
; SSE-NEXT: retq
;
[DAGCombiner] Add special case fast paths for udiv x,1 and udiv x,-1 udiv x,-1 was going down the (slow) BuildUDIV route resulting in unnecessary shifts. llvm-svn: 336701
2018-07-11 00:33:07 +08:00
; AVX-LABEL: combine_vec_udiv_by_negone:
; AVX: # %bb.0:
; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpsrld $31, %xmm0, %xmm0
; AVX-NEXT: retq
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
;
; XOP-LABEL: combine_vec_udiv_by_negone:
; XOP: # %bb.0:
; XOP-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; XOP-NEXT: vpcomeqd %xmm1, %xmm0, %xmm0
; XOP-NEXT: vpsrld $31, %xmm0, %xmm0
; XOP-NEXT: retq
[X86] Add srem/udiv/urem by constant tests Match the tests in combine-sdiv.ll llvm-svn: 336694
2018-07-11 00:08:28 +08:00
%1 = udiv <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
ret <4 x i32> %1
}
; fold (udiv x, INT_MIN) -> (srl x, 31)
define i32 @combine_udiv_by_minsigned(i32 %x) {
; CHECK-LABEL: combine_udiv_by_minsigned:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edi, %eax
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; CHECK-NEXT: shrl $31, %eax
[X86] Add srem/udiv/urem by constant tests Match the tests in combine-sdiv.ll llvm-svn: 336694
2018-07-11 00:08:28 +08:00
; CHECK-NEXT: retq
%1 = udiv i32 %x, -2147483648
ret i32 %1
}
define <4 x i32> @combine_vec_udiv_by_minsigned(<4 x i32> %x) {
; SSE-LABEL: combine_vec_udiv_by_minsigned:
; SSE: # %bb.0:
; SSE-NEXT: psrld $31, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_udiv_by_minsigned:
; AVX: # %bb.0:
; AVX-NEXT: vpsrld $31, %xmm0, %xmm0
; AVX-NEXT: retq
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
;
; XOP-LABEL: combine_vec_udiv_by_minsigned:
; XOP: # %bb.0:
; XOP-NEXT: vpsrld $31, %xmm0, %xmm0
; XOP-NEXT: retq
[X86] Add srem/udiv/urem by constant tests Match the tests in combine-sdiv.ll llvm-svn: 336694
2018-07-11 00:08:28 +08:00
%1 = udiv <4 x i32> %x, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
ret <4 x i32> %1
}
[DAGCombiner] Fold 0 div/rem X to 0 Reviewers: RKSimon, spatel, javed.absar, craig.topper, t.p.northover Reviewed By: RKSimon Subscribers: craig.topper, llvm-commits Differential Revision: https://reviews.llvm.org/D52504 llvm-svn: 345721
2018-10-31 22:18:57 +08:00
; fold (udiv 0, x) -> 0
[X86] Add tests showing missing div/rem 0, X -> 0 combines llvm-svn: 339562
2018-08-13 21:29:54 +08:00
define i32 @combine_udiv_zero(i32 %x) {
; CHECK-LABEL: combine_udiv_zero:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retq
%1 = udiv i32 0, %x
ret i32 %1
}
define <4 x i32> @combine_vec_udiv_zero(<4 x i32> %x) {
[DAGCombiner] Fold 0 div/rem X to 0 Reviewers: RKSimon, spatel, javed.absar, craig.topper, t.p.northover Reviewed By: RKSimon Subscribers: craig.topper, llvm-commits Differential Revision: https://reviews.llvm.org/D52504 llvm-svn: 345721
2018-10-31 22:18:57 +08:00
; SSE-LABEL: combine_vec_udiv_zero:
; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: retq
[X86] Add tests showing missing div/rem 0, X -> 0 combines llvm-svn: 339562
2018-08-13 21:29:54 +08:00
;
; AVX-LABEL: combine_vec_udiv_zero:
; AVX: # %bb.0:
[DAGCombiner] Fold 0 div/rem X to 0 Reviewers: RKSimon, spatel, javed.absar, craig.topper, t.p.northover Reviewed By: RKSimon Subscribers: craig.topper, llvm-commits Differential Revision: https://reviews.llvm.org/D52504 llvm-svn: 345721
2018-10-31 22:18:57 +08:00
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86] Add tests showing missing div/rem 0, X -> 0 combines llvm-svn: 339562
2018-08-13 21:29:54 +08:00
; AVX-NEXT: retq
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
;
; XOP-LABEL: combine_vec_udiv_zero:
; XOP: # %bb.0:
[DAGCombiner] Fold 0 div/rem X to 0 Reviewers: RKSimon, spatel, javed.absar, craig.topper, t.p.northover Reviewed By: RKSimon Subscribers: craig.topper, llvm-commits Differential Revision: https://reviews.llvm.org/D52504 llvm-svn: 345721
2018-10-31 22:18:57 +08:00
; XOP-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
; XOP-NEXT: retq
[X86] Add tests showing missing div/rem 0, X -> 0 combines llvm-svn: 339562
2018-08-13 21:29:54 +08:00
%1 = udiv <4 x i32> zeroinitializer, %x
ret <4 x i32> %1
}
[DAGCombiner] Add X / X -> 1 & X % X -> 0 folds Adds more divrem folds to try and get in sync with InstructionSimplify Differential Revision: https://reviews.llvm.org/D50636 llvm-svn: 340919
2018-08-29 19:30:16 +08:00
; fold (udiv x, x) -> 1
[X86] Show missed combine for X/X for SDIV/UDIV and X%X for SREM/UREM llvm-svn: 321807
2018-01-05 02:20:46 +08:00
define i32 @combine_udiv_dupe(i32 %x) {
[X86] Add common CHECK prefix for tests without SSE/AVX codegen llvm-svn: 321810
2018-01-05 02:23:46 +08:00
; CHECK-LABEL: combine_udiv_dupe:
; CHECK: # %bb.0:
[DAGCombiner] Add X / X -> 1 & X % X -> 0 folds Adds more divrem folds to try and get in sync with InstructionSimplify Differential Revision: https://reviews.llvm.org/D50636 llvm-svn: 340919
2018-08-29 19:30:16 +08:00
; CHECK-NEXT: movl $1, %eax
[X86] Add common CHECK prefix for tests without SSE/AVX codegen llvm-svn: 321810
2018-01-05 02:23:46 +08:00
; CHECK-NEXT: retq
[X86] Show missed combine for X/X for SDIV/UDIV and X%X for SREM/UREM llvm-svn: 321807
2018-01-05 02:20:46 +08:00
%1 = udiv i32 %x, %x
ret i32 %1
}
define <4 x i32> @combine_vec_udiv_dupe(<4 x i32> %x) {
[DAGCombiner] Add X / X -> 1 & X % X -> 0 folds Adds more divrem folds to try and get in sync with InstructionSimplify Differential Revision: https://reviews.llvm.org/D50636 llvm-svn: 340919
2018-08-29 19:30:16 +08:00
; SSE-LABEL: combine_vec_udiv_dupe:
; SSE: # %bb.0:
; SSE-NEXT: movaps {{.*#+}} xmm0 = [1,1,1,1]
; SSE-NEXT: retq
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
;
[DAGCombiner] Add X / X -> 1 & X % X -> 0 folds Adds more divrem folds to try and get in sync with InstructionSimplify Differential Revision: https://reviews.llvm.org/D50636 llvm-svn: 340919
2018-08-29 19:30:16 +08:00
; AVX1-LABEL: combine_vec_udiv_dupe:
; AVX1: # %bb.0:
; AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [1,1,1,1]
; AVX1-NEXT: retq
[X86] Show missed combine for X/X for SDIV/UDIV and X%X for SREM/UREM llvm-svn: 321807
2018-01-05 02:20:46 +08:00
;
[DAGCombiner] Add X / X -> 1 & X % X -> 0 folds Adds more divrem folds to try and get in sync with InstructionSimplify Differential Revision: https://reviews.llvm.org/D50636 llvm-svn: 340919
2018-08-29 19:30:16 +08:00
; AVX2-LABEL: combine_vec_udiv_dupe:
; AVX2: # %bb.0:
; AVX2-NEXT: vbroadcastss {{.*#+}} xmm0 = [1,1,1,1]
; AVX2-NEXT: retq
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
;
; XOP-LABEL: combine_vec_udiv_dupe:
; XOP: # %bb.0:
[DAGCombiner] Add X / X -> 1 & X % X -> 0 folds Adds more divrem folds to try and get in sync with InstructionSimplify Differential Revision: https://reviews.llvm.org/D50636 llvm-svn: 340919
2018-08-29 19:30:16 +08:00
; XOP-NEXT: vmovaps {{.*#+}} xmm0 = [1,1,1,1]
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
; XOP-NEXT: retq
[X86] Show missed combine for X/X for SDIV/UDIV and X%X for SREM/UREM llvm-svn: 321807
2018-01-05 02:20:46 +08:00
%1 = udiv <4 x i32> %x, %x
ret <4 x i32> %1
}
[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
; fold (udiv x, (1 << c)) -> x >>u c
define <4 x i32> @combine_vec_udiv_by_pow2a(<4 x i32> %x) {
; SSE-LABEL: combine_vec_udiv_by_pow2a:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SSE: # %bb.0:
[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
; SSE-NEXT: psrld $2, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_udiv_by_pow2a:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; AVX: # %bb.0:
[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
; AVX-NEXT: vpsrld $2, %xmm0, %xmm0
; AVX-NEXT: retq
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
;
; XOP-LABEL: combine_vec_udiv_by_pow2a:
; XOP: # %bb.0:
; XOP-NEXT: vpsrld $2, %xmm0, %xmm0
; XOP-NEXT: retq
[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
%1 = udiv <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>
ret <4 x i32> %1
}
define <4 x i32> @combine_vec_udiv_by_pow2b(<4 x i32> %x) {
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
; SSE2-LABEL: combine_vec_udiv_by_pow2b:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrld $4, %xmm1
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: psrld $3, %xmm2
; SSE2-NEXT: punpckhqdq {{.*#+}} xmm2 = xmm2[1],xmm1[1]
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrld $2, %xmm1
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3],xmm2[0,3]
; SSE2-NEXT: retq
;
; SSE41-LABEL: combine_vec_udiv_by_pow2b:
; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: psrld $3, %xmm1
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1,2,3],xmm1[4,5,6,7]
; SSE41-NEXT: psrld $4, %xmm0
; SSE41-NEXT: psrld $2, %xmm2
; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm0[4,5,6,7]
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: retq
[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
;
[DAGCombiner] Try to use SelectionDAG::isKnownToBeAPowerOfTwo instead of just APInt::isPowerOf2 Generalize sdiv/udiv/srem/urem combines using APInt::isPowerOf2, which only works for const/splat-const values, to call SelectionDAG::isKnownToBeAPowerOfTwo instead which recognises many more cases. Added a DAGCombiner::BuildLogBase2 helper since PowerOf2 combines often involve taking the log2 of such a value. Differential Revision: https://reviews.llvm.org/D27714 llvm-svn: 289654
2016-12-14 23:08:13 +08:00
; AVX1-LABEL: combine_vec_udiv_by_pow2b:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; AVX1: # %bb.0:
[DAGCombiner] Try to use SelectionDAG::isKnownToBeAPowerOfTwo instead of just APInt::isPowerOf2 Generalize sdiv/udiv/srem/urem combines using APInt::isPowerOf2, which only works for const/splat-const values, to call SelectionDAG::isKnownToBeAPowerOfTwo instead which recognises many more cases. Added a DAGCombiner::BuildLogBase2 helper since PowerOf2 combines often involve taking the log2 of such a value. Differential Revision: https://reviews.llvm.org/D27714 llvm-svn: 289654
2016-12-14 23:08:13 +08:00
; AVX1-NEXT: vpsrld $4, %xmm0, %xmm1
; AVX1-NEXT: vpsrld $2, %xmm0, %xmm2
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1,2,3],xmm1[4,5,6,7]
; AVX1-NEXT: vpsrld $3, %xmm0, %xmm2
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; AVX1-NEXT: retq
;
; AVX2-LABEL: combine_vec_udiv_by_pow2b:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; AVX2: # %bb.0:
[DAGCombiner] Try to use SelectionDAG::isKnownToBeAPowerOfTwo instead of just APInt::isPowerOf2 Generalize sdiv/udiv/srem/urem combines using APInt::isPowerOf2, which only works for const/splat-const values, to call SelectionDAG::isKnownToBeAPowerOfTwo instead which recognises many more cases. Added a DAGCombiner::BuildLogBase2 helper since PowerOf2 combines often involve taking the log2 of such a value. Differential Revision: https://reviews.llvm.org/D27714 llvm-svn: 289654
2016-12-14 23:08:13 +08:00
; AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
;
; XOP-LABEL: combine_vec_udiv_by_pow2b:
; XOP: # %bb.0:
; XOP-NEXT: vpshld {{.*}}(%rip), %xmm0, %xmm0
; XOP-NEXT: retq
[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
%1 = udiv <4 x i32> %x, <i32 1, i32 4, i32 8, i32 16>
ret <4 x i32> %1
}
[SelectionDAG] Recognise splat vector isKnownToBeAPowerOfTwo one/sign bit shift cases. llvm-svn: 301303
2017-04-25 20:29:07 +08:00
define <4 x i32> @combine_vec_udiv_by_pow2c(<4 x i32> %x, <4 x i32> %y) {
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
; SSE2-LABEL: combine_vec_udiv_by_pow2c:
; SSE2: # %bb.0:
; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]
; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: psrld %xmm2, %xmm3
; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm1[0,1,1,1,4,5,6,7]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: psrld %xmm4, %xmm2
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm1[2,3,3,3,4,5,6,7]
; SSE2-NEXT: movdqa %xmm0, %xmm4
; SSE2-NEXT: psrld %xmm3, %xmm4
; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,1,1,4,5,6,7]
; SSE2-NEXT: psrld %xmm1, %xmm0
; SSE2-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm4[1]
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,3],xmm0[0,3]
; SSE2-NEXT: movaps %xmm2, %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: combine_vec_udiv_by_pow2c:
; SSE41: # %bb.0:
; SSE41-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]
; SSE41-NEXT: movdqa %xmm0, %xmm3
; SSE41-NEXT: psrld %xmm2, %xmm3
; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
; SSE41-NEXT: pshuflw {{.*#+}} xmm4 = xmm2[2,3,3,3,4,5,6,7]
; SSE41-NEXT: movdqa %xmm0, %xmm5
; SSE41-NEXT: psrld %xmm4, %xmm5
; SSE41-NEXT: pblendw {{.*#+}} xmm5 = xmm3[0,1,2,3],xmm5[4,5,6,7]
; SSE41-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,1,1,4,5,6,7]
; SSE41-NEXT: movdqa %xmm0, %xmm3
; SSE41-NEXT: psrld %xmm1, %xmm3
; SSE41-NEXT: pshuflw {{.*#+}} xmm1 = xmm2[0,1,1,1,4,5,6,7]
; SSE41-NEXT: psrld %xmm1, %xmm0
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm3[0,1,2,3],xmm0[4,5,6,7]
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm5[2,3],xmm0[4,5],xmm5[6,7]
; SSE41-NEXT: retq
[SelectionDAG] Recognise splat vector isKnownToBeAPowerOfTwo one/sign bit shift cases. llvm-svn: 301303
2017-04-25 20:29:07 +08:00
;
; AVX1-LABEL: combine_vec_udiv_by_pow2c:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; AVX1: # %bb.0:
[SelectionDAG] Recognise splat vector isKnownToBeAPowerOfTwo one/sign bit shift cases. llvm-svn: 301303
2017-04-25 20:29:07 +08:00
; AVX1-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX1-NEXT: vpsrld %xmm2, %xmm0, %xmm2
; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm3
; AVX1-NEXT: vpsrld %xmm3, %xmm0, %xmm3
; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm3 = xmm1[2],xmm3[2],xmm1[3],xmm3[3]
; AVX1-NEXT: vpsrld %xmm3, %xmm0, %xmm3
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX1-NEXT: vpsrld %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7]
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; AVX1-NEXT: retq
;
; AVX2-LABEL: combine_vec_udiv_by_pow2c:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; AVX2: # %bb.0:
[SelectionDAG] Recognise splat vector isKnownToBeAPowerOfTwo one/sign bit shift cases. llvm-svn: 301303
2017-04-25 20:29:07 +08:00
; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
;
; XOP-LABEL: combine_vec_udiv_by_pow2c:
; XOP: # %bb.0:
; XOP-NEXT: vpxor %xmm2, %xmm2, %xmm2
; XOP-NEXT: vpsubd %xmm1, %xmm2, %xmm1
; XOP-NEXT: vpshld %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq
[SelectionDAG] Recognise splat vector isKnownToBeAPowerOfTwo one/sign bit shift cases. llvm-svn: 301303
2017-04-25 20:29:07 +08:00
%1 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y
%2 = udiv <4 x i32> %x, %1
ret <4 x i32> %2
}
[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
define <4 x i32> @combine_vec_udiv_by_shl_pow2a(<4 x i32> %x, <4 x i32> %y) {
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
; SSE2-LABEL: combine_vec_udiv_by_shl_pow2a:
; SSE2: # %bb.0:
; SSE2-NEXT: paddd {{.*}}(%rip), %xmm1
; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]
; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: psrld %xmm2, %xmm3
; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm1[0,1,1,1,4,5,6,7]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: psrld %xmm4, %xmm2
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm1[2,3,3,3,4,5,6,7]
; SSE2-NEXT: movdqa %xmm0, %xmm4
; SSE2-NEXT: psrld %xmm3, %xmm4
; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,1,1,4,5,6,7]
; SSE2-NEXT: psrld %xmm1, %xmm0
; SSE2-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm4[1]
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,3],xmm0[0,3]
; SSE2-NEXT: movaps %xmm2, %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: combine_vec_udiv_by_shl_pow2a:
; SSE41: # %bb.0:
; SSE41-NEXT: paddd {{.*}}(%rip), %xmm1
; SSE41-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]
; SSE41-NEXT: movdqa %xmm0, %xmm3
; SSE41-NEXT: psrld %xmm2, %xmm3
; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
; SSE41-NEXT: pshuflw {{.*#+}} xmm4 = xmm2[2,3,3,3,4,5,6,7]
; SSE41-NEXT: movdqa %xmm0, %xmm5
; SSE41-NEXT: psrld %xmm4, %xmm5
; SSE41-NEXT: pblendw {{.*#+}} xmm5 = xmm3[0,1,2,3],xmm5[4,5,6,7]
; SSE41-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,1,1,4,5,6,7]
; SSE41-NEXT: movdqa %xmm0, %xmm3
; SSE41-NEXT: psrld %xmm1, %xmm3
; SSE41-NEXT: pshuflw {{.*#+}} xmm1 = xmm2[0,1,1,1,4,5,6,7]
; SSE41-NEXT: psrld %xmm1, %xmm0
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm3[0,1,2,3],xmm0[4,5,6,7]
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm5[2,3],xmm0[4,5],xmm5[6,7]
; SSE41-NEXT: retq
[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
;
[X86][SSE] Add AVX1 tests to sdiv/udiv srem/urem combine tests As requested on D27714 llvm-svn: 289652
2016-12-14 22:39:51 +08:00
; AVX1-LABEL: combine_vec_udiv_by_shl_pow2a:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; AVX1: # %bb.0:
[X86][SSE] Add AVX1 tests to sdiv/udiv srem/urem combine tests As requested on D27714 llvm-svn: 289652
2016-12-14 22:39:51 +08:00
; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX1-NEXT: vpsrld %xmm2, %xmm0, %xmm2
; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm3
; AVX1-NEXT: vpsrld %xmm3, %xmm0, %xmm3
; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm3 = xmm1[2],xmm3[2],xmm1[3],xmm3[3]
; AVX1-NEXT: vpsrld %xmm3, %xmm0, %xmm3
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX1-NEXT: vpsrld %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7]
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; AVX1-NEXT: retq
;
; AVX2-LABEL: combine_vec_udiv_by_shl_pow2a:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; AVX2: # %bb.0:
[X86][AVX] Regenerate combine tests with constant broadcast comments llvm-svn: 308128
2017-07-16 19:36:11 +08:00
; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2,2,2,2]
[X86][SSE] Add AVX1 tests to sdiv/udiv srem/urem combine tests As requested on D27714 llvm-svn: 289652
2016-12-14 22:39:51 +08:00
; AVX2-NEXT: vpaddd %xmm2, %xmm1, %xmm1
; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
;
; XOP-LABEL: combine_vec_udiv_by_shl_pow2a:
; XOP: # %bb.0:
; XOP-NEXT: vmovdqa {{.*#+}} xmm2 = [4294967294,4294967294,4294967294,4294967294]
; XOP-NEXT: vpsubd %xmm1, %xmm2, %xmm1
; XOP-NEXT: vpshld %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq
[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
%1 = shl <4 x i32> <i32 4, i32 4, i32 4, i32 4>, %y
%2 = udiv <4 x i32> %x, %1
ret <4 x i32> %2
}
define <4 x i32> @combine_vec_udiv_by_shl_pow2b(<4 x i32> %x, <4 x i32> %y) {
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
; SSE2-LABEL: combine_vec_udiv_by_shl_pow2b:
; SSE2: # %bb.0:
; SSE2-NEXT: paddd {{.*}}(%rip), %xmm1
; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]
; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: psrld %xmm2, %xmm3
; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm1[0,1,1,1,4,5,6,7]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: psrld %xmm4, %xmm2
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm1[2,3,3,3,4,5,6,7]
; SSE2-NEXT: movdqa %xmm0, %xmm4
; SSE2-NEXT: psrld %xmm3, %xmm4
; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,1,1,4,5,6,7]
; SSE2-NEXT: psrld %xmm1, %xmm0
; SSE2-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm4[1]
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,3],xmm0[0,3]
; SSE2-NEXT: movaps %xmm2, %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: combine_vec_udiv_by_shl_pow2b:
; SSE41: # %bb.0:
; SSE41-NEXT: paddd {{.*}}(%rip), %xmm1
; SSE41-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]
; SSE41-NEXT: movdqa %xmm0, %xmm3
; SSE41-NEXT: psrld %xmm2, %xmm3
; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
; SSE41-NEXT: pshuflw {{.*#+}} xmm4 = xmm2[2,3,3,3,4,5,6,7]
; SSE41-NEXT: movdqa %xmm0, %xmm5
; SSE41-NEXT: psrld %xmm4, %xmm5
; SSE41-NEXT: pblendw {{.*#+}} xmm5 = xmm3[0,1,2,3],xmm5[4,5,6,7]
; SSE41-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,1,1,4,5,6,7]
; SSE41-NEXT: movdqa %xmm0, %xmm3
; SSE41-NEXT: psrld %xmm1, %xmm3
; SSE41-NEXT: pshuflw {{.*#+}} xmm1 = xmm2[0,1,1,1,4,5,6,7]
; SSE41-NEXT: psrld %xmm1, %xmm0
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm3[0,1,2,3],xmm0[4,5,6,7]
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm5[2,3],xmm0[4,5],xmm5[6,7]
; SSE41-NEXT: retq
[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
;
[X86][SSE] Add AVX1 tests to sdiv/udiv srem/urem combine tests As requested on D27714 llvm-svn: 289652
2016-12-14 22:39:51 +08:00
; AVX1-LABEL: combine_vec_udiv_by_shl_pow2b:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; AVX1: # %bb.0:
[X86][SSE] Add AVX1 tests to sdiv/udiv srem/urem combine tests As requested on D27714 llvm-svn: 289652
2016-12-14 22:39:51 +08:00
; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1
[DAGCombiner] Try to use SelectionDAG::isKnownToBeAPowerOfTwo instead of just APInt::isPowerOf2 Generalize sdiv/udiv/srem/urem combines using APInt::isPowerOf2, which only works for const/splat-const values, to call SelectionDAG::isKnownToBeAPowerOfTwo instead which recognises many more cases. Added a DAGCombiner::BuildLogBase2 helper since PowerOf2 combines often involve taking the log2 of such a value. Differential Revision: https://reviews.llvm.org/D27714 llvm-svn: 289654
2016-12-14 23:08:13 +08:00
; AVX1-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX1-NEXT: vpsrld %xmm2, %xmm0, %xmm2
; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm3
; AVX1-NEXT: vpsrld %xmm3, %xmm0, %xmm3
; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm3 = xmm1[2],xmm3[2],xmm1[3],xmm3[3]
; AVX1-NEXT: vpsrld %xmm3, %xmm0, %xmm3
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX1-NEXT: vpsrld %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7]
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
[X86][SSE] Add AVX1 tests to sdiv/udiv srem/urem combine tests As requested on D27714 llvm-svn: 289652
2016-12-14 22:39:51 +08:00
; AVX1-NEXT: retq
;
; AVX2-LABEL: combine_vec_udiv_by_shl_pow2b:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; AVX2: # %bb.0:
[DAGCombiner] Try to use SelectionDAG::isKnownToBeAPowerOfTwo instead of just APInt::isPowerOf2 Generalize sdiv/udiv/srem/urem combines using APInt::isPowerOf2, which only works for const/splat-const values, to call SelectionDAG::isKnownToBeAPowerOfTwo instead which recognises many more cases. Added a DAGCombiner::BuildLogBase2 helper since PowerOf2 combines often involve taking the log2 of such a value. Differential Revision: https://reviews.llvm.org/D27714 llvm-svn: 289654
2016-12-14 23:08:13 +08:00
; AVX2-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1
; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
[X86][SSE] Add AVX1 tests to sdiv/udiv srem/urem combine tests As requested on D27714 llvm-svn: 289652
2016-12-14 22:39:51 +08:00
; AVX2-NEXT: retq
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
;
; XOP-LABEL: combine_vec_udiv_by_shl_pow2b:
; XOP: # %bb.0:
; XOP-NEXT: vmovdqa {{.*#+}} xmm2 = [0,4294967294,4294967293,4294967292]
; XOP-NEXT: vpsubd %xmm1, %xmm2, %xmm1
; XOP-NEXT: vpshld %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq
[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
%1 = shl <4 x i32> <i32 1, i32 4, i32 8, i32 16>, %y
%2 = udiv <4 x i32> %x, %1
ret <4 x i32> %2
}
[X86] Add UDIV by uniform/non-uniform constant tests llvm-svn: 336894
2018-07-12 17:04:28 +08:00
; fold (udiv x, c1)
define i32 @combine_udiv_uniform(i32 %x) {
; CHECK-LABEL: combine_udiv_uniform:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edi, %ecx
; CHECK-NEXT: movl $2987803337, %eax # imm = 0xB21642C9
; CHECK-NEXT: imulq %rcx, %rax
; CHECK-NEXT: shrq $36, %rax
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
; CHECK-NEXT: retq
%1 = udiv i32 %x, 23
ret i32 %1
}
define <8 x i16> @combine_vec_udiv_uniform(<8 x i16> %x) {
; SSE-LABEL: combine_vec_udiv_uniform:
; SSE: # %bb.0:
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [25645,25645,25645,25645,25645,25645,25645,25645]
; SSE-NEXT: pmulhuw %xmm0, %xmm1
; SSE-NEXT: psubw %xmm1, %xmm0
; SSE-NEXT: psrlw $1, %xmm0
; SSE-NEXT: paddw %xmm1, %xmm0
; SSE-NEXT: psrlw $4, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_udiv_uniform:
; AVX: # %bb.0:
; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpsrlw $4, %xmm0, %xmm0
; AVX-NEXT: retq
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
;
; XOP-LABEL: combine_vec_udiv_uniform:
; XOP: # %bb.0:
; XOP-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
; XOP-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; XOP-NEXT: vpsrlw $1, %xmm0, %xmm0
; XOP-NEXT: vpaddw %xmm1, %xmm0, %xmm0
; XOP-NEXT: vpsrlw $4, %xmm0, %xmm0
; XOP-NEXT: retq
[X86] Add UDIV by uniform/non-uniform constant tests llvm-svn: 336894
2018-07-12 17:04:28 +08:00
%1 = udiv <8 x i16> %x, <i16 23, i16 23, i16 23, i16 23, i16 23, i16 23, i16 23, i16 23>
ret <8 x i16> %1
}
define <8 x i16> @combine_vec_udiv_nonuniform(<8 x i16> %x) {
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
; SSE2-LABEL: combine_vec_udiv_nonuniform:
; SSE2: # %bb.0:
[X86][SSE] Always enable ISD::SRL -> ISD::MULHU for v8i16 For constant non-uniform cases we'll never introduce more and/andn/or selects than already occur in generic pre-SSE41 ISD::SRL lowering. llvm-svn: 342352
2018-09-17 04:28:38 +08:00
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [65535,65535,65535,0,65535,65535,65535,65535]
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: pand %xmm2, %xmm1
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: psrlw $3, %xmm3
[X86][SSE] Always enable ISD::SRL -> ISD::MULHU for v8i16 For constant non-uniform cases we'll never introduce more and/andn/or selects than already occur in generic pre-SSE41 ISD::SRL lowering. llvm-svn: 342352
2018-09-17 04:28:38 +08:00
; SSE2-NEXT: pandn %xmm3, %xmm2
; SSE2-NEXT: por %xmm1, %xmm2
; SSE2-NEXT: pmulhuw {{.*}}(%rip), %xmm2
; SSE2-NEXT: psubw %xmm2, %xmm0
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
; SSE2-NEXT: movl $32768, %eax # imm = 0x8000
[X86][SSE] Always enable ISD::SRL -> ISD::MULHU for v8i16 For constant non-uniform cases we'll never introduce more and/andn/or selects than already occur in generic pre-SSE41 ISD::SRL lowering. llvm-svn: 342352
2018-09-17 04:28:38 +08:00
; SSE2-NEXT: movd %eax, %xmm1
; SSE2-NEXT: pmulhuw %xmm0, %xmm1
; SSE2-NEXT: paddw %xmm2, %xmm1
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [65535,65535,65535,0,0,65535,65535,0]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pandn %xmm1, %xmm2
[X86][SSE] Always enable ISD::SRL -> ISD::MULHU for v8i16 For constant non-uniform cases we'll never introduce more and/andn/or selects than already occur in generic pre-SSE41 ISD::SRL lowering. llvm-svn: 342352
2018-09-17 04:28:38 +08:00
; SSE2-NEXT: pmulhuw {{.*}}(%rip), %xmm1
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: por %xmm2, %xmm1
[X86][SSE] Always enable ISD::SRL -> ISD::MULHU for v8i16 For constant non-uniform cases we'll never introduce more and/andn/or selects than already occur in generic pre-SSE41 ISD::SRL lowering. llvm-svn: 342352
2018-09-17 04:28:38 +08:00
; SSE2-NEXT: movdqa %xmm1, %xmm0
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
; SSE2-NEXT: retq
;
; SSE41-LABEL: combine_vec_udiv_nonuniform:
; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: psrlw $3, %xmm1
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1,2],xmm1[3],xmm0[4,5,6,7]
; SSE41-NEXT: pmulhuw {{.*}}(%rip), %xmm1
; SSE41-NEXT: psubw %xmm1, %xmm0
; SSE41-NEXT: movl $32768, %eax # imm = 0x8000
; SSE41-NEXT: movd %eax, %xmm2
; SSE41-NEXT: pmulhuw %xmm0, %xmm2
; SSE41-NEXT: paddw %xmm1, %xmm2
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = <4096,2048,8,u,u,2,2,u>
; SSE41-NEXT: pmulhuw %xmm2, %xmm0
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2],xmm2[3,4],xmm0[5,6],xmm2[7]
; SSE41-NEXT: retq
[X86] Add UDIV by uniform/non-uniform constant tests llvm-svn: 336894
2018-07-12 17:04:28 +08:00
;
; AVX-LABEL: combine_vec_udiv_nonuniform:
; AVX: # %bb.0:
[TargetLowering] Add support for non-uniform vectors to BuildUDIV This patch refactors the existing TargetLowering::BuildUDIV base implementation to support non-uniform constant vector denominators. It also includes a fold for MULHU by pow2 constants to SRL which can now more readily occur from BuildUDIV. Differential Revision: https://reviews.llvm.org/D49248 llvm-svn: 339121
2018-08-07 17:51:34 +08:00
; AVX-NEXT: vpsrlw $3, %xmm0, %xmm1
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1,2],xmm1[3],xmm0[4,5,6,7]
; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; AVX-NEXT: movl $32768, %eax # imm = 0x8000
; AVX-NEXT: vmovd %eax, %xmm2
; AVX-NEXT: vpmulhuw %xmm2, %xmm0, %xmm0
; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3,4],xmm1[5,6],xmm0[7]
[X86] Add UDIV by uniform/non-uniform constant tests llvm-svn: 336894
2018-07-12 17:04:28 +08:00
; AVX-NEXT: retq
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
;
; XOP-LABEL: combine_vec_udiv_nonuniform:
; XOP: # %bb.0:
; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm0, %xmm1
; XOP-NEXT: vpmulhuw {{.*}}(%rip), %xmm1, %xmm1
; XOP-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; XOP-NEXT: movl $32768, %eax # imm = 0x8000
; XOP-NEXT: vmovd %eax, %xmm2
; XOP-NEXT: vpmulhuw %xmm2, %xmm0, %xmm0
; XOP-NEXT: vpaddw %xmm1, %xmm0, %xmm0
; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm0, %xmm0
; XOP-NEXT: retq
[X86] Add UDIV by uniform/non-uniform constant tests llvm-svn: 336894
2018-07-12 17:04:28 +08:00
%1 = udiv <8 x i16> %x, <i16 23, i16 34, i16 -23, i16 56, i16 128, i16 -1, i16 -256, i16 -32768>
ret <8 x i16> %1
}
[X86][SSE] Add more UDIV nonuniform-constant vector tests Ensure we cover all paths for vector data as requested on D49248 llvm-svn: 338698
2018-08-02 18:53:53 +08:00
define <8 x i16> @combine_vec_udiv_nonuniform2(<8 x i16> %x) {
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
; SSE2-LABEL: combine_vec_udiv_nonuniform2:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [0,65535,65535,65535,65535,65535,65535,65535]
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: pand %xmm2, %xmm1
; SSE2-NEXT: psrlw $1, %xmm0
; SSE2-NEXT: pandn %xmm0, %xmm2
; SSE2-NEXT: por %xmm2, %xmm1
; SSE2-NEXT: pmulhuw {{.*}}(%rip), %xmm1
; SSE2-NEXT: pmulhuw {{.*}}(%rip), %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: combine_vec_udiv_nonuniform2:
; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: psrlw $1, %xmm1
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0],xmm0[1,2,3,4,5,6,7]
; SSE41-NEXT: pmulhuw {{.*}}(%rip), %xmm1
; SSE41-NEXT: pmulhuw {{.*}}(%rip), %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: retq
[X86][SSE] Add more UDIV nonuniform-constant vector tests Ensure we cover all paths for vector data as requested on D49248 llvm-svn: 338698
2018-08-02 18:53:53 +08:00
;
; AVX-LABEL: combine_vec_udiv_nonuniform2:
; AVX: # %bb.0:
[TargetLowering] Add support for non-uniform vectors to BuildUDIV This patch refactors the existing TargetLowering::BuildUDIV base implementation to support non-uniform constant vector denominators. It also includes a fold for MULHU by pow2 constants to SRL which can now more readily occur from BuildUDIV. Differential Revision: https://reviews.llvm.org/D49248 llvm-svn: 339121
2018-08-07 17:51:34 +08:00
; AVX-NEXT: vpsrlw $1, %xmm0, %xmm1
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3,4,5,6,7]
; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm0
[X86][SSE] Add more UDIV nonuniform-constant vector tests Ensure we cover all paths for vector data as requested on D49248 llvm-svn: 338698
2018-08-02 18:53:53 +08:00
; AVX-NEXT: retq
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
;
; XOP-LABEL: combine_vec_udiv_nonuniform2:
; XOP: # %bb.0:
; XOP-NEXT: movl $65535, %eax # imm = 0xFFFF
; XOP-NEXT: vmovd %eax, %xmm1
; XOP-NEXT: vpshlw %xmm1, %xmm0, %xmm0
; XOP-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm0
; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm0, %xmm0
; XOP-NEXT: retq
[X86][SSE] Add more UDIV nonuniform-constant vector tests Ensure we cover all paths for vector data as requested on D49248 llvm-svn: 338698
2018-08-02 18:53:53 +08:00
%1 = udiv <8 x i16> %x, <i16 -34, i16 35, i16 36, i16 -37, i16 38, i16 -39, i16 40, i16 -41>
ret <8 x i16> %1
}
define <8 x i16> @combine_vec_udiv_nonuniform3(<8 x i16> %x) {
; SSE-LABEL: combine_vec_udiv_nonuniform3:
; SSE: # %bb.0:
[TargetLowering] Add support for non-uniform vectors to BuildUDIV This patch refactors the existing TargetLowering::BuildUDIV base implementation to support non-uniform constant vector denominators. It also includes a fold for MULHU by pow2 constants to SRL which can now more readily occur from BuildUDIV. Differential Revision: https://reviews.llvm.org/D49248 llvm-svn: 339121
2018-08-07 17:51:34 +08:00
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [9363,25645,18351,12137,2115,23705,1041,517]
; SSE-NEXT: pmulhuw %xmm0, %xmm1
; SSE-NEXT: psubw %xmm1, %xmm0
; SSE-NEXT: psrlw $1, %xmm0
; SSE-NEXT: paddw %xmm1, %xmm0
; SSE-NEXT: pmulhuw {{.*}}(%rip), %xmm0
[X86][SSE] Add more UDIV nonuniform-constant vector tests Ensure we cover all paths for vector data as requested on D49248 llvm-svn: 338698
2018-08-02 18:53:53 +08:00
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_udiv_nonuniform3:
; AVX: # %bb.0:
[TargetLowering] Add support for non-uniform vectors to BuildUDIV This patch refactors the existing TargetLowering::BuildUDIV base implementation to support non-uniform constant vector denominators. It also includes a fold for MULHU by pow2 constants to SRL which can now more readily occur from BuildUDIV. Differential Revision: https://reviews.llvm.org/D49248 llvm-svn: 339121
2018-08-07 17:51:34 +08:00
; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm0
[X86][SSE] Add more UDIV nonuniform-constant vector tests Ensure we cover all paths for vector data as requested on D49248 llvm-svn: 338698
2018-08-02 18:53:53 +08:00
; AVX-NEXT: retq
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
;
; XOP-LABEL: combine_vec_udiv_nonuniform3:
; XOP: # %bb.0:
; XOP-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
; XOP-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; XOP-NEXT: vpsrlw $1, %xmm0, %xmm0
; XOP-NEXT: vpaddw %xmm1, %xmm0, %xmm0
; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm0, %xmm0
; XOP-NEXT: retq
[X86][SSE] Add more UDIV nonuniform-constant vector tests Ensure we cover all paths for vector data as requested on D49248 llvm-svn: 338698
2018-08-02 18:53:53 +08:00
%1 = udiv <8 x i16> %x, <i16 7, i16 23, i16 25, i16 27, i16 31, i16 47, i16 63, i16 127>
ret <8 x i16> %1
}
[TargetLowering] BuildUDIV - Early out for divide by one (PR38477) We're not handling the UDIV by one special case properly - for now just early out. llvm-svn: 339229
2018-08-08 18:00:54 +08:00
[X86][SSE] Add non-uniform udiv test that is mostly divide by 1. The test demonstrates over-complicated codegen for a udiv that only has one divisor that doesn't equal 1. This should have allowed the codegen to be a lot simpler (uniform shifts etc.) but only the SSE2 manages to make use of this...... llvm-svn: 340313
2018-08-22 02:02:28 +08:00
define <16 x i8> @combine_vec_udiv_nonuniform4(<16 x i8> %x) {
; SSE2-LABEL: combine_vec_udiv_nonuniform4:
; SSE2: # %bb.0:
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3],xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
; SSE2-NEXT: movl $171, %eax
[SelectionDAG][AArch64][X86] Move legalization of vector MULHS/MULHU from LegalizeDAG to LegalizeVectorOps I believe we should be legalizing these with the rest of vector binary operations. If any custom lowering is required for these nodes, this will give the DAG combine between LegalizeVectorOps and LegalizeDAG to run on the custom code before constant build_vectors are lowered in LegalizeDAG. I've moved MULHU/MULHS handling in AArch64 from Lowering to isel. Moving the lowering earlier caused build_vector+extract_subvector simplifications to kick in which made the generated code worse. Differential Revision: https://reviews.llvm.org/D54276 llvm-svn: 347902
2018-11-30 03:36:17 +08:00
; SSE2-NEXT: movd %eax, %xmm1
; SSE2-NEXT: pmullw %xmm2, %xmm1
; SSE2-NEXT: psrlw $8, %xmm1
; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm1
; SSE2-NEXT: psrlw $8, %xmm1
; SSE2-NEXT: movl $255, %eax
; SSE2-NEXT: movd %eax, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2
[X86][SSE] Add non-uniform udiv test that is mostly divide by 1. The test demonstrates over-complicated codegen for a udiv that only has one divisor that doesn't equal 1. This should have allowed the codegen to be a lot simpler (uniform shifts etc.) but only the SSE2 manages to make use of this...... llvm-svn: 340313
2018-08-22 02:02:28 +08:00
; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
[SelectionDAG][AArch64][X86] Move legalization of vector MULHS/MULHU from LegalizeDAG to LegalizeVectorOps I believe we should be legalizing these with the rest of vector binary operations. If any custom lowering is required for these nodes, this will give the DAG combine between LegalizeVectorOps and LegalizeDAG to run on the custom code before constant build_vectors are lowered in LegalizeDAG. I've moved MULHU/MULHS handling in AArch64 from Lowering to isel. Moving the lowering earlier caused build_vector+extract_subvector simplifications to kick in which made the generated code worse. Differential Revision: https://reviews.llvm.org/D54276 llvm-svn: 347902
2018-11-30 03:36:17 +08:00
; SSE2-NEXT: por %xmm2, %xmm0
[X86][SSE] Add non-uniform udiv test that is mostly divide by 1. The test demonstrates over-complicated codegen for a udiv that only has one divisor that doesn't equal 1. This should have allowed the codegen to be a lot simpler (uniform shifts etc.) but only the SSE2 manages to make use of this...... llvm-svn: 340313
2018-08-22 02:02:28 +08:00
; SSE2-NEXT: retq
;
; SSE41-LABEL: combine_vec_udiv_nonuniform4:
; SSE41: # %bb.0:
[X86][SSE] LowerMULH vXi8 - use SSE shifts directly. We know these vXi16 extended cases are legal constant splat shifts. llvm-svn: 340414
2018-08-22 23:37:11 +08:00
; SSE41-NEXT: movdqa %xmm0, %xmm1
[X86][SSE] Add non-uniform udiv test that is mostly divide by 1. The test demonstrates over-complicated codegen for a udiv that only has one divisor that doesn't equal 1. This should have allowed the codegen to be a lot simpler (uniform shifts etc.) but only the SSE2 manages to make use of this...... llvm-svn: 340313
2018-08-22 02:02:28 +08:00
; SSE41-NEXT: movl $171, %eax
[X86][SSE] LowerMULH vXi8 - use SSE shifts directly. We know these vXi16 extended cases are legal constant splat shifts. llvm-svn: 340414
2018-08-22 23:37:11 +08:00
; SSE41-NEXT: movd %eax, %xmm0
; SSE41-NEXT: pmovzxbw {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
; SSE41-NEXT: pmullw %xmm0, %xmm2
; SSE41-NEXT: psrlw $8, %xmm2
[X86] Add vector shift by immediate to SimplifyDemandedBitsForTargetNode. Summary: This also enables some constant folding from KnownBits propagation. This helps on some cases vXi64 case in 32-bit mode where constant vectors appear as vXi32 and a bitcast. This can prevent getNode from constant folding sra/shl/srl. Reviewers: RKSimon, spatel Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54069 llvm-svn: 346102
2018-11-05 01:31:27 +08:00
; SSE41-NEXT: movdqa %xmm2, %xmm0
[SelectionDAG][AArch64][X86] Move legalization of vector MULHS/MULHU from LegalizeDAG to LegalizeVectorOps I believe we should be legalizing these with the rest of vector binary operations. If any custom lowering is required for these nodes, this will give the DAG combine between LegalizeVectorOps and LegalizeDAG to run on the custom code before constant build_vectors are lowered in LegalizeDAG. I've moved MULHU/MULHS handling in AArch64 from Lowering to isel. Moving the lowering earlier caused build_vector+extract_subvector simplifications to kick in which made the generated code worse. Differential Revision: https://reviews.llvm.org/D54276 llvm-svn: 347902
2018-11-30 03:36:17 +08:00
; SSE41-NEXT: psllw $1, %xmm0
; SSE41-NEXT: psllw $8, %xmm2
; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3,4,5,6,7]
[X86][SSE] Add non-uniform udiv test that is mostly divide by 1. The test demonstrates over-complicated codegen for a udiv that only has one divisor that doesn't equal 1. This should have allowed the codegen to be a lot simpler (uniform shifts etc.) but only the SSE2 manages to make use of this...... llvm-svn: 340313
2018-08-22 02:02:28 +08:00
; SSE41-NEXT: psrlw $8, %xmm2
[X86][SSE] Add SimplifyDemandedVectorElts support for PACKSS/PACKUS instructions. As discussed on rL347240. llvm-svn: 347299
2018-11-20 19:09:46 +08:00
; SSE41-NEXT: packuswb %xmm0, %xmm2
[X86][SSE] Add non-uniform udiv test that is mostly divide by 1. The test demonstrates over-complicated codegen for a udiv that only has one divisor that doesn't equal 1. This should have allowed the codegen to be a lot simpler (uniform shifts etc.) but only the SSE2 manages to make use of this...... llvm-svn: 340313
2018-08-22 02:02:28 +08:00
; SSE41-NEXT: movaps {{.*#+}} xmm0 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
[X86][SSE] LowerMULH vXi8 - use SSE shifts directly. We know these vXi16 extended cases are legal constant splat shifts. llvm-svn: 340414
2018-08-22 23:37:11 +08:00
; SSE41-NEXT: pblendvb %xmm0, %xmm1, %xmm2
[X86][SSE] Add non-uniform udiv test that is mostly divide by 1. The test demonstrates over-complicated codegen for a udiv that only has one divisor that doesn't equal 1. This should have allowed the codegen to be a lot simpler (uniform shifts etc.) but only the SSE2 manages to make use of this...... llvm-svn: 340313
2018-08-22 02:02:28 +08:00
; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: combine_vec_udiv_nonuniform4:
; AVX1: # %bb.0:
; AVX1-NEXT: movl $171, %eax
[X86][SSE] LowerMULH vXi8 - use SSE shifts directly. We know these vXi16 extended cases are legal constant splat shifts. llvm-svn: 340414
2018-08-22 23:37:11 +08:00
; AVX1-NEXT: vmovd %eax, %xmm1
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
[X86] Add vector shift by immediate to SimplifyDemandedBitsForTargetNode. Summary: This also enables some constant folding from KnownBits propagation. This helps on some cases vXi64 case in 32-bit mode where constant vectors appear as vXi32 and a bitcast. This can prevent getNode from constant folding sra/shl/srl. Reviewers: RKSimon, spatel Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54069 llvm-svn: 346102
2018-11-05 01:31:27 +08:00
; AVX1-NEXT: vpmullw %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpsrlw $8, %xmm1, %xmm1
[SelectionDAG][AArch64][X86] Move legalization of vector MULHS/MULHU from LegalizeDAG to LegalizeVectorOps I believe we should be legalizing these with the rest of vector binary operations. If any custom lowering is required for these nodes, this will give the DAG combine between LegalizeVectorOps and LegalizeDAG to run on the custom code before constant build_vectors are lowered in LegalizeDAG. I've moved MULHU/MULHS handling in AArch64 from Lowering to isel. Moving the lowering earlier caused build_vector+extract_subvector simplifications to kick in which made the generated code worse. Differential Revision: https://reviews.llvm.org/D54276 llvm-svn: 347902
2018-11-30 03:36:17 +08:00
; AVX1-NEXT: vpsllw $1, %xmm1, %xmm2
; AVX1-NEXT: vpsllw $8, %xmm1, %xmm1
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3,4,5,6,7]
[X86][SSE] LowerMULH vXi8 - use SSE shifts directly. We know these vXi16 extended cases are legal constant splat shifts. llvm-svn: 340414
2018-08-22 23:37:11 +08:00
; AVX1-NEXT: vpsrlw $8, %xmm1, %xmm1
[X86][SSE] Add SimplifyDemandedVectorElts support for PACKSS/PACKUS instructions. As discussed on rL347240. llvm-svn: 347299
2018-11-20 19:09:46 +08:00
; AVX1-NEXT: vpackuswb %xmm0, %xmm1, %xmm1
[X86][SSE] Add non-uniform udiv test that is mostly divide by 1. The test demonstrates over-complicated codegen for a udiv that only has one divisor that doesn't equal 1. This should have allowed the codegen to be a lot simpler (uniform shifts etc.) but only the SSE2 manages to make use of this...... llvm-svn: 340313
2018-08-22 02:02:28 +08:00
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX1-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: combine_vec_udiv_nonuniform4:
; AVX2: # %bb.0:
; AVX2-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
; AVX2-NEXT: movl $171, %eax
; AVX2-NEXT: vmovd %eax, %xmm2
; AVX2-NEXT: vpmullw %ymm2, %ymm1, %ymm1
; AVX2-NEXT: vpsrlw $8, %ymm1, %ymm1
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX2-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
; AVX2-NEXT: vpsrlw $8, %ymm1, %ymm1
[X86][SSE] Add SimplifyDemandedVectorElts support for PACKSS/PACKUS instructions. As discussed on rL347240. llvm-svn: 347299
2018-11-20 19:09:46 +08:00
; AVX2-NEXT: vpackuswb %xmm0, %xmm1, %xmm1
[X86][SSE] Add non-uniform udiv test that is mostly divide by 1. The test demonstrates over-complicated codegen for a udiv that only has one divisor that doesn't equal 1. This should have allowed the codegen to be a lot simpler (uniform shifts etc.) but only the SSE2 manages to make use of this...... llvm-svn: 340313
2018-08-22 02:02:28 +08:00
; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX2-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
; XOP-LABEL: combine_vec_udiv_nonuniform4:
; XOP: # %bb.0:
; XOP-NEXT: movl $171, %eax
; XOP-NEXT: vmovd %eax, %xmm1
; XOP-NEXT: vpmovzxbw {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
[SelectionDAG][AArch64][X86] Move legalization of vector MULHS/MULHU from LegalizeDAG to LegalizeVectorOps I believe we should be legalizing these with the rest of vector binary operations. If any custom lowering is required for these nodes, this will give the DAG combine between LegalizeVectorOps and LegalizeDAG to run on the custom code before constant build_vectors are lowered in LegalizeDAG. I've moved MULHU/MULHS handling in AArch64 from Lowering to isel. Moving the lowering earlier caused build_vector+extract_subvector simplifications to kick in which made the generated code worse. Differential Revision: https://reviews.llvm.org/D54276 llvm-svn: 347902
2018-11-30 03:36:17 +08:00
; XOP-NEXT: vpmullw %xmm1, %xmm2, %xmm1
; XOP-NEXT: vpxor %xmm2, %xmm2, %xmm2
[X86] Emit PACKUS directly from the v16i8 LowerMULH code instead of using a shuffle. llvm-svn: 347967
2018-11-30 16:32:05 +08:00
; XOP-NEXT: vpperm {{.*#+}} xmm1 = xmm1[1,3,5,7,9,11,13,15],xmm2[1,3,5,7,9,11,13,15]
[X86][SSE] Add non-uniform udiv test that is mostly divide by 1. The test demonstrates over-complicated codegen for a udiv that only has one divisor that doesn't equal 1. This should have allowed the codegen to be a lot simpler (uniform shifts etc.) but only the SSE2 manages to make use of this...... llvm-svn: 340313
2018-08-22 02:02:28 +08:00
; XOP-NEXT: movl $249, %eax
; XOP-NEXT: vmovd %eax, %xmm2
; XOP-NEXT: vpshlb %xmm2, %xmm1, %xmm1
; XOP-NEXT: vmovdqa {{.*#+}} xmm2 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; XOP-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
; XOP-NEXT: retq
%div = udiv <16 x i8> %x, <i8 -64, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
ret <16 x i8> %div
}
[TargetLowering] BuildUDIV - Early out for divide by one (PR38477) We're not handling the UDIV by one special case properly - for now just early out. llvm-svn: 339229
2018-08-08 18:00:54 +08:00
define <8 x i16> @pr38477(<8 x i16> %a0) {
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
; SSE2-LABEL: pr38477:
; SSE2: # %bb.0:
[X86][SSE] Always enable ISD::SRL -> ISD::MULHU for v8i16 For constant non-uniform cases we'll never introduce more and/andn/or selects than already occur in generic pre-SSE41 ISD::SRL lowering. llvm-svn: 342352
2018-09-17 04:28:38 +08:00
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [0,4957,57457,4103,16385,35545,2048,2115]
; SSE2-NEXT: pmulhuw %xmm0, %xmm2
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psubw %xmm2, %xmm1
; SSE2-NEXT: pmulhuw {{.*}}(%rip), %xmm1
; SSE2-NEXT: paddw %xmm2, %xmm1
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [0,65535,65535,65535,65535,65535,0,65535]
; SSE2-NEXT: movdqa %xmm2, %xmm3
; SSE2-NEXT: pandn %xmm1, %xmm3
; SSE2-NEXT: pmulhuw {{.*}}(%rip), %xmm1
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
; SSE2-NEXT: pand %xmm2, %xmm1
[X86][SSE] Always enable ISD::SRL -> ISD::MULHU for v8i16 For constant non-uniform cases we'll never introduce more and/andn/or selects than already occur in generic pre-SSE41 ISD::SRL lowering. llvm-svn: 342352
2018-09-17 04:28:38 +08:00
; SSE2-NEXT: por %xmm3, %xmm1
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [0,65535,65535,65535,65535,65535,65535,65535]
; SSE2-NEXT: pand %xmm2, %xmm1
; SSE2-NEXT: pandn %xmm0, %xmm2
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
; SSE2-NEXT: por %xmm2, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: pr38477:
; SSE41: # %bb.0:
; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [0,4957,57457,4103,16385,35545,2048,2115]
; SSE41-NEXT: pmulhuw %xmm0, %xmm2
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: psubw %xmm2, %xmm1
; SSE41-NEXT: pmulhuw {{.*}}(%rip), %xmm1
; SSE41-NEXT: paddw %xmm2, %xmm1
; SSE41-NEXT: movdqa {{.*#+}} xmm2 = <u,1024,1024,16,4,1024,u,4096>
; SSE41-NEXT: pmulhuw %xmm1, %xmm2
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5],xmm1[6],xmm2[7]
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3,4,5,6,7]
; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: retq
[TargetLowering] BuildUDIV - Early out for divide by one (PR38477) We're not handling the UDIV by one special case properly - for now just early out. llvm-svn: 339229
2018-08-08 18:00:54 +08:00
;
; AVX-LABEL: pr38477:
; AVX: # %bb.0:
[TargetLowering] BuildUDIV - Add support for divide by one (PR38477) Provide a pass-through of the numerator for divide by one cases - this is the same approach we take in DAGCombiner::visitSDIVLike. I investigated whether we could achieve this by magic MULHU/SRL values but nothing appeared to work as we don't have a way for MULHU(x,c) -> x llvm-svn: 339254
2018-08-08 22:51:19 +08:00
; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm2
; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm2, %xmm2
; AVX-NEXT: vpaddw %xmm1, %xmm2, %xmm1
; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm1, %xmm2
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5],xmm1[6],xmm2[7]
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4,5,6,7]
[TargetLowering] BuildUDIV - Early out for divide by one (PR38477) We're not handling the UDIV by one special case properly - for now just early out. llvm-svn: 339229
2018-08-08 18:00:54 +08:00
; AVX-NEXT: retq
[X86] Add SSE2 and XOP udiv combine tests llvm-svn: 340282
2018-08-21 23:21:45 +08:00
;
; XOP-LABEL: pr38477:
; XOP: # %bb.0:
; XOP-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
; XOP-NEXT: vpsubw %xmm1, %xmm0, %xmm2
; XOP-NEXT: vpmulhuw {{.*}}(%rip), %xmm2, %xmm2
; XOP-NEXT: vpaddw %xmm1, %xmm2, %xmm1
; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm1, %xmm1
; XOP-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4,5,6,7]
; XOP-NEXT: retq
[TargetLowering] BuildUDIV - Add support for divide by one (PR38477) Provide a pass-through of the numerator for divide by one cases - this is the same approach we take in DAGCombiner::visitSDIVLike. I investigated whether we could achieve this by magic MULHU/SRL values but nothing appeared to work as we don't have a way for MULHU(x,c) -> x llvm-svn: 339254
2018-08-08 22:51:19 +08:00
%1 = udiv <8 x i16> %a0, <i16 1, i16 119, i16 73, i16 -111, i16 -3, i16 118, i16 32, i16 31>
ret <8 x i16> %1
[TargetLowering] BuildUDIV - Early out for divide by one (PR38477) We're not handling the UDIV by one special case properly - for now just early out. llvm-svn: 339229
2018-08-08 18:00:54 +08:00
}
[DAGCombiner][NFC] Tests for X div/rem Y single bit fold llvm-svn: 343392
2018-09-30 05:00:37 +08:00
define i1 @bool_udiv(i1 %x, i1 %y) {
; CHECK-LABEL: bool_udiv:
; CHECK: # %bb.0:
[DAGCombiner] Improve X div/rem Y fold if single bit element type Summary: Tests by @spatel, thanks Reviewers: spatel, RKSimon Reviewed By: spatel Subscribers: sdardis, atanasyan, llvm-commits, spatel Differential Revision: https://reviews.llvm.org/D52668 llvm-svn: 345575
2018-10-30 17:07:22 +08:00
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: # kill: def $al killed $al killed $eax
[DAGCombiner][NFC] Tests for X div/rem Y single bit fold llvm-svn: 343392
2018-09-30 05:00:37 +08:00
; CHECK-NEXT: retq
%r = udiv i1 %x, %y
ret i1 %r
}
define <4 x i1> @boolvec_udiv(<4 x i1> %x, <4 x i1> %y) {
[DAGCombiner] Improve X div/rem Y fold if single bit element type Summary: Tests by @spatel, thanks Reviewers: spatel, RKSimon Reviewed By: spatel Subscribers: sdardis, atanasyan, llvm-commits, spatel Differential Revision: https://reviews.llvm.org/D52668 llvm-svn: 345575
2018-10-30 17:07:22 +08:00
; CHECK-LABEL: boolvec_udiv:
; CHECK: # %bb.0:
; CHECK-NEXT: retq
[DAGCombiner][NFC] Tests for X div/rem Y single bit fold llvm-svn: 343392
2018-09-30 05:00:37 +08:00
%r = udiv <4 x i1> %x, %y
ret <4 x i1> %r
}