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llvm-project/llvm/test/CodeGen/X86/clzero-schedule.ll

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[X86] Add CLZERO schedule test llvm-svn: 320382
2017-12-11 23:53:12 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 -mattr=+clzero | FileCheck %s --check-prefix=GENERIC
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=znver1 | FileCheck %s --check-prefix=ZNVER1
define void @test_clzero(i8* %p) {
; GENERIC-LABEL: test_clzero:
; GENERIC: # %bb.0:
; GENERIC-NEXT: leaq (%rdi), %rax # sched: [1:0.50]
; GENERIC-NEXT: clzero # sched: [100:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; ZNVER1-LABEL: test_clzero:
; ZNVER1: # %bb.0:
; ZNVER1-NEXT: leaq (%rdi), %rax # sched: [1:0.25]
[CodeGen] assume max/default throughput for unspecified instructions This is a fix for the problem arising in D47374 (PR37678): https://bugs.llvm.org/show_bug.cgi?id=37678 We may not have throughput info because it's not specified in the model or it's not available with variant scheduling, so assume that those instructions can execute/complete at max-issue-width. Differential Revision: https://reviews.llvm.org/D47723 llvm-svn: 334055
2018-06-06 07:34:45 +08:00
; ZNVER1-NEXT: clzero # sched: [100:0.25]
[X86] Add CLZERO schedule test llvm-svn: 320382
2017-12-11 23:53:12 +08:00
; ZNVER1-NEXT: retq # sched: [1:0.50]
tail call void @llvm.x86.clzero(i8* %p)
ret void
}
declare void @llvm.x86.clzero(i8*)