llvm-project/llvm/test/CodeGen/X86/2011-12-26-extractelement-d...

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-unknown -mattr=-sse4.2,+sse4.1 < %s | FileCheck %s

; Make sure we don't load from the location pointed to by %p
; twice: it has non-obvious performance implications, and
; the relevant transformation doesn't know how to update
; the chains correctly.
; PR10747

define <4 x i32> @test(<4 x i32>* %p) {
; CHECK-LABEL: test:
; CHECK:       # BB#0:
; CHECK-NEXT:    movdqa (%rdi), %xmm0
; CHECK-NEXT:    pextrd $2, %xmm0, %eax
; CHECK-NEXT:    cmpl $3, %eax
; CHECK-NEXT:    je .LBB0_2
; CHECK-NEXT:  # BB#1:
; CHECK-NEXT:    pxor %xmm0, %xmm0
; CHECK-NEXT:  .LBB0_2:
; CHECK-NEXT:    retq
  %v = load <4 x i32>, <4 x i32>* %p
  %e = extractelement <4 x i32> %v, i32 2
  %cmp = icmp eq i32 %e, 3
  %sel = select i1 %cmp, <4 x i32> %v, <4 x i32> zeroinitializer
  ret <4 x i32> %sel
}
[X86][SSE] Regenerate test. llvm-svn: 288906 2016-12-07 21:05:04 +08:00			`; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py`
			`; RUN: llc -mtriple=x86_64-unknown -mattr=-sse4.2,+sse4.1 < %s \| FileCheck %s`

Make sure DAGCombiner doesn't introduce multiple loads from the same memory location. PR10747, part 2. llvm-svn: 147283 2011-12-27 06:49:32 +08:00			`; Make sure we don't load from the location pointed to by %p`
			`; twice: it has non-obvious performance implications, and`
			`; the relevant transformation doesn't know how to update`
			`; the chains correctly.`
			`; PR10747`

			`define <4 x i32> @test(<4 x i32>* %p) {`
[X86][SSE] Regenerate test. llvm-svn: 288906 2016-12-07 21:05:04 +08:00			`; CHECK-LABEL: test:`
			`; CHECK: # BB#0:`
			`; CHECK-NEXT: movdqa (%rdi), %xmm0`
			`; CHECK-NEXT: pextrd $2, %xmm0, %eax`
			`; CHECK-NEXT: cmpl $3, %eax`
			`; CHECK-NEXT: je .LBB0_2`
			`; CHECK-NEXT: # BB#1:`
			`; CHECK-NEXT: pxor %xmm0, %xmm0`
			`; CHECK-NEXT: .LBB0_2:`
			`; CHECK-NEXT: retq`
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=\|:\|^)\sload (?:atomic )?(?:volatile )?(.?))(\| addrspace\(\d+\) )\($\| (?:%\|@\|null\|undef\|blockaddress\|getelementptr\|addrspacecast\|bitcast\|inttoptr\|\[\[[a-zA-Z]\|\{\{).$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794 2015-02-28 05:17:42 +08:00			`%v = load <4 x i32>, <4 x i32>* %p`
Make sure DAGCombiner doesn't introduce multiple loads from the same memory location. PR10747, part 2. llvm-svn: 147283 2011-12-27 06:49:32 +08:00			`%e = extractelement <4 x i32> %v, i32 2`
			`%cmp = icmp eq i32 %e, 3`
			`%sel = select i1 %cmp, <4 x i32> %v, <4 x i32> zeroinitializer`
			`ret <4 x i32> %sel`
			`}`