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llvm-project/llvm/test/CodeGen/Mips/Fast-ISel/rem1.ll

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[mips][FastISel] Implement srem/urem and sdiv/udiv instructions. Summary: Implement the LLVM assembly urem/srem and sdiv/udiv instructions in MIPS FastISel. Based on a patch by Reed Kotler. Test Plan: srem1.ll div1.ll test-suite at O0/O2 for mips32 r1/r2 Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D7028 llvm-svn: 238757
2015-06-02 00:17:37 +08:00
; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
Re-commit: [mips][fastisel] Handle 0-4 arguments without SelectionDAG. Summary: Implements fastLowerArguments() to avoid the need to fall back on SelectionDAG for 0-4 argument functions that don't do tricky things like passing double in a pair of i32's. This allows us to move all except one test to -fast-isel-abort=3. The remaining one has function prototypes of the form 'i32 (i32, double, double)' which requires floats to be passed in GPR's. The previous commit had an uninitialized variable that caused the incoming argument region to have undefined size. This has been fixed. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: https://reviews.llvm.org/D22680 llvm-svn: 277136
2016-07-29 20:27:28 +08:00
; RUN: -fast-isel-abort=3 | FileCheck %s
[mips][FastISel] Implement srem/urem and sdiv/udiv instructions. Summary: Implement the LLVM assembly urem/srem and sdiv/udiv instructions in MIPS FastISel. Based on a patch by Reed Kotler. Test Plan: srem1.ll div1.ll test-suite at O0/O2 for mips32 r1/r2 Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D7028 llvm-svn: 238757
2015-06-02 00:17:37 +08:00
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
Re-commit: [mips][fastisel] Handle 0-4 arguments without SelectionDAG. Summary: Implements fastLowerArguments() to avoid the need to fall back on SelectionDAG for 0-4 argument functions that don't do tricky things like passing double in a pair of i32's. This allows us to move all except one test to -fast-isel-abort=3. The remaining one has function prototypes of the form 'i32 (i32, double, double)' which requires floats to be passed in GPR's. The previous commit had an uninitialized variable that caused the incoming argument region to have undefined size. This has been fixed. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: https://reviews.llvm.org/D22680 llvm-svn: 277136
2016-07-29 20:27:28 +08:00
; RUN: -fast-isel-abort=3 | FileCheck %s
[mips][FastISel] Implement srem/urem and sdiv/udiv instructions. Summary: Implement the LLVM assembly urem/srem and sdiv/udiv instructions in MIPS FastISel. Based on a patch by Reed Kotler. Test Plan: srem1.ll div1.ll test-suite at O0/O2 for mips32 r1/r2 Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D7028 llvm-svn: 238757
2015-06-02 00:17:37 +08:00
@sj = global i32 200, align 4
@sk = global i32 -47, align 4
@uj = global i32 200, align 4
@uk = global i32 43, align 4
@si = common global i32 0, align 4
@ui = common global i32 0, align 4
define void @rems() {
; CHECK-LABEL: rems:
; CHECK: lui $[[GOT1:[0-9]+]], %hi(_gp_disp)
; CHECK: addiu $[[GOT2:[0-9]+]], $[[GOT1]], %lo(_gp_disp)
; CHECK: addu $[[GOT:[0-9]+]], $[[GOT2:[0-9]+]], $25
; CHECK-DAG: lw $[[I_ADDR:[0-9]+]], %got(si)($[[GOT]])
; CHECK-DAG: lw $[[K_ADDR:[0-9]+]], %got(sk)($[[GOT]])
; CHECK-DAG: lw $[[J_ADDR:[0-9]+]], %got(sj)($[[GOT]])
; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]])
; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]])
; CHECK-DAG: div $zero, $[[J]], $[[K]]
fix CHECK_DAG -> CHECK-DAG llvm-svn: 264673
2016-03-29 06:00:38 +08:00
; CHECK-DAG: teq $[[K]], $zero, 7
[mips][FastISel] Implement srem/urem and sdiv/udiv instructions. Summary: Implement the LLVM assembly urem/srem and sdiv/udiv instructions in MIPS FastISel. Based on a patch by Reed Kotler. Test Plan: srem1.ll div1.ll test-suite at O0/O2 for mips32 r1/r2 Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D7028 llvm-svn: 238757
2015-06-02 00:17:37 +08:00
; CHECK-DAG: mfhi $[[RESULT:[0-9]+]]
; CHECK: sw $[[RESULT]], 0($[[I_ADDR]])
%1 = load i32, i32* @sj, align 4
%2 = load i32, i32* @sk, align 4
%rem = srem i32 %1, %2
store i32 %rem, i32* @si, align 4
ret void
}
; Function Attrs: noinline nounwind
define void @remu() {
; CHECK-LABEL: remu:
; CHECK: lui $[[GOT1:[0-9]+]], %hi(_gp_disp)
; CHECK: addiu $[[GOT2:[0-9]+]], $[[GOT1]], %lo(_gp_disp)
; CHECK: addu $[[GOT:[0-9]+]], $[[GOT2:[0-9]+]], $25
; CHECK-DAG: lw $[[I_ADDR:[0-9]+]], %got(ui)($[[GOT]])
; CHECK-DAG: lw $[[K_ADDR:[0-9]+]], %got(uk)($[[GOT]])
; CHECK-DAG: lw $[[J_ADDR:[0-9]+]], %got(uj)($[[GOT]])
; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]])
; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]])
; CHECK-DAG: divu $zero, $[[J]], $[[K]]
fix CHECK_DAG -> CHECK-DAG llvm-svn: 264673
2016-03-29 06:00:38 +08:00
; CHECK-DAG: teq $[[K]], $zero, 7
[mips][FastISel] Implement srem/urem and sdiv/udiv instructions. Summary: Implement the LLVM assembly urem/srem and sdiv/udiv instructions in MIPS FastISel. Based on a patch by Reed Kotler. Test Plan: srem1.ll div1.ll test-suite at O0/O2 for mips32 r1/r2 Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D7028 llvm-svn: 238757
2015-06-02 00:17:37 +08:00
; CHECK-DAG: mfhi $[[RESULT:[0-9]+]]
; CHECK: sw $[[RESULT]], 0($[[I_ADDR]])
%1 = load i32, i32* @uj, align 4
%2 = load i32, i32* @uk, align 4
%rem = urem i32 %1, %2
store i32 %rem, i32* @ui, align 4
ret void
}