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llvm-project/llvm/test/CodeGen/X86/2007-01-08-InstrSched.ll

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Add PR number for future reference llvm-svn: 33031
2007-01-09 08:31:52 +08:00
; PR1075
Instruction scheduling itinerary for Intel Atom. Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558
2012-02-02 07:20:51 +08:00
; RUN: llc < %s -mcpu=generic -mtriple=x86_64-apple-darwin -O3 | FileCheck %s
Added a test case from PR1075. llvm-svn: 33028
2007-01-09 07:58:27 +08:00
eliminate some uses of prcontext. Any help here would be appreciated :) llvm-svn: 80520
2009-08-31 05:45:23 +08:00
define float @foo(float %x) nounwind {
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
2009-06-05 06:49:04 +08:00
%tmp1 = fmul float %x, 3.000000e+00
%tmp3 = fmul float %x, 5.000000e+00
%tmp5 = fmul float %x, 7.000000e+00
%tmp7 = fmul float %x, 1.100000e+01
%tmp10 = fadd float %tmp1, %tmp3
%tmp12 = fadd float %tmp10, %tmp5
%tmp14 = fadd float %tmp12, %tmp7
Added a test case from PR1075. llvm-svn: 33028
2007-01-09 07:58:27 +08:00
ret float %tmp14
eliminate some uses of prcontext. Any help here would be appreciated :) llvm-svn: 80520
2009-08-31 05:45:23 +08:00
Revert "Temporarily enable MI-Sched on X86." This reverts commit 98a9b72e8c56dc13a2617de84503a3d78352789c. llvm-svn: 184823
2013-06-25 10:48:58 +08:00
; CHECK: mulss
; CHECK: mulss
Add LiveRangeShrink pass to shrink live range within BB. Summary: LiveRangeShrink pass moves instruction right after the definition with the same BB if the instruction and its operands all have more than one use. This pass is inexpensive and guarantees optimal live-range within BB. Reviewers: davidxl, wmi, hfinkel, MatzeB, andreadb Reviewed By: MatzeB, andreadb Subscribers: hiraditya, jyknight, sanjoy, skatkov, gberry, jholewinski, qcolombet, javed.absar, krytarowski, atrick, spatel, RKSimon, andreadb, MatzeB, mehdi_amini, mgorny, efriedma, davide, dberlin, llvm-commits Differential Revision: https://reviews.llvm.org/D32563 llvm-svn: 302938
2017-05-13 03:29:27 +08:00
; CHECK: mulss
; CHECK: mulss
Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
2013-10-16 07:33:07 +08:00
; CHECK: addss
Revert r302938 "Add LiveRangeShrink pass to shrink live range within BB." This also reverts follow-ups r303292 and r303298. It broke some Chromium tests under MSan, and apparently also internal tests at Google. llvm-svn: 303369
2017-05-19 02:50:05 +08:00
; CHECK: addss
; CHECK: addss
Turning off post-ra scheduling for x86. It isn't a consistent win. llvm-svn: 98810
2010-03-18 14:55:42 +08:00
; CHECK: ret
Added a test case from PR1075. llvm-svn: 33028
2007-01-09 07:58:27 +08:00
}