2021-03-20 10:27:52 +08:00
|
|
|
# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -start-before si-shrink-instructions -stop-before si-late-branch-lowering -o - %s | FileCheck -check-prefix=GCN %s
|
2017-06-21 04:33:44 +08:00
|
|
|
|
|
|
|
# GCN-LABEL: name: subbrev{{$}}
|
2018-02-24 09:32:32 +08:00
|
|
|
# GCN: V_SUBBREV_U32_e32 0, undef $vgpr0, implicit-def $vcc, implicit killed $vcc, implicit $exec
|
2017-06-21 04:33:44 +08:00
|
|
|
|
|
|
|
---
|
|
|
|
name: subbrev
|
|
|
|
tracksRegLiveness: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: vgpr_32 }
|
|
|
|
- { id: 1, class: vgpr_32 }
|
|
|
|
- { id: 2, class: vgpr_32 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 3, class: sreg_64_xexec }
|
2017-06-21 04:33:44 +08:00
|
|
|
- { id: 4, class: vgpr_32 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 5, class: sreg_64_xexec }
|
2017-06-21 04:33:44 +08:00
|
|
|
body: |
|
|
|
|
bb.0:
|
|
|
|
|
|
|
|
%0 = IMPLICIT_DEF
|
|
|
|
%1 = IMPLICIT_DEF
|
|
|
|
%2 = IMPLICIT_DEF
|
2018-02-01 06:04:26 +08:00
|
|
|
%3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec
|
2019-03-19 03:35:44 +08:00
|
|
|
%4, %5 = V_SUBBREV_U32_e64 0, %0, %3, 0, implicit $exec
|
2021-02-09 08:36:10 +08:00
|
|
|
GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, implicit $exec
|
2017-06-21 04:33:44 +08:00
|
|
|
|
|
|
|
...
|
|
|
|
|
|
|
|
# GCN-LABEL: name: subb{{$}}
|
2018-02-24 09:32:32 +08:00
|
|
|
# GCN: V_SUBBREV_U32_e32 0, undef $vgpr0, implicit-def $vcc, implicit killed $vcc, implicit $exec
|
2017-06-21 04:33:44 +08:00
|
|
|
|
|
|
|
---
|
|
|
|
name: subb
|
|
|
|
tracksRegLiveness: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: vgpr_32 }
|
|
|
|
- { id: 1, class: vgpr_32 }
|
|
|
|
- { id: 2, class: vgpr_32 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 3, class: sreg_64_xexec }
|
2017-06-21 04:33:44 +08:00
|
|
|
- { id: 4, class: vgpr_32 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 5, class: sreg_64_xexec }
|
2017-06-21 04:33:44 +08:00
|
|
|
body: |
|
|
|
|
bb.0:
|
|
|
|
|
|
|
|
%0 = IMPLICIT_DEF
|
|
|
|
%1 = IMPLICIT_DEF
|
|
|
|
%2 = IMPLICIT_DEF
|
2018-02-01 06:04:26 +08:00
|
|
|
%3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec
|
2019-03-19 03:35:44 +08:00
|
|
|
%4, %5 = V_SUBB_U32_e64 %0, 0, %3, 0, implicit $exec
|
2021-02-09 08:36:10 +08:00
|
|
|
GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, implicit $exec
|
2017-06-21 04:33:44 +08:00
|
|
|
|
|
|
|
...
|
|
|
|
|
|
|
|
# GCN-LABEL: name: addc{{$}}
|
2018-02-01 06:04:26 +08:00
|
|
|
# GCN: V_ADDC_U32_e32 0, undef $vgpr0, implicit-def $vcc, implicit killed $vcc, implicit $exec
|
2017-06-21 04:33:44 +08:00
|
|
|
|
|
|
|
---
|
|
|
|
name: addc
|
|
|
|
tracksRegLiveness: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: vgpr_32 }
|
|
|
|
- { id: 1, class: vgpr_32 }
|
|
|
|
- { id: 2, class: vgpr_32 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 3, class: sreg_64_xexec }
|
2017-06-21 04:33:44 +08:00
|
|
|
- { id: 4, class: vgpr_32 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 5, class: sreg_64_xexec }
|
2017-06-21 04:33:44 +08:00
|
|
|
body: |
|
|
|
|
bb.0:
|
|
|
|
|
|
|
|
%0 = IMPLICIT_DEF
|
|
|
|
%1 = IMPLICIT_DEF
|
|
|
|
%2 = IMPLICIT_DEF
|
2018-02-01 06:04:26 +08:00
|
|
|
%3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec
|
2019-03-19 03:35:44 +08:00
|
|
|
%4, %5 = V_ADDC_U32_e64 0, %0, %3, 0, implicit $exec
|
2021-02-09 08:36:10 +08:00
|
|
|
GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, implicit $exec
|
2017-06-21 04:33:44 +08:00
|
|
|
|
|
|
|
...
|
|
|
|
|
|
|
|
# GCN-LABEL: name: addc2{{$}}
|
2018-02-01 06:04:26 +08:00
|
|
|
# GCN: V_ADDC_U32_e32 0, undef $vgpr0, implicit-def $vcc, implicit killed $vcc, implicit $exec
|
2017-06-21 04:33:44 +08:00
|
|
|
|
|
|
|
---
|
|
|
|
name: addc2
|
|
|
|
tracksRegLiveness: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: vgpr_32 }
|
|
|
|
- { id: 1, class: vgpr_32 }
|
|
|
|
- { id: 2, class: vgpr_32 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 3, class: sreg_64_xexec }
|
2017-06-21 04:33:44 +08:00
|
|
|
- { id: 4, class: vgpr_32 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 5, class: sreg_64_xexec }
|
2017-06-21 04:33:44 +08:00
|
|
|
body: |
|
|
|
|
bb.0:
|
|
|
|
|
|
|
|
%0 = IMPLICIT_DEF
|
|
|
|
%1 = IMPLICIT_DEF
|
|
|
|
%2 = IMPLICIT_DEF
|
2018-02-01 06:04:26 +08:00
|
|
|
%3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec
|
2019-03-19 03:35:44 +08:00
|
|
|
%4, %5 = V_ADDC_U32_e64 %0, 0, %3, 0, implicit $exec
|
2021-02-09 08:36:10 +08:00
|
|
|
GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, implicit $exec
|
2017-06-21 04:33:44 +08:00
|
|
|
|
|
|
|
...
|