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llvm-project/llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir

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AMDGPU: Fix verifier error on spilling partially defined SGPRs This needs an implicit def of the super-register in case one of the lanes isn't defined, similar to copyPhysReg (or the not-VGPR spill case below). This showed up in GlobalISel testing since it currently doesn't fold out many undef instructions.
2020-07-24 09:11:04 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck %s
#
# Check for liveness errors when spilling partially defined super registers.
---
name: sgpr_spill_s64_undef_high32
tracksRegLiveness: true
machineFunctionInfo:
isEntryFunction: true
hasSpilledSGPRs: true
scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
stackPtrOffsetReg: '$sgpr32'
stack:
- { id: 0, type: spill-slot, size: 8, alignment: 4, stack-id: sgpr-spill }
body: |
bb.0:
liveins: $sgpr4
; CHECK-LABEL: name: sgpr_spill_s64_undef_high32
; CHECK: liveins: $sgpr4, $vgpr0
AMDGPU: Remove SGPRSpillVGPRDefinedSet hack These VGPRs should be reserved and therefore do not need "correct" liveness. They should not have undef uses, which can still cause issues.
2020-10-16 06:40:02 +08:00
; CHECK: $vgpr0 = V_WRITELANE_B32 $sgpr4, 0, $vgpr0, implicit-def $sgpr4_sgpr5, implicit $sgpr4_sgpr5
[AMDGPU] Use pseudo instructions for readlane/writelane This reverts r227987 "R600/SI: Determine target-specific encoding of READLANE and WRITELANE early v2". All the codegen changes are caused by the post-RA scheduler no longer treating readlane/writelane as scheduling barriers due to having unmodelled side effects. (The pseudos are hasSideEffects = 0, but the real instructions are hasSideEffects = ? which TableGen conservatively treats as 1.) Differential Revision: https://reviews.llvm.org/D90401
2020-10-29 20:10:56 +08:00
; CHECK: $vgpr0 = V_WRITELANE_B32 $sgpr5, 1, $vgpr0, implicit $sgpr4_sgpr5
AMDGPU: Fix verifier error on spilling partially defined SGPRs This needs an implicit def of the super-register in case one of the lanes isn't defined, similar to copyPhysReg (or the not-VGPR spill case below). This showed up in GlobalISel testing since it currently doesn't fold out many undef instructions.
2020-07-24 09:11:04 +08:00
SI_SPILL_S64_SAVE renamable $sgpr4_sgpr5, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store 8 into %stack.0, align 4, addrspace 5)
...
---
name: sgpr_spill_s64_undef_low32
tracksRegLiveness: true
machineFunctionInfo:
isEntryFunction: true
hasSpilledSGPRs: true
scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
stackPtrOffsetReg: '$sgpr32'
stack:
- { id: 0, type: spill-slot, size: 8, alignment: 4, stack-id: sgpr-spill }
body: |
bb.0:
liveins: $sgpr5
; CHECK-LABEL: name: sgpr_spill_s64_undef_low32
; CHECK: liveins: $sgpr5, $vgpr0
AMDGPU: Remove SGPRSpillVGPRDefinedSet hack These VGPRs should be reserved and therefore do not need "correct" liveness. They should not have undef uses, which can still cause issues.
2020-10-16 06:40:02 +08:00
; CHECK: $vgpr0 = V_WRITELANE_B32 $sgpr4, 0, $vgpr0, implicit-def $sgpr4_sgpr5, implicit $sgpr4_sgpr5
[AMDGPU] Use pseudo instructions for readlane/writelane This reverts r227987 "R600/SI: Determine target-specific encoding of READLANE and WRITELANE early v2". All the codegen changes are caused by the post-RA scheduler no longer treating readlane/writelane as scheduling barriers due to having unmodelled side effects. (The pseudos are hasSideEffects = 0, but the real instructions are hasSideEffects = ? which TableGen conservatively treats as 1.) Differential Revision: https://reviews.llvm.org/D90401
2020-10-29 20:10:56 +08:00
; CHECK: $vgpr0 = V_WRITELANE_B32 $sgpr5, 1, $vgpr0, implicit $sgpr4_sgpr5
AMDGPU: Fix verifier error on spilling partially defined SGPRs This needs an implicit def of the super-register in case one of the lanes isn't defined, similar to copyPhysReg (or the not-VGPR spill case below). This showed up in GlobalISel testing since it currently doesn't fold out many undef instructions.
2020-07-24 09:11:04 +08:00
SI_SPILL_S64_SAVE renamable $sgpr4_sgpr5, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store 8 into %stack.0, align 4, addrspace 5)
...