2021-01-07 02:34:21 +08:00
|
|
|
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,SI,FUNC %s
|
|
|
|
|
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GFX89,FUNC %s
|
|
|
|
|
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GFX9,GFX89,FUNC %s
|
|
|
|
|
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600-- -mcpu=cypress < %s | FileCheck -enable-var-scope --check-prefixes=EG,FUNC %s
|
2014-03-18 02:58:11 +08:00
|
|
|
|
2017-01-12 06:35:22 +08:00
|
|
|
; FIXME: i16 promotion pass ruins the scalar cases when legal.
|
2017-02-28 06:15:25 +08:00
|
|
|
; FIXME: r600 fails verifier
|
2017-01-12 06:35:22 +08:00
|
|
|
|
2014-10-02 01:15:17 +08:00
|
|
|
; FUNC-LABEL: {{^}}sext_in_reg_i1_i32:
|
2016-12-10 05:10:41 +08:00
|
|
|
; GCN: s_load_dword [[ARG:s[0-9]+]],
|
|
|
|
|
; GCN: s_bfe_i32 [[SEXTRACT:s[0-9]+]], [[ARG]], 0x10000
|
|
|
|
|
; GCN: v_mov_b32_e32 [[EXTRACT:v[0-9]+]], [[SEXTRACT]]
|
|
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|
|
; GCN: buffer_store_dword [[EXTRACT]],
|
2014-03-18 02:58:11 +08:00
|
|
|
|
2014-04-16 09:41:34 +08:00
|
|
|
; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
|
2015-12-04 09:51:19 +08:00
|
|
|
; EG: LSHR * [[ADDR]]
|
|
|
|
|
; EG: BFE_INT * [[RES]], {{.*}}, 0.0, 1
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @sext_in_reg_i1_i32(i32 addrspace(1)* %out, i32 %in) #0 {
|
2014-03-18 02:58:11 +08:00
|
|
|
%shl = shl i32 %in, 31
|
|
|
|
|
%sext = ashr i32 %shl, 31
|
|
|
|
|
store i32 %sext, i32 addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-02 01:15:17 +08:00
|
|
|
; FUNC-LABEL: {{^}}sext_in_reg_i8_to_i32:
|
2016-12-10 05:10:41 +08:00
|
|
|
; GCN: s_add_i32 [[VAL:s[0-9]+]],
|
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|
|
; GCN: s_sext_i32_i8 [[EXTRACT:s[0-9]+]], [[VAL]]
|
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|
; GCN: v_mov_b32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]]
|
|
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|
|
; GCN: buffer_store_dword [[VEXTRACT]],
|
2014-03-18 02:58:11 +08:00
|
|
|
|
2014-04-16 09:41:34 +08:00
|
|
|
; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
|
|
|
|
|
; EG: ADD_INT
|
|
|
|
|
; EG-NEXT: BFE_INT [[RES]], {{.*}}, 0.0, literal
|
|
|
|
|
; EG-NEXT: LSHR * [[ADDR]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @sext_in_reg_i8_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
|
2014-03-18 02:58:11 +08:00
|
|
|
%c = add i32 %a, %b ; add to prevent folding into extload
|
|
|
|
|
%shl = shl i32 %c, 24
|
|
|
|
|
%ashr = ashr i32 %shl, 24
|
|
|
|
|
store i32 %ashr, i32 addrspace(1)* %out, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-02 01:15:17 +08:00
|
|
|
; FUNC-LABEL: {{^}}sext_in_reg_i16_to_i32:
|
2016-12-10 05:10:41 +08:00
|
|
|
; GCN: s_add_i32 [[VAL:s[0-9]+]],
|
|
|
|
|
; GCN: s_sext_i32_i16 [[EXTRACT:s[0-9]+]], [[VAL]]
|
|
|
|
|
; GCN: v_mov_b32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]]
|
|
|
|
|
; GCN: buffer_store_dword [[VEXTRACT]],
|
2014-03-18 02:58:11 +08:00
|
|
|
|
2014-04-16 09:41:34 +08:00
|
|
|
; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
|
|
|
|
|
; EG: ADD_INT
|
|
|
|
|
; EG-NEXT: BFE_INT [[RES]], {{.*}}, 0.0, literal
|
|
|
|
|
; EG-NEXT: LSHR * [[ADDR]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @sext_in_reg_i16_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
|
2014-03-18 02:58:11 +08:00
|
|
|
%c = add i32 %a, %b ; add to prevent folding into extload
|
|
|
|
|
%shl = shl i32 %c, 16
|
|
|
|
|
%ashr = ashr i32 %shl, 16
|
|
|
|
|
store i32 %ashr, i32 addrspace(1)* %out, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-02 01:15:17 +08:00
|
|
|
; FUNC-LABEL: {{^}}sext_in_reg_i8_to_v1i32:
|
2016-12-10 05:10:41 +08:00
|
|
|
; GCN: s_add_i32 [[VAL:s[0-9]+]],
|
|
|
|
|
; GCN: s_sext_i32_i8 [[EXTRACT:s[0-9]+]], [[VAL]]
|
|
|
|
|
; GCN: v_mov_b32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]]
|
|
|
|
|
; GCN: buffer_store_dword [[VEXTRACT]],
|
2014-03-18 02:58:11 +08:00
|
|
|
|
2014-04-16 09:41:34 +08:00
|
|
|
; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
|
|
|
|
|
; EG: ADD_INT
|
|
|
|
|
; EG-NEXT: BFE_INT [[RES]], {{.*}}, 0.0, literal
|
|
|
|
|
; EG-NEXT: LSHR * [[ADDR]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @sext_in_reg_i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i32> %a, <1 x i32> %b) #0 {
|
2014-03-18 02:58:11 +08:00
|
|
|
%c = add <1 x i32> %a, %b ; add to prevent folding into extload
|
|
|
|
|
%shl = shl <1 x i32> %c, <i32 24>
|
|
|
|
|
%ashr = ashr <1 x i32> %shl, <i32 24>
|
|
|
|
|
store <1 x i32> %ashr, <1 x i32> addrspace(1)* %out, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-02 01:15:17 +08:00
|
|
|
; FUNC-LABEL: {{^}}sext_in_reg_i1_to_i64:
|
2016-12-10 05:10:41 +08:00
|
|
|
; GCN: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]]
|
|
|
|
|
; GCN-DAG: s_bfe_i64 s{{\[}}[[SLO:[0-9]+]]:[[SHI:[0-9]+]]{{\]}}, [[VAL]], 0x10000
|
|
|
|
|
; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SLO]]
|
|
|
|
|
; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]]
|
|
|
|
|
; GCN: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}}
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @sext_in_reg_i1_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) #0 {
|
2014-11-15 02:18:16 +08:00
|
|
|
%c = shl i64 %a, %b
|
2014-04-22 11:49:30 +08:00
|
|
|
%shl = shl i64 %c, 63
|
|
|
|
|
%ashr = ashr i64 %shl, 63
|
|
|
|
|
store i64 %ashr, i64 addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-02 01:15:17 +08:00
|
|
|
; FUNC-LABEL: {{^}}sext_in_reg_i8_to_i64:
|
2016-12-10 05:10:41 +08:00
|
|
|
; GCN: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]]
|
|
|
|
|
; GCN-DAG: s_bfe_i64 s{{\[}}[[SLO:[0-9]+]]:[[SHI:[0-9]+]]{{\]}}, [[VAL]], 0x80000
|
|
|
|
|
; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SLO]]
|
|
|
|
|
; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]]
|
|
|
|
|
; GCN: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}}
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @sext_in_reg_i8_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) #0 {
|
2014-11-15 02:18:16 +08:00
|
|
|
%c = shl i64 %a, %b
|
2014-03-18 02:58:11 +08:00
|
|
|
%shl = shl i64 %c, 56
|
|
|
|
|
%ashr = ashr i64 %shl, 56
|
|
|
|
|
store i64 %ashr, i64 addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-02 01:15:17 +08:00
|
|
|
; FUNC-LABEL: {{^}}sext_in_reg_i16_to_i64:
|
2016-12-10 05:10:41 +08:00
|
|
|
; GCN: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]]
|
|
|
|
|
; GCN-DAG: s_bfe_i64 s{{\[}}[[SLO:[0-9]+]]:[[SHI:[0-9]+]]{{\]}}, [[VAL]], 0x100000
|
|
|
|
|
; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SLO]]
|
|
|
|
|
; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]]
|
|
|
|
|
; GCN: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}}
|
2014-03-18 02:58:11 +08:00
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @sext_in_reg_i16_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) #0 {
|
2014-11-15 02:18:16 +08:00
|
|
|
%c = shl i64 %a, %b
|
2014-03-18 02:58:11 +08:00
|
|
|
%shl = shl i64 %c, 48
|
|
|
|
|
%ashr = ashr i64 %shl, 48
|
|
|
|
|
store i64 %ashr, i64 addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-02 01:15:17 +08:00
|
|
|
; FUNC-LABEL: {{^}}sext_in_reg_i32_to_i64:
|
2016-12-10 05:10:41 +08:00
|
|
|
; GCN: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]]
|
|
|
|
|
; GCN-DAG: s_bfe_i64 s{{\[}}[[SLO:[0-9]+]]:[[SHI:[0-9]+]]{{\]}}, [[VAL]], 0x200000
|
|
|
|
|
; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SLO]]
|
|
|
|
|
; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]]
|
|
|
|
|
; GCN: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}}
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @sext_in_reg_i32_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) #0 {
|
2014-11-15 02:18:16 +08:00
|
|
|
%c = shl i64 %a, %b
|
2014-03-27 02:31:06 +08:00
|
|
|
%shl = shl i64 %c, 32
|
|
|
|
|
%ashr = ashr i64 %shl, 32
|
|
|
|
|
store i64 %ashr, i64 addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2014-03-18 02:58:11 +08:00
|
|
|
; This is broken on Evergreen for some reason related to the <1 x i64> kernel arguments.
|
2014-10-02 01:15:17 +08:00
|
|
|
; XFUNC-LABEL: {{^}}sext_in_reg_i8_to_v1i64:
|
2016-12-10 05:10:41 +08:00
|
|
|
; XGCN: s_bfe_i32 [[EXTRACT:s[0-9]+]], {{s[0-9]+}}, 524288
|
|
|
|
|
; XGCN: s_ashr_i32 {{v[0-9]+}}, [[EXTRACT]], 31
|
|
|
|
|
; XGCN: buffer_store_dword
|
2014-03-18 02:58:11 +08:00
|
|
|
; XEG: BFE_INT
|
|
|
|
|
; XEG: ASHR
|
2017-03-22 05:39:51 +08:00
|
|
|
; define amdgpu_kernel void @sext_in_reg_i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i64> %a, <1 x i64> %b) #0 {
|
2014-03-18 02:58:11 +08:00
|
|
|
; %c = add <1 x i64> %a, %b
|
|
|
|
|
; %shl = shl <1 x i64> %c, <i64 56>
|
|
|
|
|
; %ashr = ashr <1 x i64> %shl, <i64 56>
|
|
|
|
|
; store <1 x i64> %ashr, <1 x i64> addrspace(1)* %out, align 8
|
|
|
|
|
; ret void
|
|
|
|
|
; }
|
|
|
|
|
|
2014-11-15 02:18:16 +08:00
|
|
|
; FUNC-LABEL: {{^}}v_sext_in_reg_i1_to_i64:
|
|
|
|
|
; SI: buffer_load_dwordx2
|
|
|
|
|
; SI: v_lshl_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}
|
2016-12-10 05:10:41 +08:00
|
|
|
|
2017-07-29 09:03:53 +08:00
|
|
|
; GFX89: {{flat|global}}_load_dwordx2
|
2017-02-28 06:15:25 +08:00
|
|
|
; GFX89: v_lshlrev_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}
|
2016-12-10 05:10:41 +08:00
|
|
|
|
|
|
|
|
; GCN: v_bfe_i32 v[[LO:[0-9]+]], v[[VAL_LO]], 0, 1
|
|
|
|
|
; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
|
|
|
|
|
|
2014-11-15 02:18:16 +08:00
|
|
|
; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX89: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[HI]]{{\]}}
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @v_sext_in_reg_i1_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) #0 {
|
2020-02-10 05:38:56 +08:00
|
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
[opaque pointer type] Add textual IR support for explicit type parameter to getelementptr instruction
One of several parallel first steps to remove the target type of pointers,
replacing them with a single opaque pointer type.
This adds an explicit type parameter to the gep instruction so that when the
first parameter becomes an opaque pointer type, the type to gep through is
still available to the instructions.
* This doesn't modify gep operators, only instructions (operators will be
handled separately)
* Textual IR changes only. Bitcode (including upgrade) and changing the
in-memory representation will be in separate changes.
* geps of vectors are transformed as:
getelementptr <4 x float*> %x, ...
->getelementptr float, <4 x float*> %x, ...
Then, once the opaque pointer type is introduced, this will ultimately look
like:
getelementptr float, <4 x ptr> %x
with the unambiguous interpretation that it is a vector of pointers to float.
* address spaces remain on the pointer, not the type:
getelementptr float addrspace(1)* %x
->getelementptr float, float addrspace(1)* %x
Then, eventually:
getelementptr float, ptr addrspace(1) %x
Importantly, the massive amount of test case churn has been automated by
same crappy python code. I had to manually update a few test cases that
wouldn't fit the script's model (r228970,r229196,r229197,r229198). The
python script just massages stdin and writes the result to stdout, I
then wrapped that in a shell script to handle replacing files, then
using the usual find+xargs to migrate all the files.
update.py:
import fileinput
import sys
import re
ibrep = re.compile(r"(^.*?[^%\w]getelementptr inbounds )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
normrep = re.compile( r"(^.*?[^%\w]getelementptr )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
def conv(match, line):
if not match:
return line
line = match.groups()[0]
if len(match.groups()[5]) == 0:
line += match.groups()[2]
line += match.groups()[3]
line += ", "
line += match.groups()[1]
line += "\n"
return line
for line in sys.stdin:
if line.find("getelementptr ") == line.find("getelementptr inbounds"):
if line.find("getelementptr inbounds") != line.find("getelementptr inbounds ("):
line = conv(re.match(ibrep, line), line)
elif line.find("getelementptr ") != line.find("getelementptr ("):
line = conv(re.match(normrep, line), line)
sys.stdout.write(line)
apply.sh:
for name in "$@"
do
python3 `dirname "$0"`/update.py < "$name" > "$name.tmp" && mv "$name.tmp" "$name"
rm -f "$name.tmp"
done
The actual commands:
From llvm/src:
find test/ -name *.ll | xargs ./apply.sh
From llvm/src/tools/clang:
find test/ -name *.mm -o -name *.m -o -name *.cpp -o -name *.c | xargs -I '{}' ../../apply.sh "{}"
From llvm/src/tools/polly:
find test/ -name *.ll | xargs ./apply.sh
After that, check-all (with llvm, clang, clang-tools-extra, lld,
compiler-rt, and polly all checked out).
The extra 'rm' in the apply.sh script is due to a few files in clang's test
suite using interesting unicode stuff that my python script was throwing
exceptions on. None of those files needed to be migrated, so it seemed
sufficient to ignore those cases.
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7636
llvm-svn: 230786
2015-02-28 03:29:02 +08:00
|
|
|
%a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
|
2015-02-28 05:17:42 +08:00
|
|
|
%a = load i64, i64 addrspace(1)* %a.gep, align 8
|
|
|
|
|
%b = load i64, i64 addrspace(1)* %b.gep, align 8
|
2014-11-15 02:18:16 +08:00
|
|
|
|
|
|
|
|
%c = shl i64 %a, %b
|
|
|
|
|
%shl = shl i64 %c, 63
|
|
|
|
|
%ashr = ashr i64 %shl, 63
|
|
|
|
|
store i64 %ashr, i64 addrspace(1)* %out.gep, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}v_sext_in_reg_i8_to_i64:
|
|
|
|
|
; SI: buffer_load_dwordx2
|
|
|
|
|
; SI: v_lshl_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}
|
2016-12-10 05:10:41 +08:00
|
|
|
|
2017-07-29 09:03:53 +08:00
|
|
|
; GFX89: {{flat|global}}_load_dwordx2
|
2017-02-28 06:15:25 +08:00
|
|
|
; GFX89: v_lshlrev_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}
|
2016-12-10 05:10:41 +08:00
|
|
|
|
|
|
|
|
; GCN: v_bfe_i32 v[[LO:[0-9]+]], v[[VAL_LO]], 0, 8
|
|
|
|
|
; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
|
|
|
|
|
|
2014-11-15 02:18:16 +08:00
|
|
|
; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX89: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[HI]]{{\]}}
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @v_sext_in_reg_i8_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) #0 {
|
2020-02-10 05:38:56 +08:00
|
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
[opaque pointer type] Add textual IR support for explicit type parameter to getelementptr instruction
One of several parallel first steps to remove the target type of pointers,
replacing them with a single opaque pointer type.
This adds an explicit type parameter to the gep instruction so that when the
first parameter becomes an opaque pointer type, the type to gep through is
still available to the instructions.
* This doesn't modify gep operators, only instructions (operators will be
handled separately)
* Textual IR changes only. Bitcode (including upgrade) and changing the
in-memory representation will be in separate changes.
* geps of vectors are transformed as:
getelementptr <4 x float*> %x, ...
->getelementptr float, <4 x float*> %x, ...
Then, once the opaque pointer type is introduced, this will ultimately look
like:
getelementptr float, <4 x ptr> %x
with the unambiguous interpretation that it is a vector of pointers to float.
* address spaces remain on the pointer, not the type:
getelementptr float addrspace(1)* %x
->getelementptr float, float addrspace(1)* %x
Then, eventually:
getelementptr float, ptr addrspace(1) %x
Importantly, the massive amount of test case churn has been automated by
same crappy python code. I had to manually update a few test cases that
wouldn't fit the script's model (r228970,r229196,r229197,r229198). The
python script just massages stdin and writes the result to stdout, I
then wrapped that in a shell script to handle replacing files, then
using the usual find+xargs to migrate all the files.
update.py:
import fileinput
import sys
import re
ibrep = re.compile(r"(^.*?[^%\w]getelementptr inbounds )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
normrep = re.compile( r"(^.*?[^%\w]getelementptr )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
def conv(match, line):
if not match:
return line
line = match.groups()[0]
if len(match.groups()[5]) == 0:
line += match.groups()[2]
line += match.groups()[3]
line += ", "
line += match.groups()[1]
line += "\n"
return line
for line in sys.stdin:
if line.find("getelementptr ") == line.find("getelementptr inbounds"):
if line.find("getelementptr inbounds") != line.find("getelementptr inbounds ("):
line = conv(re.match(ibrep, line), line)
elif line.find("getelementptr ") != line.find("getelementptr ("):
line = conv(re.match(normrep, line), line)
sys.stdout.write(line)
apply.sh:
for name in "$@"
do
python3 `dirname "$0"`/update.py < "$name" > "$name.tmp" && mv "$name.tmp" "$name"
rm -f "$name.tmp"
done
The actual commands:
From llvm/src:
find test/ -name *.ll | xargs ./apply.sh
From llvm/src/tools/clang:
find test/ -name *.mm -o -name *.m -o -name *.cpp -o -name *.c | xargs -I '{}' ../../apply.sh "{}"
From llvm/src/tools/polly:
find test/ -name *.ll | xargs ./apply.sh
After that, check-all (with llvm, clang, clang-tools-extra, lld,
compiler-rt, and polly all checked out).
The extra 'rm' in the apply.sh script is due to a few files in clang's test
suite using interesting unicode stuff that my python script was throwing
exceptions on. None of those files needed to be migrated, so it seemed
sufficient to ignore those cases.
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7636
llvm-svn: 230786
2015-02-28 03:29:02 +08:00
|
|
|
%a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
|
2015-02-28 05:17:42 +08:00
|
|
|
%a = load i64, i64 addrspace(1)* %a.gep, align 8
|
|
|
|
|
%b = load i64, i64 addrspace(1)* %b.gep, align 8
|
2014-11-15 02:18:16 +08:00
|
|
|
|
|
|
|
|
%c = shl i64 %a, %b
|
|
|
|
|
%shl = shl i64 %c, 56
|
|
|
|
|
%ashr = ashr i64 %shl, 56
|
|
|
|
|
store i64 %ashr, i64 addrspace(1)* %out.gep, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}v_sext_in_reg_i16_to_i64:
|
|
|
|
|
; SI: buffer_load_dwordx2
|
|
|
|
|
; SI: v_lshl_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}
|
2016-12-10 05:10:41 +08:00
|
|
|
|
2017-07-29 09:03:53 +08:00
|
|
|
; GFX89: {{flat|global}}_load_dwordx2
|
2017-02-28 06:15:25 +08:00
|
|
|
; GFX89: v_lshlrev_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}
|
2016-12-10 05:10:41 +08:00
|
|
|
|
|
|
|
|
; GCN: v_bfe_i32 v[[LO:[0-9]+]], v[[VAL_LO]], 0, 16
|
|
|
|
|
; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
|
|
|
|
|
|
2014-11-15 02:18:16 +08:00
|
|
|
; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX89: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[HI]]{{\]}}
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @v_sext_in_reg_i16_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) #0 {
|
2020-02-10 05:38:56 +08:00
|
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
[opaque pointer type] Add textual IR support for explicit type parameter to getelementptr instruction
One of several parallel first steps to remove the target type of pointers,
replacing them with a single opaque pointer type.
This adds an explicit type parameter to the gep instruction so that when the
first parameter becomes an opaque pointer type, the type to gep through is
still available to the instructions.
* This doesn't modify gep operators, only instructions (operators will be
handled separately)
* Textual IR changes only. Bitcode (including upgrade) and changing the
in-memory representation will be in separate changes.
* geps of vectors are transformed as:
getelementptr <4 x float*> %x, ...
->getelementptr float, <4 x float*> %x, ...
Then, once the opaque pointer type is introduced, this will ultimately look
like:
getelementptr float, <4 x ptr> %x
with the unambiguous interpretation that it is a vector of pointers to float.
* address spaces remain on the pointer, not the type:
getelementptr float addrspace(1)* %x
->getelementptr float, float addrspace(1)* %x
Then, eventually:
getelementptr float, ptr addrspace(1) %x
Importantly, the massive amount of test case churn has been automated by
same crappy python code. I had to manually update a few test cases that
wouldn't fit the script's model (r228970,r229196,r229197,r229198). The
python script just massages stdin and writes the result to stdout, I
then wrapped that in a shell script to handle replacing files, then
using the usual find+xargs to migrate all the files.
update.py:
import fileinput
import sys
import re
ibrep = re.compile(r"(^.*?[^%\w]getelementptr inbounds )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
normrep = re.compile( r"(^.*?[^%\w]getelementptr )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
def conv(match, line):
if not match:
return line
line = match.groups()[0]
if len(match.groups()[5]) == 0:
line += match.groups()[2]
line += match.groups()[3]
line += ", "
line += match.groups()[1]
line += "\n"
return line
for line in sys.stdin:
if line.find("getelementptr ") == line.find("getelementptr inbounds"):
if line.find("getelementptr inbounds") != line.find("getelementptr inbounds ("):
line = conv(re.match(ibrep, line), line)
elif line.find("getelementptr ") != line.find("getelementptr ("):
line = conv(re.match(normrep, line), line)
sys.stdout.write(line)
apply.sh:
for name in "$@"
do
python3 `dirname "$0"`/update.py < "$name" > "$name.tmp" && mv "$name.tmp" "$name"
rm -f "$name.tmp"
done
The actual commands:
From llvm/src:
find test/ -name *.ll | xargs ./apply.sh
From llvm/src/tools/clang:
find test/ -name *.mm -o -name *.m -o -name *.cpp -o -name *.c | xargs -I '{}' ../../apply.sh "{}"
From llvm/src/tools/polly:
find test/ -name *.ll | xargs ./apply.sh
After that, check-all (with llvm, clang, clang-tools-extra, lld,
compiler-rt, and polly all checked out).
The extra 'rm' in the apply.sh script is due to a few files in clang's test
suite using interesting unicode stuff that my python script was throwing
exceptions on. None of those files needed to be migrated, so it seemed
sufficient to ignore those cases.
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7636
llvm-svn: 230786
2015-02-28 03:29:02 +08:00
|
|
|
%a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
|
2015-02-28 05:17:42 +08:00
|
|
|
%a = load i64, i64 addrspace(1)* %a.gep, align 8
|
|
|
|
|
%b = load i64, i64 addrspace(1)* %b.gep, align 8
|
2014-11-15 02:18:16 +08:00
|
|
|
|
|
|
|
|
%c = shl i64 %a, %b
|
|
|
|
|
%shl = shl i64 %c, 48
|
|
|
|
|
%ashr = ashr i64 %shl, 48
|
|
|
|
|
store i64 %ashr, i64 addrspace(1)* %out.gep, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}v_sext_in_reg_i32_to_i64:
|
|
|
|
|
; SI: buffer_load_dwordx2
|
|
|
|
|
; SI: v_lshl_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}},
|
2016-12-10 05:10:41 +08:00
|
|
|
|
2017-07-29 09:03:53 +08:00
|
|
|
; GFX89: {{flat|global}}_load_dwordx2
|
2017-02-28 06:15:25 +08:00
|
|
|
; GFX89: v_lshlrev_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}},
|
2016-12-10 05:10:41 +08:00
|
|
|
|
|
|
|
|
; GCN: v_ashrrev_i32_e32 v[[SHR:[0-9]+]], 31, v[[LO]]
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX89: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[SHR]]{{\]}}
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @v_sext_in_reg_i32_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) #0 {
|
2020-02-10 05:38:56 +08:00
|
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
[opaque pointer type] Add textual IR support for explicit type parameter to getelementptr instruction
One of several parallel first steps to remove the target type of pointers,
replacing them with a single opaque pointer type.
This adds an explicit type parameter to the gep instruction so that when the
first parameter becomes an opaque pointer type, the type to gep through is
still available to the instructions.
* This doesn't modify gep operators, only instructions (operators will be
handled separately)
* Textual IR changes only. Bitcode (including upgrade) and changing the
in-memory representation will be in separate changes.
* geps of vectors are transformed as:
getelementptr <4 x float*> %x, ...
->getelementptr float, <4 x float*> %x, ...
Then, once the opaque pointer type is introduced, this will ultimately look
like:
getelementptr float, <4 x ptr> %x
with the unambiguous interpretation that it is a vector of pointers to float.
* address spaces remain on the pointer, not the type:
getelementptr float addrspace(1)* %x
->getelementptr float, float addrspace(1)* %x
Then, eventually:
getelementptr float, ptr addrspace(1) %x
Importantly, the massive amount of test case churn has been automated by
same crappy python code. I had to manually update a few test cases that
wouldn't fit the script's model (r228970,r229196,r229197,r229198). The
python script just massages stdin and writes the result to stdout, I
then wrapped that in a shell script to handle replacing files, then
using the usual find+xargs to migrate all the files.
update.py:
import fileinput
import sys
import re
ibrep = re.compile(r"(^.*?[^%\w]getelementptr inbounds )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
normrep = re.compile( r"(^.*?[^%\w]getelementptr )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
def conv(match, line):
if not match:
return line
line = match.groups()[0]
if len(match.groups()[5]) == 0:
line += match.groups()[2]
line += match.groups()[3]
line += ", "
line += match.groups()[1]
line += "\n"
return line
for line in sys.stdin:
if line.find("getelementptr ") == line.find("getelementptr inbounds"):
if line.find("getelementptr inbounds") != line.find("getelementptr inbounds ("):
line = conv(re.match(ibrep, line), line)
elif line.find("getelementptr ") != line.find("getelementptr ("):
line = conv(re.match(normrep, line), line)
sys.stdout.write(line)
apply.sh:
for name in "$@"
do
python3 `dirname "$0"`/update.py < "$name" > "$name.tmp" && mv "$name.tmp" "$name"
rm -f "$name.tmp"
done
The actual commands:
From llvm/src:
find test/ -name *.ll | xargs ./apply.sh
From llvm/src/tools/clang:
find test/ -name *.mm -o -name *.m -o -name *.cpp -o -name *.c | xargs -I '{}' ../../apply.sh "{}"
From llvm/src/tools/polly:
find test/ -name *.ll | xargs ./apply.sh
After that, check-all (with llvm, clang, clang-tools-extra, lld,
compiler-rt, and polly all checked out).
The extra 'rm' in the apply.sh script is due to a few files in clang's test
suite using interesting unicode stuff that my python script was throwing
exceptions on. None of those files needed to be migrated, so it seemed
sufficient to ignore those cases.
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7636
llvm-svn: 230786
2015-02-28 03:29:02 +08:00
|
|
|
%a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
|
2015-02-28 05:17:42 +08:00
|
|
|
%a = load i64, i64 addrspace(1)* %a.gep, align 8
|
|
|
|
|
%b = load i64, i64 addrspace(1)* %b.gep, align 8
|
2014-11-15 02:18:16 +08:00
|
|
|
|
|
|
|
|
%c = shl i64 %a, %b
|
|
|
|
|
%shl = shl i64 %c, 32
|
|
|
|
|
%ashr = ashr i64 %shl, 32
|
|
|
|
|
store i64 %ashr, i64 addrspace(1)* %out.gep, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-02 01:15:17 +08:00
|
|
|
; FUNC-LABEL: {{^}}sext_in_reg_i1_in_i32_other_amount:
|
2016-12-10 05:10:41 +08:00
|
|
|
; GCN-NOT: s_lshl
|
|
|
|
|
; GCN-NOT: s_ashr
|
|
|
|
|
; GCN: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x190001
|
2014-04-16 09:41:34 +08:00
|
|
|
|
|
|
|
|
; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
|
2014-03-18 02:58:11 +08:00
|
|
|
; EG-NOT: BFE
|
2014-04-16 09:41:34 +08:00
|
|
|
; EG: ADD_INT
|
|
|
|
|
; EG: LSHL
|
|
|
|
|
; EG: ASHR [[RES]]
|
|
|
|
|
; EG: LSHR {{\*?}} [[ADDR]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @sext_in_reg_i1_in_i32_other_amount(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
|
2014-03-18 02:58:11 +08:00
|
|
|
%c = add i32 %a, %b
|
|
|
|
|
%x = shl i32 %c, 6
|
|
|
|
|
%y = ashr i32 %x, 7
|
|
|
|
|
store i32 %y, i32 addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-02 01:15:17 +08:00
|
|
|
; FUNC-LABEL: {{^}}sext_in_reg_v2i1_in_v2i32_other_amount:
|
2016-12-10 05:10:41 +08:00
|
|
|
; GCN-NOT: s_lshl
|
|
|
|
|
; GCN-NOT: s_ashr
|
|
|
|
|
; GCN-DAG: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x190001
|
|
|
|
|
; GCN-DAG: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x190001
|
|
|
|
|
; GCN: s_endpgm
|
2014-04-16 09:41:34 +08:00
|
|
|
|
|
|
|
|
; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
|
2014-03-18 02:58:11 +08:00
|
|
|
; EG-NOT: BFE
|
2014-04-16 09:41:34 +08:00
|
|
|
; EG: ADD_INT
|
|
|
|
|
; EG: LSHL
|
|
|
|
|
; EG: ASHR [[RES]]
|
|
|
|
|
; EG: LSHL
|
|
|
|
|
; EG: ASHR [[RES]]
|
|
|
|
|
; EG: LSHR {{\*?}} [[ADDR]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @sext_in_reg_v2i1_in_v2i32_other_amount(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) #0 {
|
2014-03-18 02:58:11 +08:00
|
|
|
%c = add <2 x i32> %a, %b
|
|
|
|
|
%x = shl <2 x i32> %c, <i32 6, i32 6>
|
|
|
|
|
%y = ashr <2 x i32> %x, <i32 7, i32 7>
|
2016-07-02 06:55:55 +08:00
|
|
|
store <2 x i32> %y, <2 x i32> addrspace(1)* %out
|
2014-03-18 02:58:11 +08:00
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2014-10-02 01:15:17 +08:00
|
|
|
; FUNC-LABEL: {{^}}sext_in_reg_v2i1_to_v2i32:
|
2016-12-10 05:10:41 +08:00
|
|
|
; GCN: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
|
|
|
|
|
; GCN: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
|
|
|
|
|
; GCN: buffer_store_dwordx2
|
2014-04-16 09:41:34 +08:00
|
|
|
|
|
|
|
|
; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
|
|
|
|
|
; EG: BFE_INT [[RES]]
|
|
|
|
|
; EG: BFE_INT [[RES]]
|
|
|
|
|
; EG: LSHR {{\*?}} [[ADDR]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @sext_in_reg_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) #0 {
|
2014-03-18 02:58:11 +08:00
|
|
|
%c = add <2 x i32> %a, %b ; add to prevent folding into extload
|
|
|
|
|
%shl = shl <2 x i32> %c, <i32 31, i32 31>
|
|
|
|
|
%ashr = ashr <2 x i32> %shl, <i32 31, i32 31>
|
|
|
|
|
store <2 x i32> %ashr, <2 x i32> addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-02 01:15:17 +08:00
|
|
|
; FUNC-LABEL: {{^}}sext_in_reg_v4i1_to_v4i32:
|
2016-12-10 05:10:41 +08:00
|
|
|
; GCN: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
|
|
|
|
|
; GCN: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
|
|
|
|
|
; GCN: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
|
|
|
|
|
; GCN: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
|
|
|
|
|
; GCN: buffer_store_dwordx4
|
2014-03-18 02:58:11 +08:00
|
|
|
|
2014-04-16 09:41:34 +08:00
|
|
|
; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW][XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
|
|
|
|
|
; EG: BFE_INT [[RES]]
|
|
|
|
|
; EG: BFE_INT [[RES]]
|
|
|
|
|
; EG: BFE_INT [[RES]]
|
|
|
|
|
; EG: BFE_INT [[RES]]
|
|
|
|
|
; EG: LSHR {{\*?}} [[ADDR]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @sext_in_reg_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) #0 {
|
2014-03-18 02:58:11 +08:00
|
|
|
%c = add <4 x i32> %a, %b ; add to prevent folding into extload
|
|
|
|
|
%shl = shl <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
|
|
|
|
|
%ashr = ashr <4 x i32> %shl, <i32 31, i32 31, i32 31, i32 31>
|
|
|
|
|
store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-02 01:15:17 +08:00
|
|
|
; FUNC-LABEL: {{^}}sext_in_reg_v2i8_to_v2i32:
|
2016-12-10 05:10:41 +08:00
|
|
|
; GCN: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}}
|
|
|
|
|
; GCN: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}}
|
|
|
|
|
; GCN: buffer_store_dwordx2
|
2014-03-18 02:58:11 +08:00
|
|
|
|
2014-04-16 09:41:34 +08:00
|
|
|
; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
|
|
|
|
|
; EG: BFE_INT [[RES]]
|
|
|
|
|
; EG: BFE_INT [[RES]]
|
|
|
|
|
; EG: LSHR {{\*?}} [[ADDR]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @sext_in_reg_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) #0 {
|
2014-03-18 02:58:11 +08:00
|
|
|
%c = add <2 x i32> %a, %b ; add to prevent folding into extload
|
|
|
|
|
%shl = shl <2 x i32> %c, <i32 24, i32 24>
|
|
|
|
|
%ashr = ashr <2 x i32> %shl, <i32 24, i32 24>
|
|
|
|
|
store <2 x i32> %ashr, <2 x i32> addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-02 01:15:17 +08:00
|
|
|
; FUNC-LABEL: {{^}}sext_in_reg_v4i8_to_v4i32:
|
2016-12-10 05:10:41 +08:00
|
|
|
; GCN: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}}
|
|
|
|
|
; GCN: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}}
|
|
|
|
|
; GCN: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}}
|
|
|
|
|
; GCN: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}}
|
|
|
|
|
; GCN: buffer_store_dwordx4
|
2014-03-18 02:58:11 +08:00
|
|
|
|
2014-04-16 09:41:34 +08:00
|
|
|
; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW][XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
|
|
|
|
|
; EG: BFE_INT [[RES]]
|
|
|
|
|
; EG: BFE_INT [[RES]]
|
|
|
|
|
; EG: BFE_INT [[RES]]
|
|
|
|
|
; EG: BFE_INT [[RES]]
|
|
|
|
|
; EG: LSHR {{\*?}} [[ADDR]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @sext_in_reg_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) #0 {
|
2014-03-18 02:58:11 +08:00
|
|
|
%c = add <4 x i32> %a, %b ; add to prevent folding into extload
|
|
|
|
|
%shl = shl <4 x i32> %c, <i32 24, i32 24, i32 24, i32 24>
|
|
|
|
|
%ashr = ashr <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24>
|
|
|
|
|
store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-02 01:15:17 +08:00
|
|
|
; FUNC-LABEL: {{^}}sext_in_reg_v2i16_to_v2i32:
|
2016-12-10 05:10:41 +08:00
|
|
|
; GCN: s_sext_i32_i16 {{s[0-9]+}}, {{s[0-9]+}}
|
|
|
|
|
; GCN: s_sext_i32_i16 {{s[0-9]+}}, {{s[0-9]+}}
|
|
|
|
|
; GCN: buffer_store_dwordx2
|
2014-03-18 02:58:11 +08:00
|
|
|
|
2014-04-16 09:41:34 +08:00
|
|
|
; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
|
|
|
|
|
; EG: BFE_INT [[RES]]
|
|
|
|
|
; EG: BFE_INT [[RES]]
|
|
|
|
|
; EG: LSHR {{\*?}} [[ADDR]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @sext_in_reg_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) #0 {
|
2014-03-18 02:58:11 +08:00
|
|
|
%c = add <2 x i32> %a, %b ; add to prevent folding into extload
|
2014-04-18 09:53:18 +08:00
|
|
|
%shl = shl <2 x i32> %c, <i32 16, i32 16>
|
|
|
|
|
%ashr = ashr <2 x i32> %shl, <i32 16, i32 16>
|
2014-03-18 02:58:11 +08:00
|
|
|
store <2 x i32> %ashr, <2 x i32> addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-02 01:15:17 +08:00
|
|
|
; FUNC-LABEL: {{^}}testcase:
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @testcase(i8 addrspace(1)* %out, i8 %a) #0 {
|
2014-03-18 02:58:11 +08:00
|
|
|
%and_a_1 = and i8 %a, 1
|
|
|
|
|
%cmp_eq = icmp eq i8 %and_a_1, 0
|
|
|
|
|
%cmp_slt = icmp slt i8 %a, 0
|
|
|
|
|
%sel0 = select i1 %cmp_slt, i8 0, i8 %a
|
|
|
|
|
%sel1 = select i1 %cmp_eq, i8 0, i8 %a
|
|
|
|
|
%xor = xor i8 %sel0, %sel1
|
|
|
|
|
store i8 %xor, i8 addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-02 01:15:17 +08:00
|
|
|
; FUNC-LABEL: {{^}}testcase_3:
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @testcase_3(i8 addrspace(1)* %out, i8 %a) #0 {
|
2014-03-18 02:58:11 +08:00
|
|
|
%and_a_1 = and i8 %a, 1
|
|
|
|
|
%cmp_eq = icmp eq i8 %and_a_1, 0
|
|
|
|
|
%cmp_slt = icmp slt i8 %a, 0
|
|
|
|
|
%sel0 = select i1 %cmp_slt, i8 0, i8 %a
|
|
|
|
|
%sel1 = select i1 %cmp_eq, i8 0, i8 %a
|
|
|
|
|
%xor = xor i8 %sel0, %sel1
|
|
|
|
|
store i8 %xor, i8 addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
2014-03-28 01:23:24 +08:00
|
|
|
|
2014-10-02 01:15:17 +08:00
|
|
|
; FUNC-LABEL: {{^}}vgpr_sext_in_reg_v4i8_to_v4i32:
|
2016-12-10 05:10:41 +08:00
|
|
|
; GCN: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8
|
|
|
|
|
; GCN: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8
|
|
|
|
|
; GCN: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8
|
|
|
|
|
; GCN: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @vgpr_sext_in_reg_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %a, <4 x i32> addrspace(1)* %b) #0 {
|
2015-02-28 05:17:42 +08:00
|
|
|
%loada = load <4 x i32>, <4 x i32> addrspace(1)* %a, align 16
|
|
|
|
|
%loadb = load <4 x i32>, <4 x i32> addrspace(1)* %b, align 16
|
2014-04-18 13:19:26 +08:00
|
|
|
%c = add <4 x i32> %loada, %loadb ; add to prevent folding into extload
|
|
|
|
|
%shl = shl <4 x i32> %c, <i32 24, i32 24, i32 24, i32 24>
|
|
|
|
|
%ashr = ashr <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24>
|
|
|
|
|
store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-02 01:15:17 +08:00
|
|
|
; FUNC-LABEL: {{^}}vgpr_sext_in_reg_v4i16_to_v4i32:
|
2016-12-10 05:10:41 +08:00
|
|
|
; GCN: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 16
|
|
|
|
|
; GCN: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 16
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @vgpr_sext_in_reg_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %a, <4 x i32> addrspace(1)* %b) #0 {
|
2015-02-28 05:17:42 +08:00
|
|
|
%loada = load <4 x i32>, <4 x i32> addrspace(1)* %a, align 16
|
|
|
|
|
%loadb = load <4 x i32>, <4 x i32> addrspace(1)* %b, align 16
|
2014-04-18 13:19:26 +08:00
|
|
|
%c = add <4 x i32> %loada, %loadb ; add to prevent folding into extload
|
|
|
|
|
%shl = shl <4 x i32> %c, <i32 16, i32 16, i32 16, i32 16>
|
|
|
|
|
%ashr = ashr <4 x i32> %shl, <i32 16, i32 16, i32 16, i32 16>
|
|
|
|
|
store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-02 01:15:17 +08:00
|
|
|
; FUNC-LABEL: {{^}}sext_in_reg_to_illegal_type:
|
2016-12-10 05:10:41 +08:00
|
|
|
; GCN: buffer_load_sbyte
|
|
|
|
|
; GCN: v_max_i32
|
|
|
|
|
; GCN-NOT: bfe
|
|
|
|
|
; GCN: buffer_store_short
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @sext_in_reg_to_illegal_type(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) #0 {
|
2015-02-28 05:17:42 +08:00
|
|
|
%tmp5 = load i8, i8 addrspace(1)* %src, align 1
|
2014-03-28 01:23:24 +08:00
|
|
|
%tmp2 = sext i8 %tmp5 to i32
|
2016-01-21 04:50:19 +08:00
|
|
|
%tmp2.5 = icmp sgt i32 %tmp2, 0
|
|
|
|
|
%tmp3 = select i1 %tmp2.5, i32 %tmp2, i32 0
|
2014-03-28 01:23:24 +08:00
|
|
|
%tmp4 = trunc i32 %tmp3 to i8
|
|
|
|
|
%tmp6 = sext i8 %tmp4 to i16
|
|
|
|
|
store i16 %tmp6, i16 addrspace(1)* %out, align 2
|
|
|
|
|
ret void
|
|
|
|
|
}
|
2014-05-23 02:09:03 +08:00
|
|
|
|
2015-08-27 04:47:58 +08:00
|
|
|
; Make sure we propagate the VALUness to users of a moved scalar BFE.
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}v_sext_in_reg_i1_to_i64_move_use:
|
|
|
|
|
; SI: buffer_load_dwordx2
|
|
|
|
|
; SI: v_lshl_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}
|
2016-12-10 05:10:41 +08:00
|
|
|
|
2017-07-29 09:03:53 +08:00
|
|
|
; GFX89: {{flat|global}}_load_dwordx2
|
2017-02-28 06:15:25 +08:00
|
|
|
; GFX89: v_lshlrev_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}
|
2016-12-10 05:10:41 +08:00
|
|
|
|
|
|
|
|
; GCN-DAG: v_bfe_i32 v[[LO:[0-9]+]], v[[VAL_LO]], 0, 1
|
|
|
|
|
; GCN-DAG: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
|
|
|
|
|
; GCN-DAG: v_and_b32_e32 v[[RESULT_LO:[0-9]+]], s{{[0-9]+}}, v[[LO]]
|
|
|
|
|
; GCN-DAG: v_and_b32_e32 v[[RESULT_HI:[0-9]+]], s{{[0-9]+}}, v[[HI]]
|
2015-08-27 04:47:58 +08:00
|
|
|
; SI: buffer_store_dwordx2 v{{\[}}[[RESULT_LO]]:[[RESULT_HI]]{{\]}}
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX89: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[RESULT_LO]]:[[RESULT_HI]]{{\]}}
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @v_sext_in_reg_i1_to_i64_move_use(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr, i64 %s.val) #0 {
|
2020-02-10 05:38:56 +08:00
|
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
2015-08-27 04:47:58 +08:00
|
|
|
%a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
|
|
|
|
|
%a = load i64, i64 addrspace(1)* %a.gep, align 8
|
|
|
|
|
%b = load i64, i64 addrspace(1)* %b.gep, align 8
|
|
|
|
|
|
|
|
|
|
%c = shl i64 %a, %b
|
|
|
|
|
%shl = shl i64 %c, 63
|
|
|
|
|
%ashr = ashr i64 %shl, 63
|
|
|
|
|
|
|
|
|
|
%and = and i64 %ashr, %s.val
|
|
|
|
|
store i64 %and, i64 addrspace(1)* %out.gep, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}v_sext_in_reg_i32_to_i64_move_use:
|
|
|
|
|
; SI: buffer_load_dwordx2
|
|
|
|
|
; SI: v_lshl_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}},
|
2016-12-10 05:10:41 +08:00
|
|
|
|
2017-07-29 09:03:53 +08:00
|
|
|
; GFX89: {{flat|global}}_load_dwordx2
|
2017-02-28 06:15:25 +08:00
|
|
|
; GFX89: v_lshlrev_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}},
|
2016-12-10 05:10:41 +08:00
|
|
|
|
|
|
|
|
; GCN-DAG: v_ashrrev_i32_e32 v[[SHR:[0-9]+]], 31, v[[LO]]
|
|
|
|
|
; GCN-DAG: v_and_b32_e32 v[[RESULT_LO:[0-9]+]], s{{[0-9]+}}, v[[LO]]
|
|
|
|
|
; GCN-DAG: v_and_b32_e32 v[[RESULT_HI:[0-9]+]], s{{[0-9]+}}, v[[SHR]]
|
|
|
|
|
|
2015-08-27 04:47:58 +08:00
|
|
|
; SI: buffer_store_dwordx2 v{{\[}}[[RESULT_LO]]:[[RESULT_HI]]{{\]}}
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX89: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[RESULT_LO]]:[[RESULT_HI]]{{\]}}
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @v_sext_in_reg_i32_to_i64_move_use(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr, i64 %s.val) #0 {
|
2020-02-10 05:38:56 +08:00
|
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
2015-08-27 04:47:58 +08:00
|
|
|
%a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
|
|
|
|
|
%a = load i64, i64 addrspace(1)* %a.gep, align 8
|
|
|
|
|
%b = load i64, i64 addrspace(1)* %b.gep, align 8
|
|
|
|
|
|
|
|
|
|
%c = shl i64 %a, %b
|
|
|
|
|
%shl = shl i64 %c, 32
|
|
|
|
|
%ashr = ashr i64 %shl, 32
|
|
|
|
|
%and = and i64 %ashr, %s.val
|
|
|
|
|
store i64 %and, i64 addrspace(1)* %out.gep, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
2016-12-10 05:10:41 +08:00
|
|
|
|
2017-01-12 06:35:22 +08:00
|
|
|
; FUNC-LABEL: {{^}}s_sext_in_reg_i1_i16:
|
|
|
|
|
; GCN: s_load_dword [[VAL:s[0-9]+]]
|
|
|
|
|
|
|
|
|
|
; SI: s_bfe_i32 [[BFE:s[0-9]+]], [[VAL]], 0x10000
|
|
|
|
|
; SI: v_mov_b32_e32 [[VBFE:v[0-9]+]], [[BFE]]
|
|
|
|
|
; SI: buffer_store_short [[VBFE]]
|
|
|
|
|
|
2017-02-28 06:15:25 +08:00
|
|
|
; GFX89: s_lshl_b32 s{{[0-9]+}}, s{{[0-9]+}}, 15
|
|
|
|
|
; GFX89: s_sext_i32_i16 s{{[0-9]+}}, s{{[0-9]+}}
|
|
|
|
|
; GFX89: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 15
|
2018-02-14 02:00:25 +08:00
|
|
|
define amdgpu_kernel void @s_sext_in_reg_i1_i16(i16 addrspace(1)* %out, i32 addrspace(4)* %ptr) #0 {
|
|
|
|
|
%ld = load i32, i32 addrspace(4)* %ptr
|
2017-01-12 06:35:22 +08:00
|
|
|
%in = trunc i32 %ld to i16
|
|
|
|
|
%shl = shl i16 %in, 15
|
|
|
|
|
%sext = ashr i16 %shl, 15
|
|
|
|
|
store i16 %sext, i16 addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}s_sext_in_reg_i2_i16:
|
|
|
|
|
; GCN: s_load_dword [[VAL:s[0-9]+]]
|
|
|
|
|
|
|
|
|
|
; SI: s_bfe_i32 [[BFE:s[0-9]+]], [[VAL]], 0x20000
|
|
|
|
|
; SI: v_mov_b32_e32 [[VBFE:v[0-9]+]], [[BFE]]
|
|
|
|
|
; SI: buffer_store_short [[VBFE]]
|
|
|
|
|
|
2017-02-28 06:15:25 +08:00
|
|
|
; GFX89: s_lshl_b32 s{{[0-9]+}}, s{{[0-9]+}}, 14
|
|
|
|
|
; GFX89: s_sext_i32_i16 s{{[0-9]+}}, s{{[0-9]+}}
|
|
|
|
|
; GFX89: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 14
|
2018-02-14 02:00:25 +08:00
|
|
|
define amdgpu_kernel void @s_sext_in_reg_i2_i16(i16 addrspace(1)* %out, i32 addrspace(4)* %ptr) #0 {
|
|
|
|
|
%ld = load i32, i32 addrspace(4)* %ptr
|
2017-01-12 06:35:22 +08:00
|
|
|
%in = trunc i32 %ld to i16
|
|
|
|
|
%shl = shl i16 %in, 14
|
|
|
|
|
%sext = ashr i16 %shl, 14
|
|
|
|
|
store i16 %sext, i16 addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}v_sext_in_reg_i1_i16:
|
2017-07-29 09:03:53 +08:00
|
|
|
; GCN: {{buffer|flat|global}}_load_ushort [[VAL:v[0-9]+]]
|
2017-01-12 06:35:22 +08:00
|
|
|
; GCN: v_bfe_i32 [[BFE:v[0-9]+]], [[VAL]], 0, 1{{$}}
|
|
|
|
|
|
|
|
|
|
; GCN: ds_write_b16 v{{[0-9]+}}, [[BFE]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @v_sext_in_reg_i1_i16(i16 addrspace(3)* %out, i16 addrspace(1)* %ptr) #0 {
|
2020-02-10 05:38:56 +08:00
|
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
2017-01-12 06:35:22 +08:00
|
|
|
%gep = getelementptr i16, i16 addrspace(1)* %ptr, i32 %tid
|
|
|
|
|
%out.gep = getelementptr i16, i16 addrspace(3)* %out, i32 %tid
|
|
|
|
|
|
|
|
|
|
%in = load i16, i16 addrspace(1)* %gep
|
|
|
|
|
%shl = shl i16 %in, 15
|
|
|
|
|
%sext = ashr i16 %shl, 15
|
|
|
|
|
store i16 %sext, i16 addrspace(3)* %out.gep
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}v_sext_in_reg_i1_i16_nonload:
|
2017-07-29 09:03:53 +08:00
|
|
|
; GCN: {{buffer|flat|global}}_load_ushort [[VAL0:v[0-9]+]]
|
|
|
|
|
; GCN: {{buffer|flat|global}}_load_ushort [[VAL1:v[0-9]+]]
|
2017-01-12 06:35:22 +08:00
|
|
|
|
2020-02-01 01:49:00 +08:00
|
|
|
; SI: v_lshl_b32_e32 [[REG:v[0-9]+]], [[VAL0]], [[VAL1]]
|
2017-02-28 06:15:25 +08:00
|
|
|
; GFX89: v_lshlrev_b16_e32 [[REG:v[0-9]+]], [[VAL1]], [[VAL0]]
|
2017-01-12 06:35:22 +08:00
|
|
|
|
|
|
|
|
; GCN: v_bfe_i32 [[BFE:v[0-9]+]], [[REG]], 0, 1{{$}}
|
|
|
|
|
; GCN: ds_write_b16 v{{[0-9]+}}, [[BFE]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @v_sext_in_reg_i1_i16_nonload(i16 addrspace(3)* %out, i16 addrspace(1)* %aptr, i16 addrspace(1)* %bptr, i16 %s.val) nounwind {
|
2020-02-10 05:38:56 +08:00
|
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
2017-01-12 06:35:22 +08:00
|
|
|
%a.gep = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%b.gep = getelementptr i16, i16 addrspace(1)* %bptr, i32 %tid
|
|
|
|
|
%out.gep = getelementptr i16, i16 addrspace(3)* %out, i32 %tid
|
|
|
|
|
%a = load volatile i16, i16 addrspace(1)* %a.gep, align 2
|
|
|
|
|
%b = load volatile i16, i16 addrspace(1)* %b.gep, align 2
|
|
|
|
|
|
|
|
|
|
%c = shl i16 %a, %b
|
|
|
|
|
%shl = shl i16 %c, 15
|
|
|
|
|
%ashr = ashr i16 %shl, 15
|
|
|
|
|
|
|
|
|
|
store i16 %ashr, i16 addrspace(3)* %out.gep, align 2
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}s_sext_in_reg_i2_i16_arg:
|
|
|
|
|
; GCN: s_load_dword [[VAL:s[0-9]+]]
|
|
|
|
|
|
|
|
|
|
; SI: s_bfe_i32 [[BFE:s[0-9]+]], [[VAL]], 0x20000
|
|
|
|
|
; SI: v_mov_b32_e32 [[VBFE:v[0-9]+]], [[BFE]]
|
|
|
|
|
; SI: buffer_store_short [[VBFE]]
|
|
|
|
|
|
2017-02-28 06:15:25 +08:00
|
|
|
; GFX89: s_lshl_b32 s{{[0-9]+}}, s{{[0-9]+}}, 14{{$}}
|
|
|
|
|
; GFX89: s_sext_i32_i16 s{{[0-9]+}}, s{{[0-9]+}}
|
|
|
|
|
; GFX89: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 14{{$}}
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @s_sext_in_reg_i2_i16_arg(i16 addrspace(1)* %out, i16 %in) #0 {
|
2017-01-12 06:35:22 +08:00
|
|
|
%shl = shl i16 %in, 14
|
|
|
|
|
%sext = ashr i16 %shl, 14
|
|
|
|
|
store i16 %sext, i16 addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}s_sext_in_reg_i8_i16_arg:
|
|
|
|
|
; GCN: s_load_dword [[VAL:s[0-9]+]]
|
|
|
|
|
|
|
|
|
|
; SI: s_sext_i32_i8 [[SSEXT:s[0-9]+]], [[VAL]]
|
|
|
|
|
; SI: v_mov_b32_e32 [[VSEXT:v[0-9]+]], [[SSEXT]]
|
2017-11-13 07:53:44 +08:00
|
|
|
; SI: buffer_store_short [[VSEXT]]
|
2017-01-12 06:35:22 +08:00
|
|
|
|
2017-02-28 06:15:25 +08:00
|
|
|
; GFX89: s_lshl_b32 s{{[0-9]+}}, s{{[0-9]+}}, 8{{$}}
|
|
|
|
|
; GFX89: s_sext_i32_i16 s{{[0-9]+}}, s{{[0-9]+}}
|
|
|
|
|
; GFX89: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 8{{$}}
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @s_sext_in_reg_i8_i16_arg(i16 addrspace(1)* %out, i16 %in) #0 {
|
2017-01-12 06:35:22 +08:00
|
|
|
%shl = shl i16 %in, 8
|
|
|
|
|
%sext = ashr i16 %shl, 8
|
|
|
|
|
store i16 %sext, i16 addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}s_sext_in_reg_i15_i16_arg:
|
|
|
|
|
; GCN: s_load_dword [[VAL:s[0-9]+]]
|
|
|
|
|
|
|
|
|
|
; SI: s_bfe_i32 [[BFE:s[0-9]+]], [[VAL]], 0xf0000
|
|
|
|
|
; SI: v_mov_b32_e32 [[VBFE:v[0-9]+]], [[BFE]]
|
|
|
|
|
; SI: buffer_store_short [[VBFE]]
|
|
|
|
|
|
2017-02-28 06:15:25 +08:00
|
|
|
; GFX89: s_lshl_b32 s{{[0-9]+}}, s{{[0-9]+}}, 1{{$}}
|
|
|
|
|
; GFX89: s_sext_i32_i16 s{{[0-9]+}}, s{{[0-9]+}}
|
|
|
|
|
; GFX89: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 1{{$}}
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @s_sext_in_reg_i15_i16_arg(i16 addrspace(1)* %out, i16 %in) #0 {
|
2017-01-12 06:35:22 +08:00
|
|
|
%shl = shl i16 %in, 1
|
|
|
|
|
%sext = ashr i16 %shl, 1
|
|
|
|
|
store i16 %sext, i16 addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-02-28 06:15:25 +08:00
|
|
|
; FUNC-LABEL: {{^}}sext_in_reg_v2i1_to_v2i16:
|
|
|
|
|
; GFX9: v_pk_add_u16 [[ADD:v[0-9]+]]
|
|
|
|
|
; GFX9: v_pk_lshlrev_b16 [[SHL:v[0-9]+]], 15, [[ADD]]
|
|
|
|
|
; GFX9: v_pk_ashrrev_i16 [[SRA:v[0-9]+]], 15, [[SHL]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @sext_in_reg_v2i1_to_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %a, <2 x i16> %b) #0 {
|
2017-02-28 06:15:25 +08:00
|
|
|
%c = add <2 x i16> %a, %b ; add to prevent folding into extload
|
|
|
|
|
%shl = shl <2 x i16> %c, <i16 15, i16 15>
|
|
|
|
|
%ashr = ashr <2 x i16> %shl, <i16 15, i16 15>
|
|
|
|
|
store <2 x i16> %ashr, <2 x i16> addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}sext_in_reg_v3i1_to_v3i16:
|
|
|
|
|
; GFX9: v_pk_add_u16
|
2017-09-20 13:01:53 +08:00
|
|
|
; GFX9: v_pk_add_u16
|
|
|
|
|
; GFX9: v_pk_lshlrev_b16 v{{[0-9]+}}, 15, v{{[0-9]+}}
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
; GFX9: v_pk_lshlrev_b16 v{{[0-9]+}}, 15, v{{[0-9]+}}
|
|
|
|
|
; GFX9: v_pk_ashrrev_i16 v{{[0-9]+}}, 15, v{{[0-9]+}}
|
2017-02-28 06:15:25 +08:00
|
|
|
; GFX9: v_pk_ashrrev_i16 v{{[0-9]+}}, 15, v{{[0-9]+}}
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @sext_in_reg_v3i1_to_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %a, <3 x i16> %b) #0 {
|
2017-02-28 06:15:25 +08:00
|
|
|
%c = add <3 x i16> %a, %b ; add to prevent folding into extload
|
|
|
|
|
%shl = shl <3 x i16> %c, <i16 15, i16 15, i16 15>
|
|
|
|
|
%ashr = ashr <3 x i16> %shl, <i16 15, i16 15, i16 15>
|
|
|
|
|
store <3 x i16> %ashr, <3 x i16> addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
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; FUNC-LABEL: {{^}}sext_in_reg_v2i2_to_v2i16:
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; GFX9: v_pk_add_u16 [[ADD:v[0-9]+]]
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; GFX9: v_pk_lshlrev_b16 [[SHL:v[0-9]+]], 14, [[ADD]]
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; GFX9: v_pk_ashrrev_i16 [[SRA:v[0-9]+]], 14, [[SHL]]
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2017-03-22 05:39:51 +08:00
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define amdgpu_kernel void @sext_in_reg_v2i2_to_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %a, <2 x i16> %b) #0 {
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2017-02-28 06:15:25 +08:00
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%c = add <2 x i16> %a, %b ; add to prevent folding into extload
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%shl = shl <2 x i16> %c, <i16 14, i16 14>
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%ashr = ashr <2 x i16> %shl, <i16 14, i16 14>
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store <2 x i16> %ashr, <2 x i16> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}sext_in_reg_v2i8_to_v2i16:
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; GFX9: v_pk_add_u16 [[ADD:v[0-9]+]]
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; GFX9: v_pk_lshlrev_b16 [[SHL:v[0-9]+]], 8, [[ADD]]
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; GFX9: v_pk_ashrrev_i16 [[SRA:v[0-9]+]], 8, [[SHL]]
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2017-03-22 05:39:51 +08:00
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define amdgpu_kernel void @sext_in_reg_v2i8_to_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %a, <2 x i16> %b) #0 {
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2017-02-28 06:15:25 +08:00
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%c = add <2 x i16> %a, %b ; add to prevent folding into extload
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%shl = shl <2 x i16> %c, <i16 8, i16 8>
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%ashr = ashr <2 x i16> %shl, <i16 8, i16 8>
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store <2 x i16> %ashr, <2 x i16> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}sext_in_reg_v3i8_to_v3i16:
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; GFX9: v_pk_add_u16
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2017-09-20 13:01:53 +08:00
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; GFX9: v_pk_add_u16
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; GFX9: v_pk_lshlrev_b16 v{{[0-9]+}}, 8, v{{[0-9]+}}
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AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
; GFX9: v_pk_lshlrev_b16 v{{[0-9]+}}, 8, v{{[0-9]+}}
|
|
|
|
|
; GFX9: v_pk_ashrrev_i16 v{{[0-9]+}}, 8, v{{[0-9]+}}
|
2017-02-28 06:15:25 +08:00
|
|
|
; GFX9: v_pk_ashrrev_i16 v{{[0-9]+}}, 8, v{{[0-9]+}}
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @sext_in_reg_v3i8_to_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %a, <3 x i16> %b) #0 {
|
2017-02-28 06:15:25 +08:00
|
|
|
%c = add <3 x i16> %a, %b ; add to prevent folding into extload
|
|
|
|
|
%shl = shl <3 x i16> %c, <i16 8, i16 8, i16 8>
|
|
|
|
|
%ashr = ashr <3 x i16> %shl, <i16 8, i16 8, i16 8>
|
|
|
|
|
store <3 x i16> %ashr, <3 x i16> addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2020-02-10 05:38:56 +08:00
|
|
|
declare i32 @llvm.amdgcn.workitem.id.x() #1
|
2016-12-10 05:10:41 +08:00
|
|
|
|
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|
attributes #0 = { nounwind }
|
|
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|
|
attributes #1 = { nounwind readnone }
|