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llvm-project/llvm/test/CodeGen/AMDGPU/merge-load-store-agpr.mir

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[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
# RUN: llc -march=amdgcn -mcpu=gfx90a -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -enable-var-scope -check-prefix=GCN %s
# GCN-LABEL: name: ds_read_b32_v_v
AMDGPU: Add even aligned VGPR/AGPR register classes gfx90a operations require even aligned registers, but this was previously achieved by reserving registers inside the full class. Ideally this would be captured in the static instruction definitions for the operands, and we would have different instructions per subtarget. The hackiest part of this is we need to manually reassign AGPR register classes after instruction selection (we get away without this for VGPRs since those types are actually registered for legal types).
2021-02-19 21:57:14 +08:00
# GCN: vreg_64_align2 = DS_READ2_B32
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
name: ds_read_b32_v_v
body: |
bb.0:
%0:vgpr_32 = IMPLICIT_DEF
%1:vgpr_32 = DS_READ_B32_gfx9 %0, 0, 0, implicit $exec :: (load 4 from `i32 addrspace(3)* undef`)
%2:vgpr_32 = DS_READ_B32_gfx9 %0, 8, 0, implicit $exec :: (load 4 from `i32 addrspace(3)* undef`)
...
# GCN-LABEL: name: ds_read_b32_a_a
AMDGPU: Add even aligned VGPR/AGPR register classes gfx90a operations require even aligned registers, but this was previously achieved by reserving registers inside the full class. Ideally this would be captured in the static instruction definitions for the operands, and we would have different instructions per subtarget. The hackiest part of this is we need to manually reassign AGPR register classes after instruction selection (we get away without this for VGPRs since those types are actually registered for legal types).
2021-02-19 21:57:14 +08:00
# GCN: areg_64_align2 = DS_READ2_B32
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
name: ds_read_b32_a_a
body: |
bb.0:
%0:vgpr_32 = IMPLICIT_DEF
%1:agpr_32 = DS_READ_B32_gfx9 %0, 0, 0, implicit $exec :: (load 4 from `i32 addrspace(3)* undef`)
%2:agpr_32 = DS_READ_B32_gfx9 %0, 8, 0, implicit $exec :: (load 4 from `i32 addrspace(3)* undef`)
...
# GCN-LABEL: name: ds_read_b32_v_a
# GCN: vgpr_32 = DS_READ_B32
# GCN: agpr_32 = DS_READ_B32
name: ds_read_b32_v_a
body: |
bb.0:
%0:vgpr_32 = IMPLICIT_DEF
%1:vgpr_32 = DS_READ_B32_gfx9 %0, 0, 0, implicit $exec :: (load 4 from `i32 addrspace(3)* undef`)
%2:agpr_32 = DS_READ_B32_gfx9 %0, 8, 0, implicit $exec :: (load 4 from `i32 addrspace(3)* undef`)
...
# GCN-LABEL: name: ds_read_b32_a_v
# GCN: agpr_32 = DS_READ_B32
# GCN: vgpr_32 = DS_READ_B32
name: ds_read_b32_a_v
body: |
bb.0:
%0:vgpr_32 = IMPLICIT_DEF
%1:agpr_32 = DS_READ_B32_gfx9 %0, 8, 0, implicit $exec :: (load 4 from `i32 addrspace(3)* undef`)
%2:vgpr_32 = DS_READ_B32_gfx9 %0, 0, 0, implicit $exec :: (load 4 from `i32 addrspace(3)* undef`)
...
# GCN-LABEL: name: ds_write_b32_v_v
# GCN: DS_WRITE2_B32_gfx9 %0, undef %1:vgpr_32, undef %2:vgpr_32
name: ds_write_b32_v_v
body: |
bb.0:
%0:vgpr_32 = IMPLICIT_DEF
DS_WRITE_B32_gfx9 %0, undef %1:vgpr_32, 0, 0, implicit $exec :: (store 4 into `i32 addrspace(3)* undef`)
DS_WRITE_B32_gfx9 %0, undef %2:vgpr_32, 8, 0, implicit $exec :: (store 4 into `i32 addrspace(3)* undef`)
...
# GCN-LABEL: name: ds_write_b32_a_a
# GCN: DS_WRITE_B32_gfx9 %0, undef %1:agpr_32
# GCN: DS_WRITE_B32_gfx9 %0, undef %2:agpr_32
name: ds_write_b32_a_a
body: |
bb.0:
%0:vgpr_32 = IMPLICIT_DEF
DS_WRITE_B32_gfx9 %0, undef %1:agpr_32, 0, 0, implicit $exec :: (store 4 into `i32 addrspace(3)* undef`)
DS_WRITE_B32_gfx9 %0, undef %2:agpr_32, 8, 0, implicit $exec :: (store 4 into `i32 addrspace(3)* undef`)
...
# GCN-LABEL: name: ds_write_b32_v_a
# GCN: DS_WRITE_B32_gfx9 %0, undef %1:vgpr_32
# GCN: DS_WRITE_B32_gfx9 %0, undef %2:agpr_32
name: ds_write_b32_v_a
body: |
bb.0:
%0:vgpr_32 = IMPLICIT_DEF
DS_WRITE_B32_gfx9 %0, undef %1:vgpr_32, 0, 0, implicit $exec :: (store 4 into `i32 addrspace(3)* undef`)
DS_WRITE_B32_gfx9 %0, undef %2:agpr_32, 8, 0, implicit $exec :: (store 4 into `i32 addrspace(3)* undef`)
...
# GCN-LABEL: name: ds_write_b32_a_v
# GCN: DS_WRITE_B32_gfx9 %0, undef %1:agpr_32
# GCN: DS_WRITE_B32_gfx9 %0, undef %2:vgpr_32
name: ds_write_b32_a_v
body: |
bb.0:
%0:vgpr_32 = IMPLICIT_DEF
DS_WRITE_B32_gfx9 %0, undef %1:agpr_32, 0, 0, implicit $exec :: (store 4 into `i32 addrspace(3)* undef`)
DS_WRITE_B32_gfx9 %0, undef %2:vgpr_32, 8, 0, implicit $exec :: (store 4 into `i32 addrspace(3)* undef`)
...