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[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-WGP %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-CU %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx700 -amdgcn-skip-cache-invalidations -verify-machineinstrs < %s | FileCheck --check-prefixes=SKIP-CACHE-INV %s
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX90A-NOTTGSPLIT %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -mattr=+tgsplit -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX90A-TGSPLIT %s
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
define amdgpu_kernel void @local_agent_unordered_load(
; GFX6-LABEL: local_agent_unordered_load:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s0
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_read_b32 v0, v0
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: ds_write_b32 v1, v0
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_unordered_load:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: ds_read_b32 v0, v0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: ds_write_b32 v1, v0
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_unordered_load:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: ds_read_b32 v0, v0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: ds_write_b32 v1, v0
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_unordered_load:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
; GFX10-CU-NEXT: ds_read_b32 v0, v0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: ds_write_b32 v1, v0
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_unordered_load:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: ds_read_b32 v0, v0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: ds_write_b32 v1, v0
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_unordered_load:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: ds_read_b32 v0, v0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v1, v0
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_unordered_load:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: ds_read_b32 v0, v0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v1, v0
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %in, i32 addrspace(3)* %out) {
entry:
%val = load atomic i32, i32 addrspace(3)* %in syncscope("agent") unordered, align 4
store i32 %val, i32 addrspace(3)* %out
ret void
}
define amdgpu_kernel void @local_agent_monotonic_load(
; GFX6-LABEL: local_agent_monotonic_load:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s0
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_read_b32 v0, v0
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: ds_write_b32 v1, v0
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_monotonic_load:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: ds_read_b32 v0, v0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: ds_write_b32 v1, v0
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_monotonic_load:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: ds_read_b32 v0, v0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: ds_write_b32 v1, v0
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_monotonic_load:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
; GFX10-CU-NEXT: ds_read_b32 v0, v0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: ds_write_b32 v1, v0
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_monotonic_load:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: ds_read_b32 v0, v0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: ds_write_b32 v1, v0
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_monotonic_load:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: ds_read_b32 v0, v0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v1, v0
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_monotonic_load:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: ds_read_b32 v0, v0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v1, v0
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %in, i32 addrspace(3)* %out) {
entry:
%val = load atomic i32, i32 addrspace(3)* %in syncscope("agent") monotonic, align 4
store i32 %val, i32 addrspace(3)* %out
ret void
}
define amdgpu_kernel void @local_agent_acquire_load(
; GFX6-LABEL: local_agent_acquire_load:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s0
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_read_b32 v0, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_write_b32 v1, v0
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_acquire_load:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: ds_read_b32 v0, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: ds_write_b32 v1, v0
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_acquire_load:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: ds_read_b32 v0, v0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: ds_write_b32 v1, v0
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_acquire_load:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
; GFX10-CU-NEXT: ds_read_b32 v0, v0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: ds_write_b32 v1, v0
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_acquire_load:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: ds_read_b32 v0, v0
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: ds_write_b32 v1, v0
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_acquire_load:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: ds_read_b32 v0, v0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v1, v0
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_acquire_load:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: ds_read_b32 v0, v0
; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v1, v0
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %in, i32 addrspace(3)* %out) {
entry:
%val = load atomic i32, i32 addrspace(3)* %in syncscope("agent") acquire, align 4
store i32 %val, i32 addrspace(3)* %out
ret void
}
define amdgpu_kernel void @local_agent_seq_cst_load(
; GFX6-LABEL: local_agent_seq_cst_load:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s0
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_read_b32 v0, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_write_b32 v1, v0
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_seq_cst_load:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_read_b32 v0, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: ds_write_b32 v1, v0
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_seq_cst_load:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: ds_read_b32 v0, v0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: ds_write_b32 v1, v0
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_seq_cst_load:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_read_b32 v0, v0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: ds_write_b32 v1, v0
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_seq_cst_load:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_read_b32 v0, v0
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: ds_write_b32 v1, v0
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_seq_cst_load:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_read_b32 v0, v0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v1, v0
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_seq_cst_load:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_read_b32 v0, v0
; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v1, v0
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %in, i32 addrspace(3)* %out) {
entry:
%val = load atomic i32, i32 addrspace(3)* %in syncscope("agent") seq_cst, align 4
store i32 %val, i32 addrspace(3)* %out
ret void
}
define amdgpu_kernel void @local_agent_unordered_store(
; GFX6-LABEL: local_agent_unordered_store:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: v_mov_b32_e32 v0, s1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_unordered_store:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s1
; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_unordered_store:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s1
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s0
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_unordered_store:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s1
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s0
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_unordered_store:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s1
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_unordered_store:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s1
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s0
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_unordered_store:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s1
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s0
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 %in, i32 addrspace(3)* %out) {
entry:
store atomic i32 %in, i32 addrspace(3)* %out syncscope("agent") unordered, align 4
ret void
}
define amdgpu_kernel void @local_agent_monotonic_store(
; GFX6-LABEL: local_agent_monotonic_store:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: v_mov_b32_e32 v0, s1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_monotonic_store:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s1
; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_monotonic_store:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s1
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s0
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_monotonic_store:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s1
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s0
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_monotonic_store:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s1
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_monotonic_store:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s1
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s0
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_monotonic_store:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s1
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s0
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 %in, i32 addrspace(3)* %out) {
entry:
store atomic i32 %in, i32 addrspace(3)* %out syncscope("agent") monotonic, align 4
ret void
}
define amdgpu_kernel void @local_agent_release_store(
; GFX6-LABEL: local_agent_release_store:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: v_mov_b32_e32 v0, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_release_store:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s1
; GFX7-NEXT: v_mov_b32_e32 v1, s0
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_release_store:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s1
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s0
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_release_store:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s1
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s0
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_release_store:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s1
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_release_store:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s1
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_release_store:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s1
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s0
; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 %in, i32 addrspace(3)* %out) {
entry:
store atomic i32 %in, i32 addrspace(3)* %out syncscope("agent") release, align 4
ret void
}
define amdgpu_kernel void @local_agent_seq_cst_store(
; GFX6-LABEL: local_agent_seq_cst_store:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: v_mov_b32_e32 v0, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_seq_cst_store:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s1
; GFX7-NEXT: v_mov_b32_e32 v1, s0
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_seq_cst_store:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s1
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s0
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_seq_cst_store:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s1
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s0
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_seq_cst_store:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s1
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_seq_cst_store:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s1
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_seq_cst_store:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s1
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s0
; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 %in, i32 addrspace(3)* %out) {
entry:
store atomic i32 %in, i32 addrspace(3)* %out syncscope("agent") seq_cst, align 4
ret void
}
define amdgpu_kernel void @local_agent_monotonic_atomicrmw(
; GFX6-LABEL: local_agent_monotonic_atomicrmw:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_monotonic_atomicrmw:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_monotonic_atomicrmw:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_monotonic_atomicrmw:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_monotonic_atomicrmw:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_monotonic_atomicrmw:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_monotonic_atomicrmw:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-TGSPLIT-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in) {
entry:
%val = atomicrmw volatile xchg i32 addrspace(3)* %out, i32 %in syncscope("agent") monotonic
ret void
}
define amdgpu_kernel void @local_agent_acquire_atomicrmw(
; GFX6-LABEL: local_agent_acquire_atomicrmw:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_acquire_atomicrmw:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_acquire_atomicrmw:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
[AMDGPU] Correct rmw atomics s_waitcnt generation The AMD GPU SIMemoryLegalizer was using the ordering address space rather than the instruction address space when determining the s_waitcnt to generate to ensure that a read-modify-write atomic has completed. This resulted in additional unnecessary counters being waited on. Differential Revision: https://reviews.llvm.org/D96743
2021-02-16 11:22:34 +08:00
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_acquire_atomicrmw:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_acquire_atomicrmw:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_acquire_atomicrmw:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_acquire_atomicrmw:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-TGSPLIT-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in) {
entry:
%val = atomicrmw volatile xchg i32 addrspace(3)* %out, i32 %in syncscope("agent") acquire
ret void
}
define amdgpu_kernel void @local_agent_release_atomicrmw(
; GFX6-LABEL: local_agent_release_atomicrmw:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_release_atomicrmw:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_release_atomicrmw:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_release_atomicrmw:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_release_atomicrmw:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_release_atomicrmw:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_release_atomicrmw:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in) {
entry:
%val = atomicrmw volatile xchg i32 addrspace(3)* %out, i32 %in syncscope("agent") release
ret void
}
define amdgpu_kernel void @local_agent_acq_rel_atomicrmw(
; GFX6-LABEL: local_agent_acq_rel_atomicrmw:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_acq_rel_atomicrmw:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_acq_rel_atomicrmw:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
[AMDGPU] Correct rmw atomics s_waitcnt generation The AMD GPU SIMemoryLegalizer was using the ordering address space rather than the instruction address space when determining the s_waitcnt to generate to ensure that a read-modify-write atomic has completed. This resulted in additional unnecessary counters being waited on. Differential Revision: https://reviews.llvm.org/D96743
2021-02-16 11:22:34 +08:00
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_acq_rel_atomicrmw:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_acq_rel_atomicrmw:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_acq_rel_atomicrmw:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_acq_rel_atomicrmw:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in) {
entry:
%val = atomicrmw volatile xchg i32 addrspace(3)* %out, i32 %in syncscope("agent") acq_rel
ret void
}
define amdgpu_kernel void @local_agent_seq_cst_atomicrmw(
; GFX6-LABEL: local_agent_seq_cst_atomicrmw:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_seq_cst_atomicrmw:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_seq_cst_atomicrmw:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
[AMDGPU] Correct rmw atomics s_waitcnt generation The AMD GPU SIMemoryLegalizer was using the ordering address space rather than the instruction address space when determining the s_waitcnt to generate to ensure that a read-modify-write atomic has completed. This resulted in additional unnecessary counters being waited on. Differential Revision: https://reviews.llvm.org/D96743
2021-02-16 11:22:34 +08:00
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_seq_cst_atomicrmw:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_seq_cst_atomicrmw:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_seq_cst_atomicrmw:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_seq_cst_atomicrmw:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in) {
entry:
%val = atomicrmw volatile xchg i32 addrspace(3)* %out, i32 %in syncscope("agent") seq_cst
ret void
}
define amdgpu_kernel void @local_agent_acquire_ret_atomicrmw(
; GFX6-LABEL: local_agent_acquire_ret_atomicrmw:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_acquire_ret_atomicrmw:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_acquire_ret_atomicrmw:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
[AMDGPU] Correct rmw atomics s_waitcnt generation The AMD GPU SIMemoryLegalizer was using the ordering address space rather than the instruction address space when determining the s_waitcnt to generate to ensure that a read-modify-write atomic has completed. This resulted in additional unnecessary counters being waited on. Differential Revision: https://reviews.llvm.org/D96743
2021-02-16 11:22:34 +08:00
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_acquire_ret_atomicrmw:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_acquire_ret_atomicrmw:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_acquire_ret_atomicrmw:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_acquire_ret_atomicrmw:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-TGSPLIT-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in) {
entry:
%val = atomicrmw volatile xchg i32 addrspace(3)* %out, i32 %in syncscope("agent") acquire
store i32 %val, i32 addrspace(3)* %out, align 4
ret void
}
define amdgpu_kernel void @local_agent_acq_rel_ret_atomicrmw(
; GFX6-LABEL: local_agent_acq_rel_ret_atomicrmw:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_acq_rel_ret_atomicrmw:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_acq_rel_ret_atomicrmw:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
[AMDGPU] Correct rmw atomics s_waitcnt generation The AMD GPU SIMemoryLegalizer was using the ordering address space rather than the instruction address space when determining the s_waitcnt to generate to ensure that a read-modify-write atomic has completed. This resulted in additional unnecessary counters being waited on. Differential Revision: https://reviews.llvm.org/D96743
2021-02-16 11:22:34 +08:00
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_acq_rel_ret_atomicrmw:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_acq_rel_ret_atomicrmw:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_acq_rel_ret_atomicrmw:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_acq_rel_ret_atomicrmw:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in) {
entry:
%val = atomicrmw volatile xchg i32 addrspace(3)* %out, i32 %in syncscope("agent") acq_rel
store i32 %val, i32 addrspace(3)* %out, align 4
ret void
}
define amdgpu_kernel void @local_agent_seq_cst_ret_atomicrmw(
; GFX6-LABEL: local_agent_seq_cst_ret_atomicrmw:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_seq_cst_ret_atomicrmw:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_seq_cst_ret_atomicrmw:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
[AMDGPU] Correct rmw atomics s_waitcnt generation The AMD GPU SIMemoryLegalizer was using the ordering address space rather than the instruction address space when determining the s_waitcnt to generate to ensure that a read-modify-write atomic has completed. This resulted in additional unnecessary counters being waited on. Differential Revision: https://reviews.llvm.org/D96743
2021-02-16 11:22:34 +08:00
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_seq_cst_ret_atomicrmw:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_seq_cst_ret_atomicrmw:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_seq_cst_ret_atomicrmw:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_seq_cst_ret_atomicrmw:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in) {
entry:
%val = atomicrmw volatile xchg i32 addrspace(3)* %out, i32 %in syncscope("agent") seq_cst
store i32 %val, i32 addrspace(3)* %out, align 4
ret void
}
define amdgpu_kernel void @local_agent_monotonic_monotonic_cmpxchg(
; GFX6-LABEL: local_agent_monotonic_monotonic_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_monotonic_monotonic_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_monotonic_monotonic_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_monotonic_monotonic_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_monotonic_monotonic_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
; SKIP-CACHE-INV-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_monotonic_monotonic_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_monotonic_monotonic_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent") monotonic monotonic
ret void
}
define amdgpu_kernel void @local_agent_acquire_monotonic_cmpxchg(
; GFX6-LABEL: local_agent_acquire_monotonic_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_acquire_monotonic_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_acquire_monotonic_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_acquire_monotonic_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_acquire_monotonic_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
; SKIP-CACHE-INV-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_acquire_monotonic_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_acquire_monotonic_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent") acquire monotonic
ret void
}
define amdgpu_kernel void @local_agent_release_monotonic_cmpxchg(
; GFX6-LABEL: local_agent_release_monotonic_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_release_monotonic_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_release_monotonic_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_release_monotonic_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_release_monotonic_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_release_monotonic_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_release_monotonic_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent") release monotonic
ret void
}
define amdgpu_kernel void @local_agent_acq_rel_monotonic_cmpxchg(
; GFX6-LABEL: local_agent_acq_rel_monotonic_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_acq_rel_monotonic_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_acq_rel_monotonic_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_acq_rel_monotonic_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_acq_rel_monotonic_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_acq_rel_monotonic_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_acq_rel_monotonic_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent") acq_rel monotonic
ret void
}
define amdgpu_kernel void @local_agent_seq_cst_monotonic_cmpxchg(
; GFX6-LABEL: local_agent_seq_cst_monotonic_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_seq_cst_monotonic_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_seq_cst_monotonic_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_seq_cst_monotonic_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_seq_cst_monotonic_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_seq_cst_monotonic_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_seq_cst_monotonic_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent") seq_cst monotonic
ret void
}
define amdgpu_kernel void @local_agent_acquire_acquire_cmpxchg(
; GFX6-LABEL: local_agent_acquire_acquire_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_acquire_acquire_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_acquire_acquire_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_acquire_acquire_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_acquire_acquire_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
; SKIP-CACHE-INV-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_acquire_acquire_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_acquire_acquire_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent") acquire acquire
ret void
}
define amdgpu_kernel void @local_agent_release_acquire_cmpxchg(
; GFX6-LABEL: local_agent_release_acquire_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_release_acquire_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_release_acquire_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_release_acquire_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_release_acquire_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_release_acquire_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_release_acquire_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent") release acquire
ret void
}
define amdgpu_kernel void @local_agent_acq_rel_acquire_cmpxchg(
; GFX6-LABEL: local_agent_acq_rel_acquire_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_acq_rel_acquire_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_acq_rel_acquire_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_acq_rel_acquire_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_acq_rel_acquire_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_acq_rel_acquire_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_acq_rel_acquire_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent") acq_rel acquire
ret void
}
define amdgpu_kernel void @local_agent_seq_cst_acquire_cmpxchg(
; GFX6-LABEL: local_agent_seq_cst_acquire_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_seq_cst_acquire_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_seq_cst_acquire_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_seq_cst_acquire_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_seq_cst_acquire_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_seq_cst_acquire_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_seq_cst_acquire_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent") seq_cst acquire
ret void
}
define amdgpu_kernel void @local_agent_seq_cst_seq_cst_cmpxchg(
; GFX6-LABEL: local_agent_seq_cst_seq_cst_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_seq_cst_seq_cst_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_seq_cst_seq_cst_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_seq_cst_seq_cst_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_seq_cst_seq_cst_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_seq_cst_seq_cst_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_seq_cst_seq_cst_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent") seq_cst seq_cst
ret void
}
define amdgpu_kernel void @local_agent_acquire_monotonic_ret_cmpxchg(
; GFX6-LABEL: local_agent_acquire_monotonic_ret_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_acquire_monotonic_ret_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_acquire_monotonic_ret_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Correct rmw atomics s_waitcnt generation The AMD GPU SIMemoryLegalizer was using the ordering address space rather than the instruction address space when determining the s_waitcnt to generate to ensure that a read-modify-write atomic has completed. This resulted in additional unnecessary counters being waited on. Differential Revision: https://reviews.llvm.org/D96743
2021-02-16 11:22:34 +08:00
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_acquire_monotonic_ret_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_acquire_monotonic_ret_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
; SKIP-CACHE-INV-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_acquire_monotonic_ret_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_acquire_monotonic_ret_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent") acquire monotonic
%val0 = extractvalue { i32, i1 } %val, 0
store i32 %val0, i32 addrspace(3)* %out, align 4
ret void
}
define amdgpu_kernel void @local_agent_acq_rel_monotonic_ret_cmpxchg(
; GFX6-LABEL: local_agent_acq_rel_monotonic_ret_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_acq_rel_monotonic_ret_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_acq_rel_monotonic_ret_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Correct rmw atomics s_waitcnt generation The AMD GPU SIMemoryLegalizer was using the ordering address space rather than the instruction address space when determining the s_waitcnt to generate to ensure that a read-modify-write atomic has completed. This resulted in additional unnecessary counters being waited on. Differential Revision: https://reviews.llvm.org/D96743
2021-02-16 11:22:34 +08:00
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_acq_rel_monotonic_ret_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_acq_rel_monotonic_ret_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_acq_rel_monotonic_ret_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_acq_rel_monotonic_ret_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent") acq_rel monotonic
%val0 = extractvalue { i32, i1 } %val, 0
store i32 %val0, i32 addrspace(3)* %out, align 4
ret void
}
define amdgpu_kernel void @local_agent_seq_cst_monotonic_ret_cmpxchg(
; GFX6-LABEL: local_agent_seq_cst_monotonic_ret_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_seq_cst_monotonic_ret_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_seq_cst_monotonic_ret_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Correct rmw atomics s_waitcnt generation The AMD GPU SIMemoryLegalizer was using the ordering address space rather than the instruction address space when determining the s_waitcnt to generate to ensure that a read-modify-write atomic has completed. This resulted in additional unnecessary counters being waited on. Differential Revision: https://reviews.llvm.org/D96743
2021-02-16 11:22:34 +08:00
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_seq_cst_monotonic_ret_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_seq_cst_monotonic_ret_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_seq_cst_monotonic_ret_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_seq_cst_monotonic_ret_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent") seq_cst monotonic
%val0 = extractvalue { i32, i1 } %val, 0
store i32 %val0, i32 addrspace(3)* %out, align 4
ret void
}
define amdgpu_kernel void @local_agent_acquire_acquire_ret_cmpxchg(
; GFX6-LABEL: local_agent_acquire_acquire_ret_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_acquire_acquire_ret_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_acquire_acquire_ret_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Correct rmw atomics s_waitcnt generation The AMD GPU SIMemoryLegalizer was using the ordering address space rather than the instruction address space when determining the s_waitcnt to generate to ensure that a read-modify-write atomic has completed. This resulted in additional unnecessary counters being waited on. Differential Revision: https://reviews.llvm.org/D96743
2021-02-16 11:22:34 +08:00
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_acquire_acquire_ret_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_acquire_acquire_ret_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
; SKIP-CACHE-INV-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_acquire_acquire_ret_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_acquire_acquire_ret_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent") acquire acquire
%val0 = extractvalue { i32, i1 } %val, 0
store i32 %val0, i32 addrspace(3)* %out, align 4
ret void
}
define amdgpu_kernel void @local_agent_release_acquire_ret_cmpxchg(
; GFX6-LABEL: local_agent_release_acquire_ret_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_release_acquire_ret_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_release_acquire_ret_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Correct rmw atomics s_waitcnt generation The AMD GPU SIMemoryLegalizer was using the ordering address space rather than the instruction address space when determining the s_waitcnt to generate to ensure that a read-modify-write atomic has completed. This resulted in additional unnecessary counters being waited on. Differential Revision: https://reviews.llvm.org/D96743
2021-02-16 11:22:34 +08:00
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_release_acquire_ret_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_release_acquire_ret_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_release_acquire_ret_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_release_acquire_ret_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent") release acquire
%val0 = extractvalue { i32, i1 } %val, 0
store i32 %val0, i32 addrspace(3)* %out, align 4
ret void
}
define amdgpu_kernel void @local_agent_acq_rel_acquire_ret_cmpxchg(
; GFX6-LABEL: local_agent_acq_rel_acquire_ret_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_acq_rel_acquire_ret_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_acq_rel_acquire_ret_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Correct rmw atomics s_waitcnt generation The AMD GPU SIMemoryLegalizer was using the ordering address space rather than the instruction address space when determining the s_waitcnt to generate to ensure that a read-modify-write atomic has completed. This resulted in additional unnecessary counters being waited on. Differential Revision: https://reviews.llvm.org/D96743
2021-02-16 11:22:34 +08:00
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_acq_rel_acquire_ret_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_acq_rel_acquire_ret_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_acq_rel_acquire_ret_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_acq_rel_acquire_ret_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent") acq_rel acquire
%val0 = extractvalue { i32, i1 } %val, 0
store i32 %val0, i32 addrspace(3)* %out, align 4
ret void
}
define amdgpu_kernel void @local_agent_seq_cst_acquire_ret_cmpxchg(
; GFX6-LABEL: local_agent_seq_cst_acquire_ret_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_seq_cst_acquire_ret_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_seq_cst_acquire_ret_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Correct rmw atomics s_waitcnt generation The AMD GPU SIMemoryLegalizer was using the ordering address space rather than the instruction address space when determining the s_waitcnt to generate to ensure that a read-modify-write atomic has completed. This resulted in additional unnecessary counters being waited on. Differential Revision: https://reviews.llvm.org/D96743
2021-02-16 11:22:34 +08:00
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_seq_cst_acquire_ret_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_seq_cst_acquire_ret_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_seq_cst_acquire_ret_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_seq_cst_acquire_ret_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent") seq_cst acquire
%val0 = extractvalue { i32, i1 } %val, 0
store i32 %val0, i32 addrspace(3)* %out, align 4
ret void
}
define amdgpu_kernel void @local_agent_seq_cst_seq_cst_ret_cmpxchg(
; GFX6-LABEL: local_agent_seq_cst_seq_cst_ret_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_seq_cst_seq_cst_ret_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_seq_cst_seq_cst_ret_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Correct rmw atomics s_waitcnt generation The AMD GPU SIMemoryLegalizer was using the ordering address space rather than the instruction address space when determining the s_waitcnt to generate to ensure that a read-modify-write atomic has completed. This resulted in additional unnecessary counters being waited on. Differential Revision: https://reviews.llvm.org/D96743
2021-02-16 11:22:34 +08:00
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_seq_cst_seq_cst_ret_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_seq_cst_seq_cst_ret_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
[AMDGPU] Limit memory scope for scratch, LDS and GDS Changes for AMD GPU SIMemoryLegalizer: - Limit the memory scope to maximum supported by the scratch, LDS and GDS address spaces. - Improve assertion checking. - Correct toSIAtomicScope argument name. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96643
2021-02-13 16:43:48 +08:00
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_seq_cst_seq_cst_ret_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_seq_cst_seq_cst_ret_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent") seq_cst seq_cst
%val0 = extractvalue { i32, i1 } %val, 0
store i32 %val0, i32 addrspace(3)* %out, align 4
ret void
}
define amdgpu_kernel void @local_agent_one_as_unordered_load(
; GFX6-LABEL: local_agent_one_as_unordered_load:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s0
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_read_b32 v0, v0
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: ds_write_b32 v1, v0
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_unordered_load:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: ds_read_b32 v0, v0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: ds_write_b32 v1, v0
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_unordered_load:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: ds_read_b32 v0, v0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: ds_write_b32 v1, v0
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_unordered_load:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
; GFX10-CU-NEXT: ds_read_b32 v0, v0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: ds_write_b32 v1, v0
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_unordered_load:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: ds_read_b32 v0, v0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: ds_write_b32 v1, v0
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_unordered_load:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: ds_read_b32 v0, v0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v1, v0
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_unordered_load:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: ds_read_b32 v0, v0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v1, v0
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %in, i32 addrspace(3)* %out) {
entry:
%val = load atomic i32, i32 addrspace(3)* %in syncscope("agent-one-as") unordered, align 4
store i32 %val, i32 addrspace(3)* %out
ret void
}
define amdgpu_kernel void @local_agent_one_as_monotonic_load(
; GFX6-LABEL: local_agent_one_as_monotonic_load:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s0
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_read_b32 v0, v0
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: ds_write_b32 v1, v0
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_monotonic_load:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: ds_read_b32 v0, v0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: ds_write_b32 v1, v0
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_monotonic_load:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: ds_read_b32 v0, v0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: ds_write_b32 v1, v0
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_monotonic_load:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
; GFX10-CU-NEXT: ds_read_b32 v0, v0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: ds_write_b32 v1, v0
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_monotonic_load:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: ds_read_b32 v0, v0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: ds_write_b32 v1, v0
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_monotonic_load:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: ds_read_b32 v0, v0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v1, v0
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_monotonic_load:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: ds_read_b32 v0, v0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v1, v0
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %in, i32 addrspace(3)* %out) {
entry:
%val = load atomic i32, i32 addrspace(3)* %in syncscope("agent-one-as") monotonic, align 4
store i32 %val, i32 addrspace(3)* %out
ret void
}
define amdgpu_kernel void @local_agent_one_as_acquire_load(
; GFX6-LABEL: local_agent_one_as_acquire_load:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s0
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_read_b32 v0, v0
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: ds_write_b32 v1, v0
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_acquire_load:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: ds_read_b32 v0, v0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: ds_write_b32 v1, v0
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_acquire_load:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: ds_read_b32 v0, v0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: ds_write_b32 v1, v0
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_acquire_load:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
; GFX10-CU-NEXT: ds_read_b32 v0, v0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: ds_write_b32 v1, v0
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_acquire_load:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: ds_read_b32 v0, v0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: ds_write_b32 v1, v0
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_acquire_load:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: ds_read_b32 v0, v0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v1, v0
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_acquire_load:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: ds_read_b32 v0, v0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v1, v0
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %in, i32 addrspace(3)* %out) {
entry:
%val = load atomic i32, i32 addrspace(3)* %in syncscope("agent-one-as") acquire, align 4
store i32 %val, i32 addrspace(3)* %out
ret void
}
define amdgpu_kernel void @local_agent_one_as_seq_cst_load(
; GFX6-LABEL: local_agent_one_as_seq_cst_load:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s0
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_read_b32 v0, v0
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: ds_write_b32 v1, v0
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_seq_cst_load:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: ds_read_b32 v0, v0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: ds_write_b32 v1, v0
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_seq_cst_load:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: ds_read_b32 v0, v0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: ds_write_b32 v1, v0
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_seq_cst_load:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
; GFX10-CU-NEXT: ds_read_b32 v0, v0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: ds_write_b32 v1, v0
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_seq_cst_load:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: ds_read_b32 v0, v0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: ds_write_b32 v1, v0
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_seq_cst_load:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: ds_read_b32 v0, v0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v1, v0
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_seq_cst_load:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: ds_read_b32 v0, v0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v1, v0
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %in, i32 addrspace(3)* %out) {
entry:
%val = load atomic i32, i32 addrspace(3)* %in syncscope("agent-one-as") seq_cst, align 4
store i32 %val, i32 addrspace(3)* %out
ret void
}
define amdgpu_kernel void @local_agent_one_as_unordered_store(
; GFX6-LABEL: local_agent_one_as_unordered_store:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: v_mov_b32_e32 v0, s1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_unordered_store:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s1
; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_unordered_store:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s1
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s0
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_unordered_store:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s1
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s0
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_unordered_store:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s1
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_unordered_store:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s1
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s0
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_unordered_store:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s1
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s0
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 %in, i32 addrspace(3)* %out) {
entry:
store atomic i32 %in, i32 addrspace(3)* %out syncscope("agent-one-as") unordered, align 4
ret void
}
define amdgpu_kernel void @local_agent_one_as_monotonic_store(
; GFX6-LABEL: local_agent_one_as_monotonic_store:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: v_mov_b32_e32 v0, s1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_monotonic_store:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s1
; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_monotonic_store:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s1
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s0
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_monotonic_store:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s1
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s0
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_monotonic_store:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s1
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_monotonic_store:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s1
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s0
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_monotonic_store:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s1
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s0
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 %in, i32 addrspace(3)* %out) {
entry:
store atomic i32 %in, i32 addrspace(3)* %out syncscope("agent-one-as") monotonic, align 4
ret void
}
define amdgpu_kernel void @local_agent_one_as_release_store(
; GFX6-LABEL: local_agent_one_as_release_store:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: v_mov_b32_e32 v0, s1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_release_store:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s1
; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_release_store:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s1
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s0
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_release_store:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s1
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s0
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_release_store:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s1
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_release_store:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s1
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s0
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_release_store:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s1
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s0
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 %in, i32 addrspace(3)* %out) {
entry:
store atomic i32 %in, i32 addrspace(3)* %out syncscope("agent-one-as") release, align 4
ret void
}
define amdgpu_kernel void @local_agent_one_as_seq_cst_store(
; GFX6-LABEL: local_agent_one_as_seq_cst_store:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: v_mov_b32_e32 v0, s1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_seq_cst_store:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s1
; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_seq_cst_store:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s1
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s0
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_seq_cst_store:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s1
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s0
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_seq_cst_store:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s1
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_seq_cst_store:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s1
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s0
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_seq_cst_store:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s1
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s0
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 %in, i32 addrspace(3)* %out) {
entry:
store atomic i32 %in, i32 addrspace(3)* %out syncscope("agent-one-as") seq_cst, align 4
ret void
}
define amdgpu_kernel void @local_agent_one_as_monotonic_atomicrmw(
; GFX6-LABEL: local_agent_one_as_monotonic_atomicrmw:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_monotonic_atomicrmw:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_monotonic_atomicrmw:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_monotonic_atomicrmw:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_monotonic_atomicrmw:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_monotonic_atomicrmw:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_monotonic_atomicrmw:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-TGSPLIT-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in) {
entry:
%val = atomicrmw volatile xchg i32 addrspace(3)* %out, i32 %in syncscope("agent-one-as") monotonic
ret void
}
define amdgpu_kernel void @local_agent_one_as_acquire_atomicrmw(
; GFX6-LABEL: local_agent_one_as_acquire_atomicrmw:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_acquire_atomicrmw:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_acquire_atomicrmw:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_acquire_atomicrmw:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_acquire_atomicrmw:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_acquire_atomicrmw:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_acquire_atomicrmw:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-TGSPLIT-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in) {
entry:
%val = atomicrmw volatile xchg i32 addrspace(3)* %out, i32 %in syncscope("agent-one-as") acquire
ret void
}
define amdgpu_kernel void @local_agent_one_as_release_atomicrmw(
; GFX6-LABEL: local_agent_one_as_release_atomicrmw:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_release_atomicrmw:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_release_atomicrmw:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_release_atomicrmw:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_release_atomicrmw:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_release_atomicrmw:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_release_atomicrmw:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-TGSPLIT-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in) {
entry:
%val = atomicrmw volatile xchg i32 addrspace(3)* %out, i32 %in syncscope("agent-one-as") release
ret void
}
define amdgpu_kernel void @local_agent_one_as_acq_rel_atomicrmw(
; GFX6-LABEL: local_agent_one_as_acq_rel_atomicrmw:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_acq_rel_atomicrmw:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_acq_rel_atomicrmw:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_acq_rel_atomicrmw:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_acq_rel_atomicrmw:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_acq_rel_atomicrmw:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_acq_rel_atomicrmw:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-TGSPLIT-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in) {
entry:
%val = atomicrmw volatile xchg i32 addrspace(3)* %out, i32 %in syncscope("agent-one-as") acq_rel
ret void
}
define amdgpu_kernel void @local_agent_one_as_seq_cst_atomicrmw(
; GFX6-LABEL: local_agent_one_as_seq_cst_atomicrmw:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_seq_cst_atomicrmw:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_seq_cst_atomicrmw:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_seq_cst_atomicrmw:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_seq_cst_atomicrmw:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_seq_cst_atomicrmw:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_seq_cst_atomicrmw:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-TGSPLIT-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in) {
entry:
%val = atomicrmw volatile xchg i32 addrspace(3)* %out, i32 %in syncscope("agent-one-as") seq_cst
ret void
}
define amdgpu_kernel void @local_agent_one_as_acquire_ret_atomicrmw(
; GFX6-LABEL: local_agent_one_as_acquire_ret_atomicrmw:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_acquire_ret_atomicrmw:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_acquire_ret_atomicrmw:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_acquire_ret_atomicrmw:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_acquire_ret_atomicrmw:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_acquire_ret_atomicrmw:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_acquire_ret_atomicrmw:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-TGSPLIT-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in) {
entry:
%val = atomicrmw volatile xchg i32 addrspace(3)* %out, i32 %in syncscope("agent-one-as") acquire
store i32 %val, i32 addrspace(3)* %out, align 4
ret void
}
define amdgpu_kernel void @local_agent_one_as_acq_rel_ret_atomicrmw(
; GFX6-LABEL: local_agent_one_as_acq_rel_ret_atomicrmw:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_acq_rel_ret_atomicrmw:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_acq_rel_ret_atomicrmw:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_acq_rel_ret_atomicrmw:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_acq_rel_ret_atomicrmw:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_acq_rel_ret_atomicrmw:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_acq_rel_ret_atomicrmw:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-TGSPLIT-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in) {
entry:
%val = atomicrmw volatile xchg i32 addrspace(3)* %out, i32 %in syncscope("agent-one-as") acq_rel
store i32 %val, i32 addrspace(3)* %out, align 4
ret void
}
define amdgpu_kernel void @local_agent_one_as_seq_cst_ret_atomicrmw(
; GFX6-LABEL: local_agent_one_as_seq_cst_ret_atomicrmw:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX6-NEXT: s_load_dword s1, s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: v_mov_b32_e32 v1, s1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_seq_cst_ret_atomicrmw:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_seq_cst_ret_atomicrmw:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_seq_cst_ret_atomicrmw:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_seq_cst_ret_atomicrmw:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_seq_cst_ret_atomicrmw:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_seq_cst_ret_atomicrmw:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-TGSPLIT-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in) {
entry:
%val = atomicrmw volatile xchg i32 addrspace(3)* %out, i32 %in syncscope("agent-one-as") seq_cst
store i32 %val, i32 addrspace(3)* %out, align 4
ret void
}
define amdgpu_kernel void @local_agent_one_as_monotonic_monotonic_cmpxchg(
; GFX6-LABEL: local_agent_one_as_monotonic_monotonic_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_monotonic_monotonic_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_monotonic_monotonic_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_monotonic_monotonic_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_monotonic_monotonic_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
; SKIP-CACHE-INV-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_monotonic_monotonic_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_monotonic_monotonic_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent-one-as") monotonic monotonic
ret void
}
define amdgpu_kernel void @local_agent_one_as_acquire_monotonic_cmpxchg(
; GFX6-LABEL: local_agent_one_as_acquire_monotonic_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_acquire_monotonic_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_acquire_monotonic_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_acquire_monotonic_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_acquire_monotonic_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
; SKIP-CACHE-INV-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_acquire_monotonic_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_acquire_monotonic_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent-one-as") acquire monotonic
ret void
}
define amdgpu_kernel void @local_agent_one_as_release_monotonic_cmpxchg(
; GFX6-LABEL: local_agent_one_as_release_monotonic_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_release_monotonic_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_release_monotonic_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_release_monotonic_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_release_monotonic_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
; SKIP-CACHE-INV-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_release_monotonic_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_release_monotonic_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent-one-as") release monotonic
ret void
}
define amdgpu_kernel void @local_agent_one_as_acq_rel_monotonic_cmpxchg(
; GFX6-LABEL: local_agent_one_as_acq_rel_monotonic_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_acq_rel_monotonic_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_acq_rel_monotonic_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_acq_rel_monotonic_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_acq_rel_monotonic_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
; SKIP-CACHE-INV-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_acq_rel_monotonic_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_acq_rel_monotonic_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent-one-as") acq_rel monotonic
ret void
}
define amdgpu_kernel void @local_agent_one_as_seq_cst_monotonic_cmpxchg(
; GFX6-LABEL: local_agent_one_as_seq_cst_monotonic_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_seq_cst_monotonic_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_seq_cst_monotonic_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_seq_cst_monotonic_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_seq_cst_monotonic_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
; SKIP-CACHE-INV-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_seq_cst_monotonic_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_seq_cst_monotonic_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent-one-as") seq_cst monotonic
ret void
}
define amdgpu_kernel void @local_agent_one_as_acquire_acquire_cmpxchg(
; GFX6-LABEL: local_agent_one_as_acquire_acquire_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_acquire_acquire_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_acquire_acquire_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_acquire_acquire_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_acquire_acquire_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
; SKIP-CACHE-INV-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_acquire_acquire_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_acquire_acquire_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent-one-as") acquire acquire
ret void
}
define amdgpu_kernel void @local_agent_one_as_release_acquire_cmpxchg(
; GFX6-LABEL: local_agent_one_as_release_acquire_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_release_acquire_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_release_acquire_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_release_acquire_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_release_acquire_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
; SKIP-CACHE-INV-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_release_acquire_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_release_acquire_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent-one-as") release acquire
ret void
}
define amdgpu_kernel void @local_agent_one_as_acq_rel_acquire_cmpxchg(
; GFX6-LABEL: local_agent_one_as_acq_rel_acquire_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_acq_rel_acquire_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_acq_rel_acquire_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_acq_rel_acquire_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_acq_rel_acquire_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
; SKIP-CACHE-INV-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_acq_rel_acquire_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_acq_rel_acquire_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent-one-as") acq_rel acquire
ret void
}
define amdgpu_kernel void @local_agent_one_as_seq_cst_acquire_cmpxchg(
; GFX6-LABEL: local_agent_one_as_seq_cst_acquire_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_seq_cst_acquire_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_seq_cst_acquire_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_seq_cst_acquire_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_seq_cst_acquire_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
; SKIP-CACHE-INV-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_seq_cst_acquire_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_seq_cst_acquire_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent-one-as") seq_cst acquire
ret void
}
define amdgpu_kernel void @local_agent_one_as_seq_cst_seq_cst_cmpxchg(
; GFX6-LABEL: local_agent_one_as_seq_cst_seq_cst_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_seq_cst_seq_cst_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_seq_cst_seq_cst_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_seq_cst_seq_cst_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_seq_cst_seq_cst_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
; SKIP-CACHE-INV-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_seq_cst_seq_cst_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_seq_cst_seq_cst_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent-one-as") seq_cst seq_cst
ret void
}
define amdgpu_kernel void @local_agent_one_as_acquire_monotonic_ret_cmpxchg(
; GFX6-LABEL: local_agent_one_as_acquire_monotonic_ret_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_acquire_monotonic_ret_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_acquire_monotonic_ret_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_acquire_monotonic_ret_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_acquire_monotonic_ret_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
; SKIP-CACHE-INV-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_acquire_monotonic_ret_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_acquire_monotonic_ret_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent-one-as") acquire monotonic
%val0 = extractvalue { i32, i1 } %val, 0
store i32 %val0, i32 addrspace(3)* %out, align 4
ret void
}
define amdgpu_kernel void @local_agent_one_as_acq_rel_monotonic_ret_cmpxchg(
; GFX6-LABEL: local_agent_one_as_acq_rel_monotonic_ret_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_acq_rel_monotonic_ret_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_acq_rel_monotonic_ret_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_acq_rel_monotonic_ret_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_acq_rel_monotonic_ret_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
; SKIP-CACHE-INV-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_acq_rel_monotonic_ret_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_acq_rel_monotonic_ret_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent-one-as") acq_rel monotonic
%val0 = extractvalue { i32, i1 } %val, 0
store i32 %val0, i32 addrspace(3)* %out, align 4
ret void
}
define amdgpu_kernel void @local_agent_one_as_seq_cst_monotonic_ret_cmpxchg(
; GFX6-LABEL: local_agent_one_as_seq_cst_monotonic_ret_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_seq_cst_monotonic_ret_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_seq_cst_monotonic_ret_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_seq_cst_monotonic_ret_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_seq_cst_monotonic_ret_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
; SKIP-CACHE-INV-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_seq_cst_monotonic_ret_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_seq_cst_monotonic_ret_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent-one-as") seq_cst monotonic
%val0 = extractvalue { i32, i1 } %val, 0
store i32 %val0, i32 addrspace(3)* %out, align 4
ret void
}
define amdgpu_kernel void @local_agent_one_as_acquire_acquire_ret_cmpxchg(
; GFX6-LABEL: local_agent_one_as_acquire_acquire_ret_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_acquire_acquire_ret_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_acquire_acquire_ret_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_acquire_acquire_ret_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_acquire_acquire_ret_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
; SKIP-CACHE-INV-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_acquire_acquire_ret_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_acquire_acquire_ret_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent-one-as") acquire acquire
%val0 = extractvalue { i32, i1 } %val, 0
store i32 %val0, i32 addrspace(3)* %out, align 4
ret void
}
define amdgpu_kernel void @local_agent_one_as_release_acquire_ret_cmpxchg(
; GFX6-LABEL: local_agent_one_as_release_acquire_ret_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_release_acquire_ret_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_release_acquire_ret_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_release_acquire_ret_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_release_acquire_ret_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
; SKIP-CACHE-INV-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_release_acquire_ret_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_release_acquire_ret_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent-one-as") release acquire
%val0 = extractvalue { i32, i1 } %val, 0
store i32 %val0, i32 addrspace(3)* %out, align 4
ret void
}
define amdgpu_kernel void @local_agent_one_as_acq_rel_acquire_ret_cmpxchg(
; GFX6-LABEL: local_agent_one_as_acq_rel_acquire_ret_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_acq_rel_acquire_ret_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_acq_rel_acquire_ret_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_acq_rel_acquire_ret_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_acq_rel_acquire_ret_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
; SKIP-CACHE-INV-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_acq_rel_acquire_ret_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_acq_rel_acquire_ret_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent-one-as") acq_rel acquire
%val0 = extractvalue { i32, i1 } %val, 0
store i32 %val0, i32 addrspace(3)* %out, align 4
ret void
}
define amdgpu_kernel void @local_agent_one_as_seq_cst_acquire_ret_cmpxchg(
; GFX6-LABEL: local_agent_one_as_seq_cst_acquire_ret_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_seq_cst_acquire_ret_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_seq_cst_acquire_ret_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_seq_cst_acquire_ret_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_seq_cst_acquire_ret_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
; SKIP-CACHE-INV-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_seq_cst_acquire_ret_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_seq_cst_acquire_ret_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent-one-as") seq_cst acquire
%val0 = extractvalue { i32, i1 } %val, 0
store i32 %val0, i32 addrspace(3)* %out, align 4
ret void
}
define amdgpu_kernel void @local_agent_one_as_seq_cst_seq_cst_ret_cmpxchg(
; GFX6-LABEL: local_agent_one_as_seq_cst_seq_cst_ret_cmpxchg:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_agent_one_as_seq_cst_seq_cst_ret_cmpxchg:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_agent_one_as_seq_cst_seq_cst_ret_cmpxchg:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_agent_one_as_seq_cst_seq_cst_ret_cmpxchg:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_agent_one_as_seq_cst_seq_cst_ret_cmpxchg:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s3
; SKIP-CACHE-INV-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-18 05:37:46 +08:00
;
; GFX90A-NOTTGSPLIT-LABEL: local_agent_one_as_seq_cst_seq_cst_ret_cmpxchg:
; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
; GFX90A-NOTTGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-NOTTGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-NOTTGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-NOTTGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NOTTGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
;
; GFX90A-TGSPLIT-LABEL: local_agent_one_as_seq_cst_seq_cst_ret_cmpxchg:
; GFX90A-TGSPLIT: ; %bb.0: ; %entry
; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s2
; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v2, s1
; GFX90A-TGSPLIT-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16
; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-TGSPLIT-NEXT: ds_write_b32 v0, v1
; GFX90A-TGSPLIT-NEXT: s_endpgm
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
i32 addrspace(3)* %out, i32 %in, i32 %old) {
entry:
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 4
%val = cmpxchg volatile i32 addrspace(3)* %gep, i32 %old, i32 %in syncscope("agent-one-as") seq_cst seq_cst
%val0 = extractvalue { i32, i1 } %val, 0
store i32 %val0, i32 addrspace(3)* %out, align 4
ret void
}