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llvm-project/llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll

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AMDGPU: Fix adding extra operands for i128 asm constraints We don't register i128 as a legal type with addRegisterClass, but it appears in the list of legal register types. This inconsistency resulted in the asm constraint lowering trying to use 2 128-bit registers for these operands. This would leave behind a dead def that would waste registers. Regresses GlobalISel tests for i128 load/store, but these aren't very important right now. Ideally these would not depend on the list of register types.
2021-02-03 05:22:32 +08:00
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
AMDGPU: Add even aligned VGPR/AGPR register classes gfx90a operations require even aligned registers, but this was previously achieved by reserving registers inside the full class. Ideally this would be captured in the static instruction definitions for the operands, and we would have different instructions per subtarget. The hackiest part of this is we need to manually reassign AGPR register classes after instruction selection (we get away without this for VGPRs since those types are actually registered for legal types).
2021-02-19 21:57:14 +08:00
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -stop-after=finalize-isel -o - %s | FileCheck -check-prefix=GFX908 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -stop-after=finalize-isel -o - %s | FileCheck -check-prefix=GFX90A %s
AMDGPU: Fix adding extra operands for i128 asm constraints We don't register i128 as a legal type with addRegisterClass, but it appears in the list of legal register types. This inconsistency resulted in the asm constraint lowering trying to use 2 128-bit registers for these operands. This would leave behind a dead def that would waste registers. Regresses GlobalISel tests for i128 load/store, but these aren't very important right now. Ideally these would not depend on the list of register types.
2021-02-03 05:22:32 +08:00
; Make sure we only use one 128-bit register instead of 2 for i128 asm
; constraints
define amdgpu_kernel void @s_input_output_i128() {
AMDGPU: Add even aligned VGPR/AGPR register classes gfx90a operations require even aligned registers, but this was previously achieved by reserving registers inside the full class. Ideally this would be captured in the static instruction definitions for the operands, and we would have different instructions per subtarget. The hackiest part of this is we need to manually reassign AGPR register classes after instruction selection (we get away without this for VGPRs since those types are actually registered for legal types).
2021-02-19 21:57:14 +08:00
; GFX908-LABEL: name: s_input_output_i128
; GFX908: bb.0 (%ir-block.0):
; GFX908: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4784138 /* regdef:SGPR_128 */, def %4
; GFX908: [[COPY:%[0-9]+]]:sgpr_128 = COPY %4
; GFX908: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 4784137 /* reguse:SGPR_128 */, [[COPY]]
; GFX908: S_ENDPGM 0
; GFX90A-LABEL: name: s_input_output_i128
; GFX90A: bb.0 (%ir-block.0):
; GFX90A: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4784138 /* regdef:SGPR_128 */, def %4
; GFX90A: [[COPY:%[0-9]+]]:sgpr_128 = COPY %4
; GFX90A: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 4784137 /* reguse:SGPR_128 */, [[COPY]]
; GFX90A: S_ENDPGM 0
AMDGPU: Fix adding extra operands for i128 asm constraints We don't register i128 as a legal type with addRegisterClass, but it appears in the list of legal register types. This inconsistency resulted in the asm constraint lowering trying to use 2 128-bit registers for these operands. This would leave behind a dead def that would waste registers. Regresses GlobalISel tests for i128 load/store, but these aren't very important right now. Ideally these would not depend on the list of register types.
2021-02-03 05:22:32 +08:00
%val = tail call i128 asm sideeffect "; def $0", "=s"()
call void asm sideeffect "; use $0", "s"(i128 %val)
ret void
}
define amdgpu_kernel void @v_input_output_i128() {
AMDGPU: Add even aligned VGPR/AGPR register classes gfx90a operations require even aligned registers, but this was previously achieved by reserving registers inside the full class. Ideally this would be captured in the static instruction definitions for the operands, and we would have different instructions per subtarget. The hackiest part of this is we need to manually reassign AGPR register classes after instruction selection (we get away without this for VGPRs since those types are actually registered for legal types).
2021-02-19 21:57:14 +08:00
; GFX908-LABEL: name: v_input_output_i128
; GFX908: bb.0 (%ir-block.0):
; GFX908: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4390922 /* regdef:VReg_128 */, def %4
; GFX908: [[COPY:%[0-9]+]]:vreg_128 = COPY %4
; GFX908: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 4390921 /* reguse:VReg_128 */, [[COPY]]
; GFX908: S_ENDPGM 0
; GFX90A-LABEL: name: v_input_output_i128
; GFX90A: bb.0 (%ir-block.0):
; GFX90A: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4521994 /* regdef:VReg_128_Align2 */, def %4
; GFX90A: [[COPY:%[0-9]+]]:vreg_128_align2 = COPY %4
; GFX90A: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 4521993 /* reguse:VReg_128_Align2 */, [[COPY]]
; GFX90A: S_ENDPGM 0
AMDGPU: Fix adding extra operands for i128 asm constraints We don't register i128 as a legal type with addRegisterClass, but it appears in the list of legal register types. This inconsistency resulted in the asm constraint lowering trying to use 2 128-bit registers for these operands. This would leave behind a dead def that would waste registers. Regresses GlobalISel tests for i128 load/store, but these aren't very important right now. Ideally these would not depend on the list of register types.
2021-02-03 05:22:32 +08:00
%val = tail call i128 asm sideeffect "; def $0", "=v"()
call void asm sideeffect "; use $0", "v"(i128 %val)
ret void
}
define amdgpu_kernel void @a_input_output_i128() {
AMDGPU: Add even aligned VGPR/AGPR register classes gfx90a operations require even aligned registers, but this was previously achieved by reserving registers inside the full class. Ideally this would be captured in the static instruction definitions for the operands, and we would have different instructions per subtarget. The hackiest part of this is we need to manually reassign AGPR register classes after instruction selection (we get away without this for VGPRs since those types are actually registered for legal types).
2021-02-19 21:57:14 +08:00
; GFX908-LABEL: name: a_input_output_i128
; GFX908: bb.0 (%ir-block.0):
; GFX908: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4325386 /* regdef:AReg_128 */, def %4
; GFX908: [[COPY:%[0-9]+]]:areg_128 = COPY %4
; GFX908: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 4325385 /* reguse:AReg_128 */, [[COPY]]
; GFX908: S_ENDPGM 0
; GFX90A-LABEL: name: a_input_output_i128
; GFX90A: bb.0 (%ir-block.0):
; GFX90A: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4456458 /* regdef:AReg_128_Align2 */, def %4
; GFX90A: [[COPY:%[0-9]+]]:areg_128_align2 = COPY %4
; GFX90A: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 4456457 /* reguse:AReg_128_Align2 */, [[COPY]]
; GFX90A: S_ENDPGM 0
AMDGPU: Fix adding extra operands for i128 asm constraints We don't register i128 as a legal type with addRegisterClass, but it appears in the list of legal register types. This inconsistency resulted in the asm constraint lowering trying to use 2 128-bit registers for these operands. This would leave behind a dead def that would waste registers. Regresses GlobalISel tests for i128 load/store, but these aren't very important right now. Ideally these would not depend on the list of register types.
2021-02-03 05:22:32 +08:00
%val = call i128 asm sideeffect "; def $0", "=a"()
call void asm sideeffect "; use $0", "a"(i128 %val)
ret void
}