llvm-project/llvm/test/CodeGen/AMDGPU/complex-folding.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s

; CHECK: {{^}}main:
; CHECK-NOT: MOV
define amdgpu_ps void @main(<4 x float> inreg %reg0) {
entry:
  %0 = extractelement <4 x float> %reg0, i32 0
  %1 = call float @fabs(float %0)
  %2 = fptoui float %1 to i32
  %3 = bitcast i32 %2 to float
  %4 = insertelement <4 x float> undef, float %3, i32 0
  call void @llvm.r600.store.swizzle(<4 x float> %4, i32 0, i32 0)
  ret void
}

declare float @fabs(float ) readnone
declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
R600: Move fabs/fneg/sel folding logic into PostProcessIsel This move makes possible to correctly handle multiples instructions from a single pattern. llvm-svn: 190643 2013-09-13 07:44:44 +08:00			`;RUN: llc < %s -march=r600 -mcpu=redwood \| FileCheck %s`

R600: Call EmitFunctionHeader() in the AsmPrinter to populate the ELF symbol table llvm-svn: 218776 2014-10-02 01:15:17 +08:00			`; CHECK: {{^}}main:`
R600: Move fabs/fneg/sel folding logic into PostProcessIsel This move makes possible to correctly handle multiples instructions from a single pattern. llvm-svn: 190643 2013-09-13 07:44:44 +08:00			`; CHECK-NOT: MOV`
AMDGPU: Add a shader calling convention This makes it possible to distinguish between mesa shaders and other kernels even in the presence of compute shaders. Patch By: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Differential Revision: http://reviews.llvm.org/D18559 llvm-svn: 265589 2016-04-07 03:40:20 +08:00			`define amdgpu_ps void @main(<4 x float> inreg %reg0) {`
R600: Move fabs/fneg/sel folding logic into PostProcessIsel This move makes possible to correctly handle multiples instructions from a single pattern. llvm-svn: 190643 2013-09-13 07:44:44 +08:00			`entry:`
R600: Use function inputs to represent data stored in gpr llvm-svn: 194425 2013-11-12 06:10:24 +08:00			`%0 = extractelement <4 x float> %reg0, i32 0`
R600: Move fabs/fneg/sel folding logic into PostProcessIsel This move makes possible to correctly handle multiples instructions from a single pattern. llvm-svn: 190643 2013-09-13 07:44:44 +08:00			`%1 = call float @fabs(float %0)`
			`%2 = fptoui float %1 to i32`
			`%3 = bitcast i32 %2 to float`
			`%4 = insertelement <4 x float> undef, float %3, i32 0`
AMDGPU: Fix TargetPrefix for remaining r600 intrinsics llvm-svn: 275619 2016-07-16 05:27:08 +08:00			`call void @llvm.r600.store.swizzle(<4 x float> %4, i32 0, i32 0)`
R600: Move fabs/fneg/sel folding logic into PostProcessIsel This move makes possible to correctly handle multiples instructions from a single pattern. llvm-svn: 190643 2013-09-13 07:44:44 +08:00			`ret void`
			`}`

			`declare float @fabs(float ) readnone`
AMDGPU: Fix TargetPrefix for remaining r600 intrinsics llvm-svn: 275619 2016-07-16 05:27:08 +08:00			`declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)`