forked from OSchip/llvm-project
204 lines
6.6 KiB
LLVM
204 lines
6.6 KiB
LLVM
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; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s
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; Test that unused lanes in the s_xor result are masked out with v_cndmask.
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; CHECK-LABEL: combine_add_zext_xor:
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; CHECK: s_xor_b32 [[RESULT:s[0-9]+]]
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; CHECK: v_cndmask_b32_e64 [[ARG:v[0-9]+]], 0, 1, [[RESULT]]
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; CHECK: v_add_nc_u32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[ARG]]
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define i32 @combine_add_zext_xor() {
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.entry:
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br label %.a
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.a: ; preds = %bb9, %.entry
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%.2 = phi i32 [ 0, %.entry ], [ %i11, %bb9 ]
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br i1 undef, label %bb9, label %bb
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bb: ; preds = %.a
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%.i3 = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> undef, i32 %.2, i32 64, i32 1)
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%i5 = icmp eq i32 %.i3, 0
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br label %bb9
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bb9: ; preds = %bb, %.a
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%.2.0.in.in = phi i1 [ %i5, %bb ], [ undef, %.a ]
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%.2.0.in = xor i1 %.2.0.in.in, true
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%.2.0 = zext i1 %.2.0.in to i32
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%i11 = add i32 %.2, %.2.0
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%i12 = icmp sgt i32 %.2, -1050
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br i1 %i12, label %.a, label %.exit
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.exit: ; preds = %bb9
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ret i32 %.2.0
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}
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; Test that unused lanes in the s_xor result are masked out with v_cndmask.
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; CHECK-LABEL: combine_sub_zext_xor:
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; CHECK: s_xor_b32 [[RESULT:s[0-9]+]]
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; CHECK: v_cndmask_b32_e64 [[ARG:v[0-9]+]], 0, 1, [[RESULT]]
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; CHECK: v_sub_nc_u32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[ARG]]
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define i32 @combine_sub_zext_xor() {
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.entry:
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br label %.a
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.a: ; preds = %bb9, %.entry
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%.2 = phi i32 [ 0, %.entry ], [ %i11, %bb9 ]
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br i1 undef, label %bb9, label %bb
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bb: ; preds = %.a
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%.i3 = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> undef, i32 %.2, i32 64, i32 1)
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%i5 = icmp eq i32 %.i3, 0
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br label %bb9
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bb9: ; preds = %bb, %.a
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%.2.0.in.in = phi i1 [ %i5, %bb ], [ undef, %.a ]
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%.2.0.in = xor i1 %.2.0.in.in, true
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%.2.0 = zext i1 %.2.0.in to i32
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%i11 = sub i32 %.2, %.2.0
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%i12 = icmp sgt i32 %.2, -1050
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br i1 %i12, label %.a, label %.exit
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.exit: ; preds = %bb9
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ret i32 %.2.0
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}
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; Test that unused lanes in the s_or result are masked out with v_cndmask.
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; CHECK-LABEL: combine_add_zext_or:
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; CHECK: s_or_b32 [[RESULT:s[0-9]+]]
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; CHECK: v_cndmask_b32_e64 [[ARG:v[0-9]+]], 0, 1, [[RESULT]]
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; CHECK: v_add_nc_u32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[ARG]]
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define i32 @combine_add_zext_or() {
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.entry:
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br label %.a
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.a: ; preds = %bb9, %.entry
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%.2 = phi i32 [ 0, %.entry ], [ %i11, %bb9 ]
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br i1 undef, label %bb9, label %bb
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bb: ; preds = %.a
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%.i3 = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> undef, i32 %.2, i32 64, i32 1)
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%i5 = icmp eq i32 %.i3, 0
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br label %bb9
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bb9: ; preds = %bb, %.a
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%.2.0.in.in = phi i1 [ %i5, %bb ], [ undef, %.a ]
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%t = icmp sgt i32 %.2, -1050
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%.2.0.in = or i1 %.2.0.in.in, %t
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%.2.0 = zext i1 %.2.0.in to i32
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%i11 = add i32 %.2, %.2.0
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%i12 = icmp sgt i32 %.2, -1050
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br i1 %i12, label %.a, label %.exit
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.exit: ; preds = %bb9
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ret i32 %.2.0
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}
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; Test that unused lanes in the s_or result are masked out with v_cndmask.
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; CHECK-LABEL: combine_sub_zext_or:
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; CHECK: s_or_b32 [[RESULT:s[0-9]+]]
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; CHECK: v_cndmask_b32_e64 [[ARG:v[0-9]+]], 0, 1, [[RESULT]]
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; CHECK: v_sub_nc_u32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[ARG]]
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define i32 @combine_sub_zext_or() {
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.entry:
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br label %.a
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.a: ; preds = %bb9, %.entry
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%.2 = phi i32 [ 0, %.entry ], [ %i11, %bb9 ]
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br i1 undef, label %bb9, label %bb
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bb: ; preds = %.a
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%.i3 = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> undef, i32 %.2, i32 64, i32 1)
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%i5 = icmp eq i32 %.i3, 0
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br label %bb9
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bb9: ; preds = %bb, %.a
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%.2.0.in.in = phi i1 [ %i5, %bb ], [ undef, %.a ]
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%t = icmp sgt i32 %.2, -1050
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%.2.0.in = or i1 %.2.0.in.in, %t
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%.2.0 = zext i1 %.2.0.in to i32
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%i11 = sub i32 %.2, %.2.0
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%i12 = icmp sgt i32 %.2, -1050
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br i1 %i12, label %.a, label %.exit
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.exit: ; preds = %bb9
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ret i32 %.2.0
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}
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; Test that unused lanes in the s_and result are masked out with v_cndmask.
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; CHECK-LABEL: combine_add_zext_and:
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; CHECK: s_and_b32 [[RESULT:s[0-9]+]]
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; CHECK: v_cndmask_b32_e64 [[ARG:v[0-9]+]], 0, 1, [[RESULT]]
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; CHECK: v_add_nc_u32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[ARG]]
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define i32 @combine_add_zext_and() {
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.entry:
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br label %.a
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.a: ; preds = %bb9, %.entry
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%.2 = phi i32 [ 0, %.entry ], [ %i11, %bb9 ]
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br i1 undef, label %bb9, label %bb
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bb: ; preds = %.a
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%.i3 = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> undef, i32 %.2, i32 64, i32 1)
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%i5 = icmp eq i32 %.i3, 0
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br label %bb9
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bb9: ; preds = %bb, %.a
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%.2.0.in.in = phi i1 [ %i5, %bb ], [ undef, %.a ]
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%t = icmp sgt i32 %.2, -1050
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%.2.0.in = and i1 %.2.0.in.in, %t
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%.2.0 = zext i1 %.2.0.in to i32
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%i11 = add i32 %.2, %.2.0
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%i12 = icmp sgt i32 %.2, -1050
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br i1 %i12, label %.a, label %.exit
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.exit: ; preds = %bb9
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ret i32 %.2.0
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}
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; Test that unused lanes in the s_and result are masked out with v_cndmask.
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; CHECK-LABEL: combine_sub_zext_and:
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; CHECK: s_and_b32 [[RESULT:s[0-9]+]]
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; CHECK: v_cndmask_b32_e64 [[ARG:v[0-9]+]], 0, 1, [[RESULT]]
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; CHECK: v_sub_nc_u32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[ARG]]
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define i32 @combine_sub_zext_and() {
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.entry:
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br label %.a
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.a: ; preds = %bb9, %.entry
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%.2 = phi i32 [ 0, %.entry ], [ %i11, %bb9 ]
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br i1 undef, label %bb9, label %bb
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bb: ; preds = %.a
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%.i3 = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> undef, i32 %.2, i32 64, i32 1)
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%i5 = icmp eq i32 %.i3, 0
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br label %bb9
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bb9: ; preds = %bb, %.a
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%.2.0.in.in = phi i1 [ %i5, %bb ], [ undef, %.a ]
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%t = icmp sgt i32 %.2, -1050
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%.2.0.in = and i1 %.2.0.in.in, %t
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%.2.0 = zext i1 %.2.0.in to i32
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%i11 = sub i32 %.2, %.2.0
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%i12 = icmp sgt i32 %.2, -1050
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br i1 %i12, label %.a, label %.exit
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.exit: ; preds = %bb9
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ret i32 %.2.0
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}
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; Function Attrs: nounwind readonly willreturn
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declare i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32>, i32, i32, i32 immarg) #0
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attributes #0 = { nounwind readonly willreturn }
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