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llvm-project/llvm/lib/Target/Mips/Mips64InstrInfo.td

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Add .td file. llvm-svn: 140446
2011-09-24 09:40:18 +08:00
//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes Mips64 instructions.
//
//===----------------------------------------------------------------------===//
Mips64 predicate definitions. Patch by Liu. llvm-svn: 140703
2011-09-29 01:50:27 +08:00
Mips64 arithmetic and logical instructions with one source register and immediate. llvm-svn: 140839
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//===----------------------------------------------------------------------===//
// Mips Operand, Complex Patterns and Transformations Definitions.
//===----------------------------------------------------------------------===//
// Instruction operand types
Mips64 shift instructions. llvm-svn: 140841
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def shamt_64 : Operand<i64>;
Mips64 arithmetic and logical instructions with one source register and immediate. llvm-svn: 140839
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// Unsigned Operand
def uimm16_64 : Operand<i64> {
let PrintMethod = "printUnsignedImm";
}
Mips64 shift instructions. llvm-svn: 140841
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// Transformation Function - get Imm - 32.
def Subtract32 : SDNodeXForm<imm, [{
Fix 64-bit immediate patterns. llvm-svn: 146059
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return getImm(N, (unsigned)N->getZExtValue() - 32);
Mips64 shift instructions. llvm-svn: 140841
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}]>;
Remove definitions of double word shift plus 32 instructions. Assembler or direct-object emitter should emit the appropriate shift instruction depending on the shift amount. llvm-svn: 146893
2011-12-20 03:44:09 +08:00
// shamt must fit in 6 bits.
def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
Mips64 shift instructions. llvm-svn: 140841
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Mips64 arithmetic and logical instructions with two source registers. llvm-svn: 140806
2011-09-30 04:37:56 +08:00
//===----------------------------------------------------------------------===//
// Instructions specific format
//===----------------------------------------------------------------------===//
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
let DecoderNamespace = "Mips64" in {
Mips64 shift instructions. llvm-svn: 140841
2011-09-30 11:18:46 +08:00
[mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass parameter. llvm-svn: 170661
2012-12-20 12:20:09 +08:00
multiclass Atomic2Ops64<PatFrag Op> {
Remove # from the beginning and end of def names. The # is a paste operator and should only be used with something to paste on either side. llvm-svn: 171697
2013-01-07 13:45:56 +08:00
def NAME : Atomic2Ops<Op, CPU64Regs, CPURegs>,
Requires<[NotN64, HasStdEnc]>;
def _P8 : Atomic2Ops<Op, CPU64Regs, CPU64Regs>,
Requires<[IsN64, HasStdEnc]> {
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
let isCodeGenOnly = 1;
}
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
}
[mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass parameter. llvm-svn: 170661
2012-12-20 12:20:09 +08:00
multiclass AtomicCmpSwap64<PatFrag Op> {
Remove # from the beginning and end of def names. The # is a paste operator and should only be used with something to paste on either side. llvm-svn: 171697
2013-01-07 13:45:56 +08:00
def NAME : AtomicCmpSwap<Op, CPU64Regs, CPURegs>,
Requires<[NotN64, HasStdEnc]>;
def _P8 : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>,
Requires<[IsN64, HasStdEnc]> {
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
let isCodeGenOnly = 1;
}
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
}
[mips] Shorten predicate name. llvm-svn: 169579
2012-12-07 11:06:09 +08:00
let usesCustomInserter = 1, Predicates = [HasStdEnc],
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
DecoderNamespace = "Mips64" in {
[mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass parameter. llvm-svn: 170661
2012-12-20 12:20:09 +08:00
defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64>;
defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64>;
defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64>;
defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64>;
defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64>;
defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64>;
defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64>;
defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64>;
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
}
[mips] Define pseudo instructions for spilling and copying accumulator registers. llvm-svn: 178390
2013-03-30 08:54:52 +08:00
/// Pseudo instructions for loading, storing and copying accumulator registers.
let isPseudo = 1 in {
defm LOAD_AC128 : LoadM<"load_ac128", ACRegs128>;
defm STORE_AC128 : StoreM<"store_ac128", ACRegs128>;
}
def COPY_AC128 : PseudoSE<(outs ACRegs128:$dst), (ins ACRegs128:$src), []>;
Mips64 arithmetic and logical instructions with two source registers. llvm-svn: 140806
2011-09-30 04:37:56 +08:00
//===----------------------------------------------------------------------===//
// Instruction definition
//===----------------------------------------------------------------------===//
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
let DecoderNamespace = "Mips64" in {
Mips64 arithmetic and logical instructions with one source register and immediate. llvm-svn: 140839
2011-09-30 10:08:54 +08:00
/// Arithmetic Instructions (ALU Immediate)
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
def DADDi : ArithLogicI<"daddi", simm16_64, CPU64RegsOpnd>, ADDI_FM<0x18>;
def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64RegsOpnd, immSExt16, add>,
[mips] Refactor arithmetic and logic instructions with immediate operands. Separate encoding information from the rest. llvm-svn: 170648
2012-12-20 11:40:03 +08:00
ADDI_FM<0x19>, IsAsCheapAsAMove;
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
def DANDi : ArithLogicI<"andi", uimm16_64, CPU64RegsOpnd, immZExt16, and>,
[mips] Refactor arithmetic and logic instructions with immediate operands. Separate encoding information from the rest. llvm-svn: 170648
2012-12-20 11:40:03 +08:00
ADDI_FM<0xc>;
[mips] Refactor SLT (set on less than) instructions. Separate encoding information from the rest. llvm-svn: 170664
2012-12-20 12:27:52 +08:00
def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, CPU64Regs>,
SLTI_FM<0xa>;
def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, CPU64Regs>,
SLTI_FM<0xb>;
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64RegsOpnd, immZExt16, or>,
[mips] Refactor arithmetic and logic instructions with immediate operands. Separate encoding information from the rest. llvm-svn: 170648
2012-12-20 11:40:03 +08:00
ADDI_FM<0xd>;
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64RegsOpnd, immZExt16, xor>,
[mips] Refactor arithmetic and logic instructions with immediate operands. Separate encoding information from the rest. llvm-svn: 170648
2012-12-20 11:40:03 +08:00
ADDI_FM<0xe>;
[mips] Refactor LUI instruction. llvm-svn: 170944
2012-12-22 06:46:07 +08:00
def LUi64 : LoadUpper<"lui", CPU64Regs, uimm16_64>, LUI_FM;
Mips64 arithmetic and logical instructions with one source register and immediate. llvm-svn: 140839
2011-09-30 10:08:54 +08:00
Mips64 arithmetic and logical instructions with two source registers. llvm-svn: 140806
2011-09-30 04:37:56 +08:00
/// Arithmetic Instructions (3-Operand, R-Type)
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
def DADD : ArithLogicR<"dadd", CPU64RegsOpnd>, ADD_FM<0, 0x2c>;
def DADDu : ArithLogicR<"daddu", CPU64RegsOpnd, 1, IIAlu, add>,
ADD_FM<0, 0x2d>;
def DSUBu : ArithLogicR<"dsubu", CPU64RegsOpnd, 0, IIAlu, sub>,
ADD_FM<0, 0x2f>;
[mips] Refactor SLT (set on less than) instructions. Separate encoding information from the rest. llvm-svn: 170664
2012-12-20 12:27:52 +08:00
def SLT64 : SetCC_R<"slt", setlt, CPU64Regs>, ADD_FM<0, 0x2a>;
def SLTu64 : SetCC_R<"sltu", setult, CPU64Regs>, ADD_FM<0, 0x2b>;
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
def AND64 : ArithLogicR<"and", CPU64RegsOpnd, 1, IIAlu, and>, ADD_FM<0, 0x24>;
def OR64 : ArithLogicR<"or", CPU64RegsOpnd, 1, IIAlu, or>, ADD_FM<0, 0x25>;
def XOR64 : ArithLogicR<"xor", CPU64RegsOpnd, 1, IIAlu, xor>, ADD_FM<0, 0x26>;
def NOR64 : LogicNOR<"nor", CPU64RegsOpnd>, ADD_FM<0, 0x27>;
Mips64 shift instructions. llvm-svn: 140841
2011-09-30 11:18:46 +08:00
/// Shift Instructions
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
def DSLL : shift_rotate_imm<"dsll", shamt, CPU64RegsOpnd, shl, immZExt6>,
[mips] Reorder template parameters. Remove class shift_rotate_imm32 and shift_rotate_imm64. llvm-svn: 171513
2013-01-05 03:25:46 +08:00
SRA_FM<0x38, 0>;
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
def DSRL : shift_rotate_imm<"dsrl", shamt, CPU64RegsOpnd, srl, immZExt6>,
[mips] Reorder template parameters. Remove class shift_rotate_imm32 and shift_rotate_imm64. llvm-svn: 171513
2013-01-05 03:25:46 +08:00
SRA_FM<0x3a, 0>;
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
def DSRA : shift_rotate_imm<"dsra", shamt, CPU64RegsOpnd, sra, immZExt6>,
[mips] Reorder template parameters. Remove class shift_rotate_imm32 and shift_rotate_imm64. llvm-svn: 171513
2013-01-05 03:25:46 +08:00
SRA_FM<0x3b, 0>;
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
def DSLLV : shift_rotate_reg<"dsllv", CPU64RegsOpnd, shl>, SRLV_FM<0x14, 0>;
def DSRLV : shift_rotate_reg<"dsrlv", CPU64RegsOpnd, srl>, SRLV_FM<0x16, 0>;
def DSRAV : shift_rotate_reg<"dsrav", CPU64RegsOpnd, sra>, SRLV_FM<0x17, 0>;
def DSLL32 : shift_rotate_imm<"dsll32", shamt, CPU64RegsOpnd>, SRA_FM<0x3c, 0>;
def DSRL32 : shift_rotate_imm<"dsrl32", shamt, CPU64RegsOpnd>, SRA_FM<0x3e, 0>;
def DSRA32 : shift_rotate_imm<"dsra32", shamt, CPU64RegsOpnd>, SRA_FM<0x3f, 0>;
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
}
Add definitions of Mips64 rotate instructions. llvm-svn: 140870
2011-10-01 02:51:46 +08:00
// Rotate Instructions
[mips] Shorten predicate name. llvm-svn: 169579
2012-12-07 11:06:09 +08:00
let Predicates = [HasMips64r2, HasStdEnc],
This patch adds a predicate to existing mips32 and mips64 so that those instruction encodings can be excluded during mips16 processing. This revision fixes the issue raised by Jim Grosbach. bool hasStandardEncoding() const { return !inMips16Mode(); } When micromips is added it will be bool StandardEncoding() const { return !inMips16Mode()&& !inMicroMipsMode(); } No additional testing is needed other than to assure that there is no regression from this patch. Patch by Reed Kotler. llvm-svn: 157234
2012-05-22 11:10:09 +08:00
DecoderNamespace = "Mips64" in {
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
def DROTR : shift_rotate_imm<"drotr", shamt, CPU64RegsOpnd, rotr, immZExt6>,
This is a resubmittal. For some reason it broke the bots yesterday but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Removal of redundant code and formatting fixes. Contributers: Jack Carter/Vladimir Medic llvm-svn: 172842
2013-01-19 04:15:06 +08:00
SRA_FM<0x3a, 1>;
def DROTRV : shift_rotate_reg<"drotrv", CPU64RegsOpnd, rotr>,
SRLV_FM<0x16, 1>;
Add definitions of Mips64 rotate instructions. llvm-svn: 140870
2011-10-01 02:51:46 +08:00
}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
let DecoderNamespace = "Mips64" in {
Add definitions of 64-bit loads and stores. Add a patterns for unaligned zextloadi32 for which there is no corresponding pseudo or real instruction. llvm-svn: 141608
2011-10-11 08:27:28 +08:00
/// Load and Store Instructions
remove blanks, and some code format llvm-svn: 151625
2012-02-28 15:46:26 +08:00
/// aligned
[mips] Reorder template parameters. Remove class shift_rotate_imm32 and shift_rotate_imm64. llvm-svn: 171513
2013-01-05 03:25:46 +08:00
defm LB64 : LoadM<"lb", CPU64Regs, sextloadi8>, LW_FM<0x20>;
defm LBu64 : LoadM<"lbu", CPU64Regs, zextloadi8>, LW_FM<0x24>;
defm LH64 : LoadM<"lh", CPU64Regs, sextloadi16>, LW_FM<0x21>;
defm LHu64 : LoadM<"lhu", CPU64Regs, zextloadi16>, LW_FM<0x25>;
defm LW64 : LoadM<"lw", CPU64Regs, sextloadi32>, LW_FM<0x23>;
defm LWu64 : LoadM<"lwu", CPU64Regs, zextloadi32>, LW_FM<0x27>;
defm SB64 : StoreM<"sb", CPU64Regs, truncstorei8>, LW_FM<0x28>;
defm SH64 : StoreM<"sh", CPU64Regs, truncstorei16>, LW_FM<0x29>;
defm SW64 : StoreM<"sw", CPU64Regs, truncstorei32>, LW_FM<0x2b>;
defm LD : LoadM<"ld", CPU64Regs, load>, LW_FM<0x37>;
defm SD : StoreM<"sd", CPU64Regs, store>, LW_FM<0x3f>;
Add definitions of 64-bit loads and stores. Add a patterns for unaligned zextloadi32 for which there is no corresponding pseudo or real instruction. llvm-svn: 141608
2011-10-11 08:27:28 +08:00
Add definitions of 32/64-bit unaligned load/store instructions for Mips. llvm-svn: 157865
2012-06-02 08:04:19 +08:00
/// load/store left/right
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, CPU64Regs>, LW_FM<0x22>;
defm LWR64 : LoadLeftRightM<"lwr", MipsLWR, CPU64Regs>, LW_FM<0x26>;
defm SWL64 : StoreLeftRightM<"swl", MipsSWL, CPU64Regs>, LW_FM<0x2a>;
defm SWR64 : StoreLeftRightM<"swr", MipsSWR, CPU64Regs>, LW_FM<0x2e>;
[mips] Refactor load/store left/right and load-link and store-conditional instructions. llvm-svn: 170950
2012-12-22 07:01:24 +08:00
defm LDL : LoadLeftRightM<"ldl", MipsLDL, CPU64Regs>, LW_FM<0x1a>;
defm LDR : LoadLeftRightM<"ldr", MipsLDR, CPU64Regs>, LW_FM<0x1b>;
defm SDL : StoreLeftRightM<"sdl", MipsSDL, CPU64Regs>, LW_FM<0x2c>;
defm SDR : StoreLeftRightM<"sdr", MipsSDR, CPU64Regs>, LW_FM<0x2d>;
Add definitions of 32/64-bit unaligned load/store instructions for Mips. llvm-svn: 157865
2012-06-02 08:04:19 +08:00
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
/// Load-linked, Store-conditional
[mips] Refactor load/store left/right and load-link and store-conditional instructions. llvm-svn: 170950
2012-12-22 07:01:24 +08:00
let Predicates = [NotN64, HasStdEnc] in {
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
def LLD : LLBase<"lld", CPU64RegsOpnd, mem>, LW_FM<0x34>;
def SCD : SCBase<"scd", CPU64RegsOpnd, mem>, LW_FM<0x3c>;
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
}
[mips] Refactor load/store left/right and load-link and store-conditional instructions. llvm-svn: 170950
2012-12-22 07:01:24 +08:00
let Predicates = [IsN64, HasStdEnc], isCodeGenOnly = 1 in {
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
def LLD_P8 : LLBase<"lld", CPU64RegsOpnd, mem64>, LW_FM<0x34>;
def SCD_P8 : SCBase<"scd", CPU64RegsOpnd, mem64>, LW_FM<0x3c>;
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
}
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
Add support for conditional branch instructions with 64-bit register operands. llvm-svn: 141694
2011-10-12 02:49:17 +08:00
/// Jump and Branch Instructions
[mips] Refactor jump, jump register, jump-and-link and nop instructions. llvm-svn: 170952
2012-12-22 07:03:50 +08:00
def JR64 : IndirectBranch<CPU64Regs>, MTLO_FM<8>;
[mips] Refactor conditional branch instructions with two register operands. Separate encoding information from the rest. llvm-svn: 170657
2012-12-20 12:10:13 +08:00
def BEQ64 : CBranch<"beq", seteq, CPU64Regs>, BEQ_FM<4>;
def BNE64 : CBranch<"bne", setne, CPU64Regs>, BEQ_FM<5>;
[mips] Refactor conditional branch instructions with one register operand. Separate encoding information from the rest. llvm-svn: 170659
2012-12-20 12:13:23 +08:00
def BGEZ64 : CBranchZero<"bgez", setge, CPU64Regs>, BGEZ_FM<1, 1>;
def BGTZ64 : CBranchZero<"bgtz", setgt, CPU64Regs>, BGEZ_FM<7, 0>;
def BLEZ64 : CBranchZero<"blez", setle, CPU64Regs>, BGEZ_FM<6, 0>;
def BLTZ64 : CBranchZero<"bltz", setlt, CPU64Regs>, BGEZ_FM<1, 0>;
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
}
let DecoderNamespace = "Mips64" in
[mips] Refactor jump, jump register, jump-and-link and nop instructions. llvm-svn: 170952
2012-12-22 07:03:50 +08:00
def JALR64 : JumpLinkReg<"jalr", CPU64Regs>, JALR_FM;
[mips] Add definition of JALR instruction which has two register operands. Change the original JALR instruction with one register operand to be a pseudo-instruction. llvm-svn: 174657
2013-02-08 03:48:00 +08:00
def JALR64Pseudo : JumpLinkRegPseudo<CPU64Regs, JALR64, RA_64>;
[mips] Refactor jump, jump register, jump-and-link and nop instructions. llvm-svn: 170952
2012-12-22 07:03:50 +08:00
def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, MTLO_FM<8>, IsTailCall;
- Define base classes for Jump-and-link instructions and make 32-bit and 64-bit versions derive from them. - JALR64 is not needed since N64 does not emit jal. - Add template parameter to BranchLink that sets the rt field. - Fix the set of temporary registers for O32 and N64. llvm-svn: 147518
2012-01-04 11:02:47 +08:00
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
let DecoderNamespace = "Mips64" in {
Add support for 64-bit integer multiply instructions. llvm-svn: 141017
2011-10-04 04:01:11 +08:00
/// Multiply and Divide Instructions.
This is a resubmittal. For some reason it broke the bots yesterday but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Removal of redundant code and formatting fixes. Contributers: Jack Carter/Vladimir Medic llvm-svn: 172842
2013-01-19 04:15:06 +08:00
def DMULT : Mult<"dmult", IIImul, CPU64RegsOpnd, [HI64, LO64]>,
MULT_FM<0, 0x1c>;
def DMULTu : Mult<"dmultu", IIImul, CPU64RegsOpnd, [HI64, LO64]>,
MULT_FM<0, 0x1d>;
[mips] Fix definitions of multiply, multiply-add/sub and divide instructions. The new instructions have explicit register output operands and use table-gen patterns instead of C++ code to do instruction selection. Mips16's instructions are unaffected by this change. llvm-svn: 178403
2013-03-30 09:36:35 +08:00
def PseudoDMULT : MultDivPseudo<DMULT, ACRegs128, CPU64RegsOpnd, MipsMult,
IIImul>;
def PseudoDMULTu : MultDivPseudo<DMULTu, ACRegs128, CPU64RegsOpnd, MipsMultu,
IIImul>;
def DSDIV : Div<"ddiv", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>, MULT_FM<0, 0x1e>;
def DUDIV : Div<"ddivu", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>, MULT_FM<0, 0x1f>;
def PseudoDSDIV : MultDivPseudo<DSDIV, ACRegs128, CPU64RegsOpnd, MipsDivRem,
IIIdiv, 0>;
def PseudoDUDIV : MultDivPseudo<DUDIV, ACRegs128, CPU64RegsOpnd, MipsDivRemU,
IIIdiv, 0>;
Add support for 64-bit integer multiply instructions. llvm-svn: 141017
2011-10-04 04:01:11 +08:00
[mips] Refactor instructions which copy from and to HI/LO registers. llvm-svn: 170939
2012-12-22 06:39:17 +08:00
def MTHI64 : MoveToLOHI<"mthi", CPU64Regs, [HI64]>, MTLO_FM<0x11>;
def MTLO64 : MoveToLOHI<"mtlo", CPU64Regs, [LO64]>, MTLO_FM<0x13>;
def MFHI64 : MoveFromLOHI<"mfhi", CPU64Regs, [HI64]>, MFLO_FM<0x10>;
def MFLO64 : MoveFromLOHI<"mflo", CPU64Regs, [LO64]>, MFLO_FM<0x12>;
Add definitions of instructions which move values between 64-bit integer registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions of the instructions. llvm-svn: 141015
2011-10-04 03:28:44 +08:00
64-bit sign extension in register instructions. llvm-svn: 148862
2012-01-25 05:41:09 +08:00
/// Sign Ext In Register Instructions.
[mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardware instructions. llvm-svn: 170956
2012-12-22 07:21:32 +08:00
def SEB64 : SignExtInReg<"seb", i8, CPU64Regs>, SEB_FM<0x10, 0x20>;
def SEH64 : SignExtInReg<"seh", i16, CPU64Regs>, SEB_FM<0x18, 0x20>;
64-bit sign extension in register instructions. llvm-svn: 148862
2012-01-25 05:41:09 +08:00
Add support for 64-bit count leading ones and zeros instructions. llvm-svn: 141028
2011-10-04 05:16:50 +08:00
/// Count Leading
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
def DCLZ : CountLeading0<"dclz", CPU64RegsOpnd>, CLO_FM<0x24>;
def DCLO : CountLeading1<"dclo", CPU64RegsOpnd>, CLO_FM<0x25>;
Add support for 64-bit count leading ones and zeros instructions. llvm-svn: 141028
2011-10-04 05:16:50 +08:00
Add definition of DSBH (Double Swap Bytes within Halfwords) and DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces 64-bit bswap with a DSBH and DSHD pair. llvm-svn: 147017
2011-12-21 07:56:43 +08:00
/// Double Word Swap Bytes/HalfWords
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
def DSBH : SubwordSwap<"dsbh", CPU64RegsOpnd>, SEB_FM<2, 0x24>;
def DSHD : SubwordSwap<"dshd", CPU64RegsOpnd>, SEB_FM<5, 0x24>;
[mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardware instructions. llvm-svn: 170956
2012-12-22 07:21:32 +08:00
def LEA_ADDiu64 : EffectiveAddress<"daddiu", CPU64Regs, mem_ea_64>, LW_FM<0x19>;
Add definition of DSBH (Double Swap Bytes within Halfwords) and DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces 64-bit bswap with a DSBH and DSHD pair. llvm-svn: 147017
2011-12-21 07:56:43 +08:00
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
}
let DecoderNamespace = "Mips64" in {
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
def RDHWR64 : ReadHardware<CPU64Regs, HW64RegsOpnd>, RDHWR_FM;
Modify class ReadHardware and add definition of 64-bit version of instruction RDHWR. llvm-svn: 146101
2011-12-08 07:31:26 +08:00
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
def DEXT : ExtBase<"dext", CPU64RegsOpnd>, EXT_FM<3>;
The instruction DEXT may be transformed into DEXTU or DEXTM depending on the size of the extraction and its position in the 64 bit word. This patch allows support of the dext transformations with mips64 direct object output. 0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32 DINS The field is entirely contained in the right-most word of the doubleword 32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64 DINSM The field straddles the words of the doubleword 32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32 DINSU The field is entirely contained in the left-most word of the doubleword llvm-svn: 162782
2012-08-29 04:07:41 +08:00
let Pattern = []<dag> in {
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
def DEXTU : ExtBase<"dextu", CPU64RegsOpnd>, EXT_FM<2>;
def DEXTM : ExtBase<"dextm", CPU64RegsOpnd>, EXT_FM<1>;
The instruction DEXT may be transformed into DEXTU or DEXTM depending on the size of the extraction and its position in the 64 bit word. This patch allows support of the dext transformations with mips64 direct object output. 0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32 DINS The field is entirely contained in the right-most word of the doubleword 32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64 DINSM The field straddles the words of the doubleword 32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32 DINSU The field is entirely contained in the left-most word of the doubleword llvm-svn: 162782
2012-08-29 04:07:41 +08:00
}
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
def DINS : InsBase<"dins", CPU64RegsOpnd>, EXT_FM<7>;
The instruction DINS may be transformed into DINSU or DEXTM depending on the size of the extraction and its position in the 64 bit word. This patch allows support of the dext transformations with mips64 direct object output. 0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32 DINS The field is entirely contained in the right-most word of the doubleword 32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64 DINSM The field straddles the words of the doubleword 32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32 DINSU The field is entirely contained in the left-most word of the doubleword llvm-svn: 163010
2012-09-01 02:06:48 +08:00
let Pattern = []<dag> in {
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
def DINSU : InsBase<"dinsu", CPU64RegsOpnd>, EXT_FM<6>;
def DINSM : InsBase<"dinsm", CPU64RegsOpnd>, EXT_FM<5>;
The instruction DINS may be transformed into DINSU or DEXTM depending on the size of the extraction and its position in the 64 bit word. This patch allows support of the dext transformations with mips64 direct object output. 0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32 DINS The field is entirely contained in the right-most word of the doubleword 32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64 DINSM The field straddles the words of the doubleword 32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32 DINSU The field is entirely contained in the left-most word of the doubleword llvm-svn: 163010
2012-09-01 02:06:48 +08:00
}
Add definitions of 64-bit extract and insert instrucions and make PerformANDCombine and PerformOrCombine aware of them. Test cases are included too. llvm-svn: 145853
2011-12-06 05:26:34 +08:00
The define for 64 bit sign extension neglected to initialize fields of the class that it used. The result was nonsense code. Before: 0000000000000000 <foo>: 0: 00441100 0x441100 4: 03e00008 jr ra 8: 00000000 nop After: 0000000000000000 <foo>: 0: 00041000 sll v0,a0,0x0 4: 03e00008 jr ra 8: 00000000 nop llvm-svn: 161377
2012-08-07 08:35:22 +08:00
let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
Another 32 to 64 bit sign extension bug. The fields in the td definition were switched. llvm-svn: 161607
2012-08-10 03:43:18 +08:00
def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
The define for 64 bit sign extension neglected to initialize fields of the class that it used. The result was nonsense code. Before: 0000000000000000 <foo>: 0: 00441100 0x441100 4: 03e00008 jr ra 8: 00000000 nop After: 0000000000000000 <foo>: 0: 00041000 sll v0,a0,0x0 4: 03e00008 jr ra 8: 00000000 nop llvm-svn: 161377
2012-08-07 08:35:22 +08:00
"dsll\t$rd, $rt, 32", [], IIAlu>;
def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
"sll\t$rd, $rt, 0", [], IIAlu>;
def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt),
"sll\t$rd, $rt, 0", [], IIAlu>;
}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
}
Add definitions of Mips64 rotate instructions. llvm-svn: 140870
2011-10-01 02:51:46 +08:00
//===----------------------------------------------------------------------===//
// Arbitrary patterns that map to one or more instructions
//===----------------------------------------------------------------------===//
32-to-64-bit extended load. llvm-svn: 144554
2011-11-15 03:06:14 +08:00
// extended loads
[mips] Shorten predicate name. llvm-svn: 169579
2012-12-07 11:06:09 +08:00
let Predicates = [NotN64, HasStdEnc] in {
1. introduce MipsPat in place of Pat in order to exclude those from being used by Mips16 or Micro Mips 2. clean up a few lines too long encountered Patch by Reed Kotler. llvm-svn: 158470
2012-06-15 05:03:23 +08:00
def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
Remove aligned/unaligned load/store fragments defined in MipsInstrInfo.td and use load/store fragments defined in TargetSelectionDAG.td in place of them. Unaligned loads/stores are either expanded or lowered to target-specific nodes, so instruction selection should see only aligned load/store nodes. No changes in functionality. llvm-svn: 163960
2012-09-15 09:52:08 +08:00
def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
32-to-64-bit extended load. llvm-svn: 144554
2011-11-15 03:06:14 +08:00
}
[mips] Shorten predicate name. llvm-svn: 169579
2012-12-07 11:06:09 +08:00
let Predicates = [IsN64, HasStdEnc] in {
1. introduce MipsPat in place of Pat in order to exclude those from being used by Mips16 or Micro Mips 2. clean up a few lines too long encountered Patch by Reed Kotler. llvm-svn: 158470
2012-06-15 05:03:23 +08:00
def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>;
def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>;
Remove aligned/unaligned load/store fragments defined in MipsInstrInfo.td and use load/store fragments defined in TargetSelectionDAG.td in place of them. Unaligned loads/stores are either expanded or lowered to target-specific nodes, so instruction selection should see only aligned load/store nodes. No changes in functionality. llvm-svn: 163960
2012-09-15 09:52:08 +08:00
def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>;
def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>;
32-to-64-bit extended load. llvm-svn: 144554
2011-11-15 03:06:14 +08:00
}
Modify lowering of GlobalAddress so that correct code is emitted when target is Mips64. llvm-svn: 141618
2011-10-11 08:55:05 +08:00
// hi/lo relocs
1. introduce MipsPat in place of Pat in order to exclude those from being used by Mips16 or Micro Mips 2. clean up a few lines too long encountered Patch by Reed Kotler. llvm-svn: 158470
2012-06-15 05:03:23 +08:00
def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
[mips] Generate big GOT code. llvm-svn: 168460
2012-11-22 04:40:38 +08:00
def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
1. introduce MipsPat in place of Pat in order to exclude those from being used by Mips16 or Micro Mips 2. clean up a few lines too long encountered Patch by Reed Kotler. llvm-svn: 158470
2012-06-15 05:03:23 +08:00
def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
def : MipsPat<(MipsLo tglobaltlsaddr:$in),
(DADDiu ZERO_64, tglobaltlsaddr:$in)>;
[mips] Generate big GOT code. llvm-svn: 168460
2012-11-22 04:40:38 +08:00
def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
1. introduce MipsPat in place of Pat in order to exclude those from being used by Mips16 or Micro Mips 2. clean up a few lines too long encountered Patch by Reed Kotler. llvm-svn: 158470
2012-06-15 05:03:23 +08:00
def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)),
(DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>;
def : MipsPat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)),
(DADDiu CPU64Regs:$hi, tblockaddress:$lo)>;
def : MipsPat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)),
(DADDiu CPU64Regs:$hi, tjumptable:$lo)>;
def : MipsPat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)),
(DADDiu CPU64Regs:$hi, tconstpool:$lo)>;
def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)),
(DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>;
Add support for 64-bit set-on-less-than instructions. llvm-svn: 141695
2011-10-12 02:53:46 +08:00
Add an option to use a virtual register as the global base register instead of reserving a physical register ($gp or $28) for that purpose. This will completely eliminate loads that restore the value of $gp after every function call, if the register allocator assigns a callee-saved register, or eliminate unnecessary loads if it assigns a temporary register. example: .cpload $25 // set $gp. ... .cprestore 16 // store $gp to stack slot 16($sp). ... jalr $25 // function call. clobbers $gp. lw $gp, 16($sp) // not emitted if callee-saved reg is chosen. ... lw $2, 4($gp) ... jalr $25 // function call. lw $gp, 16($sp) // not emitted if $gp is not live after this instruction. ... llvm-svn: 151402
2012-02-25 06:34:47 +08:00
def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>;
def : WrapperPat<tconstpool, DADDiu, CPU64Regs>;
def : WrapperPat<texternalsym, DADDiu, CPU64Regs>;
def : WrapperPat<tblockaddress, DADDiu, CPU64Regs>;
def : WrapperPat<tjumptable, DADDiu, CPU64Regs>;
def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>;
64-bit WrapperPICPat patterns. llvm-svn: 146086
2011-12-08 06:11:43 +08:00
Add patterns for conditional branches with 64-bit register operands. llvm-svn: 141696
2011-10-12 03:09:09 +08:00
defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
ZERO_64>;
Add support for 64-bit set-on-less-than instructions. llvm-svn: 141695
2011-10-12 02:53:46 +08:00
// setcc patterns
Change the names of 64-bit logical instructions so that they match the names of the real instructions. llvm-svn: 141718
2011-10-12 05:48:01 +08:00
defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>;
Remove redundancy in setcc patterns using multiclass. llvm-svn: 141715
2011-10-12 05:40:01 +08:00
defm : SetlePats<CPU64Regs, SLT64, SLTu64>;
defm : SetgtPats<CPU64Regs, SLT64, SLTu64>;
defm : SetgePats<CPU64Regs, SLT64, SLTu64>;
defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>;
Add 64-bit to 32-bit trunc pattern. llvm-svn: 143988
2011-11-08 02:57:41 +08:00
// truncate
1. introduce MipsPat in place of Pat in order to exclude those from being used by Mips16 or Micro Mips 2. clean up a few lines too long encountered Patch by Reed Kotler. llvm-svn: 158470
2012-06-15 05:03:23 +08:00
def : MipsPat<(i32 (trunc CPU64Regs:$src)),
(SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>,
[mips] Shorten predicate name. llvm-svn: 169579
2012-12-07 11:06:09 +08:00
Requires<[IsN64, HasStdEnc]>;
remove blanks, and some code format llvm-svn: 151625
2012-02-28 15:46:26 +08:00
32 to 64-bit zext pattern. llvm-svn: 146096
2011-12-08 07:14:41 +08:00
// 32-to-64-bit extension
1. introduce MipsPat in place of Pat in order to exclude those from being used by Mips16 or Micro Mips 2. clean up a few lines too long encountered Patch by Reed Kotler. llvm-svn: 158470
2012-06-15 05:03:23 +08:00
def : MipsPat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
def : MipsPat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>;
def : MipsPat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
32-to-64-bit sign extension pattern. llvm-svn: 146995
2011-12-21 06:06:20 +08:00
32-to-64-bit sext_inreg pattern. llvm-svn: 147004
2011-12-21 06:40:40 +08:00
// Sign extend in register
1. introduce MipsPat in place of Pat in order to exclude those from being used by Mips16 or Micro Mips 2. clean up a few lines too long encountered Patch by Reed Kotler. llvm-svn: 158470
2012-06-15 05:03:23 +08:00
def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)),
(SLL64_64 CPU64Regs:$src)>;
32-to-64-bit sext_inreg pattern. llvm-svn: 147004
2011-12-21 06:40:40 +08:00
1. introduce MipsPat in place of Pat in order to exclude those from being used by Mips16 or Micro Mips 2. clean up a few lines too long encountered Patch by Reed Kotler. llvm-svn: 158470
2012-06-15 05:03:23 +08:00
// bswap MipsPattern
def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>;
Improvements to MIPS64 assembler: - Teach it about dadd[i] instructions and move pseudo-instruction - Make it parse the register names correctly (for N32 / N64) llvm-svn: 165506
2012-10-10 00:27:43 +08:00
[mips] Fix definitions of multiply, multiply-add/sub and divide instructions. The new instructions have explicit register output operands and use table-gen patterns instead of C++ code to do instruction selection. Mips16's instructions are unaffected by this change. llvm-svn: 178403
2013-03-30 09:36:35 +08:00
// mflo/hi patterns.
def : MipsPat<(i64 (ExtractLOHI ACRegs128:$ac, imm:$lohi_idx)),
(EXTRACT_SUBREG ACRegs128:$ac, imm:$lohi_idx)>;
Improvements to MIPS64 assembler: - Teach it about dadd[i] instructions and move pseudo-instruction - Make it parse the register names correctly (for N32 / N64) llvm-svn: 165506
2012-10-10 00:27:43 +08:00
//===----------------------------------------------------------------------===//
// Instruction aliases
//===----------------------------------------------------------------------===//
This patch that sets the EmitAlias flag in td files and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic llvm-svn: 174358
2013-02-05 16:32:10 +08:00
def : InstAlias<"move $dst, $src",
(DADDu CPU64RegsOpnd:$dst, CPU64RegsOpnd:$src, ZERO_64), 1>,
Requires<[HasMips64]>;
def : InstAlias<"move $dst, $src",
[mips] Print move instructions. "move $4, $5" is printed instead of "or $4, $5, $zero". llvm-svn: 176455
2013-03-05 06:25:01 +08:00
(OR64 CPU64RegsOpnd:$dst, CPU64RegsOpnd:$src, ZERO_64), 1>,
This is a resubmittal. For some reason it broke the bots yesterday but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Removal of redundant code and formatting fixes. Contributers: Jack Carter/Vladimir Medic llvm-svn: 172842
2013-01-19 04:15:06 +08:00
Requires<[HasMips64]>;
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
def : InstAlias<"and $rs, $rt, $imm",
This patch that sets the EmitAlias flag in td files and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic llvm-svn: 174358
2013-02-05 16:32:10 +08:00
(DANDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm),
1>,
This is a resubmittal. For some reason it broke the bots yesterday but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Removal of redundant code and formatting fixes. Contributers: Jack Carter/Vladimir Medic llvm-svn: 172842
2013-01-19 04:15:06 +08:00
Requires<[HasMips64]>;
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
def : InstAlias<"slt $rs, $rt, $imm",
This patch that sets the EmitAlias flag in td files and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic llvm-svn: 174358
2013-02-05 16:32:10 +08:00
(SLTi64 CPURegsOpnd:$rs, CPU64Regs:$rt, simm16_64:$imm), 1>,
This is a resubmittal. For some reason it broke the bots yesterday but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Removal of redundant code and formatting fixes. Contributers: Jack Carter/Vladimir Medic llvm-svn: 172842
2013-01-19 04:15:06 +08:00
Requires<[HasMips64]>;
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
def : InstAlias<"xor $rs, $rt, $imm",
This patch that sets the EmitAlias flag in td files and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic llvm-svn: 174358
2013-02-05 16:32:10 +08:00
(XORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm),
1>,
This is a resubmittal. For some reason it broke the bots yesterday but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Removal of redundant code and formatting fixes. Contributers: Jack Carter/Vladimir Medic llvm-svn: 172842
2013-01-19 04:15:06 +08:00
Requires<[HasMips64]>;
def : InstAlias<"not $rt, $rs",
This patch that sets the EmitAlias flag in td files and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic llvm-svn: 174358
2013-02-05 16:32:10 +08:00
(NOR64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rs, ZERO_64), 1>,
This is a resubmittal. For some reason it broke the bots yesterday but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Removal of redundant code and formatting fixes. Contributers: Jack Carter/Vladimir Medic llvm-svn: 172842
2013-01-19 04:15:06 +08:00
Requires<[HasMips64]>;
This patch that sets the EmitAlias flag in td files and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic llvm-svn: 174358
2013-02-05 16:32:10 +08:00
def : InstAlias<"j $rs", (JR64 CPU64Regs:$rs), 0>, Requires<[HasMips64]>;
[mips] Add definition of JALR instruction which has two register operands. Change the original JALR instruction with one register operand to be a pseudo-instruction. llvm-svn: 174657
2013-02-08 03:48:00 +08:00
def : InstAlias<"jalr $rs", (JALR64 RA_64, CPU64Regs:$rs)>,
Requires<[HasMips64]>;
[Mips Assembler] Add alias definitions for jal Mips assembler allows following to be used as aliased instructions: jal $rs for jalr $rs jal $rd,$rd for jalr $rd,$rs This patch provides alias definitions in td files and test cases to show the usage. Contributer: Vladimir Medic llvm-svn: 178304
2013-03-29 07:02:21 +08:00
def : InstAlias<"jal $rs", (JALR64 RA_64, CPU64Regs:$rs), 0>,
Requires<[HasMips64]>;
def : InstAlias<"jal $rd,$rs", (JALR64 CPU64Regs:$rd, CPU64Regs:$rs), 0>,
Requires<[HasMips64]>;
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
def : InstAlias<"daddu $rs, $rt, $imm",
This patch that sets the EmitAlias flag in td files and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic llvm-svn: 174358
2013-02-05 16:32:10 +08:00
(DADDiu CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm),
1>;
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
def : InstAlias<"dadd $rs, $rt, $imm",
This patch that sets the EmitAlias flag in td files and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic llvm-svn: 174358
2013-02-05 16:32:10 +08:00
(DADDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm),
1>;
[Mips Assembler] Add support for OR macro with imediate opperand Mips assembler supports macros that allows the OR instruction to have an immediate parameter. This patch adds an instruction alias that converts this macro into a Mips ORI instruction. Contributer: Vladimir Medic llvm-svn: 178316
2013-03-29 07:45:13 +08:00
def : InstAlias<"or $rs, $rt, $imm",
(ORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm),
1>, Requires<[HasMips64]>;
Expose move to/from coprocessor instructions in MIPS64 mode. Note: [D]M{T,F}CP2 is just a recommended encoding. Vendors often provide a custom CP2 that interprets instructions differently and may wish to add their own instructions that use this opcode. We should ensure that this is easy to do. I will probably add a 'has custom CP{0-3}' subtarget flag to make this easy: We want to avoid the GCC situation where every MIPS vendor makes a custom fork that breaks every other MIPS CPU and so can't be merged upstream. llvm-svn: 165711
2012-10-11 18:21:34 +08:00
/// Move between CPU and coprocessor registers
This is a resubmittal. For some reason it broke the bots yesterday but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Removal of redundant code and formatting fixes. Contributers: Jack Carter/Vladimir Medic llvm-svn: 172842
2013-01-19 04:15:06 +08:00
Expose move to/from coprocessor instructions in MIPS64 mode. Note: [D]M{T,F}CP2 is just a recommended encoding. Vendors often provide a custom CP2 that interprets instructions differently and may wish to add their own instructions that use this opcode. We should ensure that this is easy to do. I will probably add a 'has custom CP{0-3}' subtarget flag to make this easy: We want to avoid the GCC situation where every MIPS vendor makes a custom fork that breaks every other MIPS CPU and so can't be merged upstream. llvm-svn: 165711
2012-10-11 18:21:34 +08:00
let DecoderNamespace = "Mips64" in {
This is a resubmittal. For some reason it broke the bots yesterday but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Removal of redundant code and formatting fixes. Contributers: Jack Carter/Vladimir Medic llvm-svn: 172842
2013-01-19 04:15:06 +08:00
def DMFC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt),
(ins CPU64RegsOpnd:$rd, uimm16:$sel),
[mips] Refactor instructions which move data from or to coprocessors. llvm-svn: 171510
2013-01-05 03:13:49 +08:00
"dmfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 1>;
This is a resubmittal. For some reason it broke the bots yesterday but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Removal of redundant code and formatting fixes. Contributers: Jack Carter/Vladimir Medic llvm-svn: 172842
2013-01-19 04:15:06 +08:00
def DMTC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel),
(ins CPU64RegsOpnd:$rt),
[mips] Refactor instructions which move data from or to coprocessors. llvm-svn: 171510
2013-01-05 03:13:49 +08:00
"dmtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 5>;
This is a resubmittal. For some reason it broke the bots yesterday but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Removal of redundant code and formatting fixes. Contributers: Jack Carter/Vladimir Medic llvm-svn: 172842
2013-01-19 04:15:06 +08:00
def DMFC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt),
(ins CPU64RegsOpnd:$rd, uimm16:$sel),
[mips] Refactor instructions which move data from or to coprocessors. llvm-svn: 171510
2013-01-05 03:13:49 +08:00
"dmfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 1>;
This is a resubmittal. For some reason it broke the bots yesterday but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Removal of redundant code and formatting fixes. Contributers: Jack Carter/Vladimir Medic llvm-svn: 172842
2013-01-19 04:15:06 +08:00
def DMTC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel),
(ins CPU64RegsOpnd:$rt),
[mips] Refactor instructions which move data from or to coprocessors. llvm-svn: 171510
2013-01-05 03:13:49 +08:00
"dmtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 5>;
Expose move to/from coprocessor instructions in MIPS64 mode. Note: [D]M{T,F}CP2 is just a recommended encoding. Vendors often provide a custom CP2 that interprets instructions differently and may wish to add their own instructions that use this opcode. We should ensure that this is easy to do. I will probably add a 'has custom CP{0-3}' subtarget flag to make this easy: We want to avoid the GCC situation where every MIPS vendor makes a custom fork that breaks every other MIPS CPU and so can't be merged upstream. llvm-svn: 165711
2012-10-11 18:21:34 +08:00
}
This is a resubmittal. For some reason it broke the bots yesterday but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Removal of redundant code and formatting fixes. Contributers: Jack Carter/Vladimir Medic llvm-svn: 172842
2013-01-19 04:15:06 +08:00
Expose move to/from coprocessor instructions in MIPS64 mode. Note: [D]M{T,F}CP2 is just a recommended encoding. Vendors often provide a custom CP2 that interprets instructions differently and may wish to add their own instructions that use this opcode. We should ensure that this is easy to do. I will probably add a 'has custom CP{0-3}' subtarget flag to make this easy: We want to avoid the GCC situation where every MIPS vendor makes a custom fork that breaks every other MIPS CPU and so can't be merged upstream. llvm-svn: 165711
2012-10-11 18:21:34 +08:00
// Two operand (implicit 0 selector) versions:
[mips] 80 columns. llvm-svn: 171515
2013-01-05 03:38:05 +08:00
def : InstAlias<"dmfc0 $rt, $rd",
This patch that sets the EmitAlias flag in td files and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic llvm-svn: 174358
2013-02-05 16:32:10 +08:00
(DMFC0_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0), 0>;
[mips] 80 columns. llvm-svn: 171515
2013-01-05 03:38:05 +08:00
def : InstAlias<"dmtc0 $rt, $rd",
This patch that sets the EmitAlias flag in td files and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic llvm-svn: 174358
2013-02-05 16:32:10 +08:00
(DMTC0_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt), 0>;
[mips] 80 columns. llvm-svn: 171515
2013-01-05 03:38:05 +08:00
def : InstAlias<"dmfc2 $rt, $rd",
This patch that sets the EmitAlias flag in td files and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic llvm-svn: 174358
2013-02-05 16:32:10 +08:00
(DMFC2_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0), 0>;
[mips] 80 columns. llvm-svn: 171515
2013-01-05 03:38:05 +08:00
def : InstAlias<"dmtc2 $rt, $rd",
This patch that sets the EmitAlias flag in td files and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic llvm-svn: 174358
2013-02-05 16:32:10 +08:00
(DMTC2_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt), 0>;
Expose move to/from coprocessor instructions in MIPS64 mode. Note: [D]M{T,F}CP2 is just a recommended encoding. Vendors often provide a custom CP2 that interprets instructions differently and may wish to add their own instructions that use this opcode. We should ensure that this is easy to do. I will probably add a 'has custom CP{0-3}' subtarget flag to make this easy: We want to avoid the GCC situation where every MIPS vendor makes a custom fork that breaks every other MIPS CPU and so can't be merged upstream. llvm-svn: 165711
2012-10-11 18:21:34 +08:00