2014-04-23 16:57:09 +08:00
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//=- X86ScheduleSLM.td - X86 Silvermont Scheduling -----------*- tablegen -*-=//
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2013-09-14 03:23:28 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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2014-04-23 18:20:31 +08:00
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// This file defines the machine model for Intel Silvermont to support
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2014-04-23 16:57:09 +08:00
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// instruction scheduling and other instruction cost heuristics.
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2013-09-14 03:23:28 +08:00
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//
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//===----------------------------------------------------------------------===//
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2014-04-23 16:57:09 +08:00
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def SLMModel : SchedMachineModel {
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// All x86 instructions are modeled as a single micro-op, and SLM can decode 2
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// instructions per cycle.
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let IssueWidth = 2;
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let MicroOpBufferSize = 32; // Based on the reorder buffer.
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let LoadLatency = 3;
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let MispredictPenalty = 10;
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2014-07-16 06:39:58 +08:00
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let PostRAScheduler = 1;
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2014-04-23 16:57:09 +08:00
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2014-05-08 17:14:44 +08:00
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// For small loops, expand by a small factor to hide the backedge cost.
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let LoopMicroOpBufferSize = 10;
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2017-12-13 00:12:53 +08:00
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// FIXME: SSE4 is unimplemented. This flag is set to allow
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// the scheduler to assign a default model to unrecognized opcodes.
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let CompleteModel = 0;
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2014-04-23 16:57:09 +08:00
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}
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2013-09-14 03:23:28 +08:00
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2014-04-23 16:57:09 +08:00
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let SchedModel = SLMModel in {
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2014-04-23 18:20:31 +08:00
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// Silvermont has 5 reservation stations for micro-ops
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2018-03-25 09:28:43 +08:00
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def SLM_IEC_RSV0 : ProcResource<1>;
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def SLM_IEC_RSV1 : ProcResource<1>;
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def SLM_FPC_RSV0 : ProcResource<1> { let BufferSize = 1; }
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def SLM_FPC_RSV1 : ProcResource<1> { let BufferSize = 1; }
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def SLM_MEC_RSV : ProcResource<1>;
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2014-04-23 16:57:09 +08:00
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// Many micro-ops are capable of issuing on multiple ports.
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2018-03-25 09:28:43 +08:00
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def SLM_IEC_RSV01 : ProcResGroup<[SLM_IEC_RSV0, SLM_IEC_RSV1]>;
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def SLM_FPC_RSV01 : ProcResGroup<[SLM_FPC_RSV0, SLM_FPC_RSV1]>;
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2014-04-23 16:57:09 +08:00
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2018-03-25 09:28:43 +08:00
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def SLMDivider : ProcResource<1>;
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def SLMFPMultiplier : ProcResource<1>;
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def SLMFPDivider : ProcResource<1>;
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2014-04-23 16:57:09 +08:00
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// Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3
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// cycles after the memory operand.
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def : ReadAdvance<ReadAfterLd, 3>;
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// Many SchedWrites are defined in pairs with and without a folded load.
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// Instructions with folded loads are usually micro-fused, so they only appear
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// as two micro-ops when queued in the reservation station.
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// This multiclass defines the resource usage for variants with and without
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// folded loads.
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2018-03-25 09:28:43 +08:00
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multiclass SLMWriteResPair<X86FoldableSchedWrite SchedRW,
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list<ProcResourceKind> ExePorts,
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int Lat, list<int> Res = [1], int UOps = 1,
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int LoadLat = 3> {
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2014-04-23 16:57:09 +08:00
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// Register variant is using a single cycle on ExePort.
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2018-03-19 22:46:07 +08:00
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def : WriteRes<SchedRW, ExePorts> {
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let Latency = Lat;
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let ResourceCycles = Res;
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let NumMicroOps = UOps;
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}
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2014-04-23 16:57:09 +08:00
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2018-03-25 18:21:19 +08:00
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// Memory variant also uses a cycle on MEC_RSV and adds LoadLat cycles to
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// the latency (default = 3).
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2018-03-25 09:28:43 +08:00
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def : WriteRes<SchedRW.Folded, !listconcat([SLM_MEC_RSV], ExePorts)> {
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2018-03-25 18:21:19 +08:00
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let Latency = !add(Lat, LoadLat);
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2018-03-19 22:46:07 +08:00
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let ResourceCycles = !listconcat([1], Res);
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let NumMicroOps = UOps;
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2014-04-23 16:57:09 +08:00
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}
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}
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2013-09-14 03:23:28 +08:00
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2014-04-23 16:57:09 +08:00
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// A folded store needs a cycle on MEC_RSV for the store data, but it does not
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// need an extra port cycle to recompute the address.
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2018-03-25 09:28:43 +08:00
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def : WriteRes<WriteRMW, [SLM_MEC_RSV]>;
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2014-04-23 16:57:09 +08:00
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2018-03-25 09:28:43 +08:00
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def : WriteRes<WriteStore, [SLM_IEC_RSV01, SLM_MEC_RSV]>;
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def : WriteRes<WriteLoad, [SLM_MEC_RSV]> { let Latency = 3; }
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def : WriteRes<WriteMove, [SLM_IEC_RSV01]>;
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2014-04-23 16:57:09 +08:00
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def : WriteRes<WriteZero, []>;
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2018-04-22 02:07:36 +08:00
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// Load/store MXCSR.
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// FIXME: These are probably wrong. They are copy pasted from WriteStore/Load.
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def : WriteRes<WriteSTMXCSR, [SLM_IEC_RSV01, SLM_MEC_RSV]>;
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def : WriteRes<WriteLDMXCSR, [SLM_MEC_RSV]> { let Latency = 3; }
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2017-12-10 20:36:29 +08:00
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// Treat misc copies as a move.
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def : InstRW<[WriteMove], (instrs COPY)>;
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2018-03-25 09:28:43 +08:00
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defm : SLMWriteResPair<WriteALU, [SLM_IEC_RSV01], 1>;
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defm : SLMWriteResPair<WriteIMul, [SLM_IEC_RSV1], 3>;
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defm : SLMWriteResPair<WriteShift, [SLM_IEC_RSV0], 1>;
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2018-03-27 05:06:14 +08:00
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defm : SLMWriteResPair<WriteJump, [SLM_IEC_RSV1], 1>;
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defm : SLMWriteResPair<WriteCRC32, [SLM_IEC_RSV1], 3>;
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2014-04-23 16:57:09 +08:00
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2018-04-18 14:04:30 +08:00
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defm : SLMWriteResPair<WriteCMOV, [SLM_IEC_RSV01], 2, [2]>;
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2018-04-09 01:53:18 +08:00
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def : WriteRes<WriteSETCC, [SLM_IEC_RSV01]>;
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def : WriteRes<WriteSETCCStore, [SLM_IEC_RSV01, SLM_MEC_RSV]> {
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// FIXME Latency and NumMicrOps?
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let ResourceCycles = [2,1];
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}
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2014-04-23 16:57:09 +08:00
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// This is for simple LEAs with one or two input operands.
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// The complex ones can only execute on port 1, and they require two cycles on
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// the port to read all inputs. We don't model that.
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2018-03-25 09:28:43 +08:00
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def : WriteRes<WriteLEA, [SLM_IEC_RSV1]>;
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2014-04-23 16:57:09 +08:00
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2018-03-27 02:19:28 +08:00
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// Bit counts.
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defm : SLMWriteResPair<WriteBitScan, [SLM_IEC_RSV01], 10, [20], 10>;
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defm : SLMWriteResPair<WriteLZCNT, [SLM_IEC_RSV0], 3>;
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defm : SLMWriteResPair<WriteTZCNT, [SLM_IEC_RSV0], 3>;
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defm : SLMWriteResPair<WritePOPCNT, [SLM_IEC_RSV0], 3>;
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2018-03-30 04:41:39 +08:00
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// BMI1 BEXTR, BMI2 BZHI
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// NOTE: These don't exist on Silvermont. Ports are guesses.
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2018-04-20 02:01:52 +08:00
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defm : SLMWriteResPair<WriteBEXTR, [SLM_IEC_RSV0], 1>;
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defm : SLMWriteResPair<WriteBZHI, [SLM_IEC_RSV0], 1>;
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2018-03-30 04:41:39 +08:00
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2014-04-23 16:57:09 +08:00
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// This is quite rough, latency depends on the dividend.
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2018-03-26 04:16:53 +08:00
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defm : SLMWriteResPair<WriteIDiv, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
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2013-09-14 03:23:28 +08:00
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2014-04-23 16:57:09 +08:00
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// Scalar and vector floating point.
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2018-03-25 09:28:43 +08:00
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def : WriteRes<WriteFStore, [SLM_FPC_RSV01, SLM_MEC_RSV]>;
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def : WriteRes<WriteFLoad, [SLM_MEC_RSV]> { let Latency = 3; }
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def : WriteRes<WriteFMove, [SLM_FPC_RSV01]>;
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defm : SLMWriteResPair<WriteFAdd, [SLM_FPC_RSV1], 3>;
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2018-04-17 15:22:44 +08:00
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defm : SLMWriteResPair<WriteFCmp, [SLM_FPC_RSV1], 3>;
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defm : SLMWriteResPair<WriteFCom, [SLM_FPC_RSV1], 3>;
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2018-03-25 09:28:43 +08:00
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defm : SLMWriteResPair<WriteFMul, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;
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defm : SLMWriteResPair<WriteFDiv, [SLM_FPC_RSV0, SLMFPDivider], 34, [1,34]>;
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defm : SLMWriteResPair<WriteFRcp, [SLM_FPC_RSV0], 5>;
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defm : SLMWriteResPair<WriteFRsqrt, [SLM_FPC_RSV0], 5>;
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defm : SLMWriteResPair<WriteFSqrt, [SLM_FPC_RSV0], 15>;
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defm : SLMWriteResPair<WriteCvtF2I, [SLM_FPC_RSV01], 4>;
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defm : SLMWriteResPair<WriteCvtI2F, [SLM_FPC_RSV01], 4>;
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defm : SLMWriteResPair<WriteCvtF2F, [SLM_FPC_RSV01], 4>;
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2018-04-21 05:16:05 +08:00
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defm : SLMWriteResPair<WriteFSign, [SLM_FPC_RSV01], 1>;
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defm : SLMWriteResPair<WriteFLogic, [SLM_FPC_RSV01], 1>;
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2018-04-27 23:50:33 +08:00
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defm : SLMWriteResPair<WriteFLogicY, [SLM_FPC_RSV01], 1>;
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2018-03-25 09:28:43 +08:00
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defm : SLMWriteResPair<WriteFShuffle, [SLM_FPC_RSV0], 1>;
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2018-04-11 21:49:19 +08:00
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defm : SLMWriteResPair<WriteFVarShuffle, [SLM_FPC_RSV0], 1>;
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2018-04-28 02:19:48 +08:00
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defm : SLMWriteResPair<WriteFVarShuffleY,[SLM_FPC_RSV0], 1>;
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2018-03-25 09:28:43 +08:00
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defm : SLMWriteResPair<WriteFBlend, [SLM_FPC_RSV0], 1>;
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2018-04-25 00:43:07 +08:00
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def : WriteRes<WriteCvtF2FSt, [SLM_FPC_RSV01, SLM_MEC_RSV]>;
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2013-09-14 03:23:28 +08:00
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2014-04-23 16:57:09 +08:00
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// Vector integer operations.
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2018-03-25 09:28:43 +08:00
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def : WriteRes<WriteVecStore, [SLM_FPC_RSV01, SLM_MEC_RSV]>;
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def : WriteRes<WriteVecLoad, [SLM_MEC_RSV]> { let Latency = 3; }
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def : WriteRes<WriteVecMove, [SLM_FPC_RSV01]>;
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defm : SLMWriteResPair<WriteVecShift, [SLM_FPC_RSV0], 1>;
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defm : SLMWriteResPair<WriteVecLogic, [SLM_FPC_RSV01], 1>;
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2018-05-01 20:39:17 +08:00
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defm : SLMWriteResPair<WriteVecLogicY,[SLM_FPC_RSV01], 1>;
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2018-03-25 09:28:43 +08:00
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defm : SLMWriteResPair<WriteVecALU, [SLM_FPC_RSV01], 1>;
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defm : SLMWriteResPair<WriteVecIMul, [SLM_FPC_RSV0], 4>;
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2018-04-10 01:07:40 +08:00
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// FIXME: The below is closer to correct, but caused some perf regressions.
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//defm : SLMWriteResPair<WritePMULLD, [SLM_FPC_RSV0], 11, [11], 7>;
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defm : SLMWriteResPair<WritePMULLD, [SLM_FPC_RSV0], 4>;
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2018-03-25 09:28:43 +08:00
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defm : SLMWriteResPair<WriteShuffle, [SLM_FPC_RSV0], 1>;
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2018-04-11 21:49:19 +08:00
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defm : SLMWriteResPair<WriteVarShuffle, [SLM_FPC_RSV0], 1>;
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2018-03-25 09:28:43 +08:00
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defm : SLMWriteResPair<WriteBlend, [SLM_FPC_RSV0], 1>;
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defm : SLMWriteResPair<WriteMPSAD, [SLM_FPC_RSV0], 7>;
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2018-04-18 03:35:19 +08:00
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defm : SLMWriteResPair<WritePSADBW, [SLM_FPC_RSV0], 4>;
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2018-04-25 02:49:25 +08:00
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defm : SLMWriteResPair<WritePHMINPOS, [SLM_FPC_RSV0], 4>;
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2014-04-23 16:57:09 +08:00
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2018-04-24 21:21:41 +08:00
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// Vector insert/extract operations.
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defm : SLMWriteResPair<WriteVecInsert, [SLM_FPC_RSV0], 1>;
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def : WriteRes<WriteVecExtract, [SLM_FPC_RSV0]>;
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def : WriteRes<WriteVecExtractSt, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
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let Latency = 4;
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let NumMicroOps = 2;
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let ResourceCycles = [1, 2];
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}
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2017-06-09 00:44:13 +08:00
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////////////////////////////////////////////////////////////////////////////////
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// Horizontal add/sub instructions.
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////////////////////////////////////////////////////////////////////////////////
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2018-03-25 09:28:43 +08:00
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defm : SLMWriteResPair<WriteFHAdd, [SLM_FPC_RSV01], 3, [2]>;
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2018-04-28 00:11:57 +08:00
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defm : SLMWriteResPair<WriteFHAddY, [SLM_FPC_RSV01], 3, [2]>;
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2018-03-25 09:28:43 +08:00
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defm : SLMWriteResPair<WritePHAdd, [SLM_FPC_RSV01], 1>;
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2017-06-09 00:44:13 +08:00
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2014-04-23 16:57:09 +08:00
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// String instructions.
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// Packed Compare Implicit Length Strings, Return Mask
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2018-03-25 09:28:43 +08:00
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def : WriteRes<WritePCmpIStrM, [SLM_FPC_RSV0]> {
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2014-04-23 16:57:09 +08:00
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let Latency = 13;
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let ResourceCycles = [13];
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}
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2018-03-25 09:28:43 +08:00
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def : WriteRes<WritePCmpIStrMLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
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2014-04-23 16:57:09 +08:00
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let Latency = 13;
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let ResourceCycles = [13, 1];
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}
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2013-09-14 03:23:28 +08:00
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2014-04-23 16:57:09 +08:00
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// Packed Compare Explicit Length Strings, Return Mask
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2018-03-25 09:28:43 +08:00
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def : WriteRes<WritePCmpEStrM, [SLM_FPC_RSV0]> {
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2014-04-23 16:57:09 +08:00
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let Latency = 17;
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let ResourceCycles = [17];
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}
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2018-03-25 09:28:43 +08:00
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def : WriteRes<WritePCmpEStrMLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
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2014-04-23 16:57:09 +08:00
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let Latency = 17;
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let ResourceCycles = [17, 1];
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}
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2013-09-14 03:23:28 +08:00
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2014-04-23 16:57:09 +08:00
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// Packed Compare Implicit Length Strings, Return Index
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2018-03-25 09:28:43 +08:00
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def : WriteRes<WritePCmpIStrI, [SLM_FPC_RSV0]> {
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2014-04-23 16:57:09 +08:00
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let Latency = 17;
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let ResourceCycles = [17];
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}
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2018-03-25 09:28:43 +08:00
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def : WriteRes<WritePCmpIStrILd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
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2014-04-23 16:57:09 +08:00
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let Latency = 17;
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let ResourceCycles = [17, 1];
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}
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2013-09-14 03:23:28 +08:00
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2014-04-23 16:57:09 +08:00
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// Packed Compare Explicit Length Strings, Return Index
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2018-03-25 09:28:43 +08:00
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def : WriteRes<WritePCmpEStrI, [SLM_FPC_RSV0]> {
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2014-04-23 16:57:09 +08:00
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let Latency = 21;
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let ResourceCycles = [21];
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}
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2018-03-25 09:28:43 +08:00
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def : WriteRes<WritePCmpEStrILd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
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2014-04-23 16:57:09 +08:00
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let Latency = 21;
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let ResourceCycles = [21, 1];
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}
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2013-09-14 03:23:28 +08:00
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2018-03-28 04:38:54 +08:00
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// MOVMSK Instructions.
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def : WriteRes<WriteFMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; }
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def : WriteRes<WriteVecMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; }
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def : WriteRes<WriteMMXMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; }
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2014-04-23 16:57:09 +08:00
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// AES Instructions.
|
2018-03-25 09:28:43 +08:00
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def : WriteRes<WriteAESDecEnc, [SLM_FPC_RSV0]> {
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2014-04-23 16:57:09 +08:00
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let Latency = 8;
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let ResourceCycles = [5];
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}
|
2018-03-25 09:28:43 +08:00
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def : WriteRes<WriteAESDecEncLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
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2014-04-23 16:57:09 +08:00
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let Latency = 8;
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let ResourceCycles = [5, 1];
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}
|
2013-09-14 03:23:28 +08:00
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2018-03-25 09:28:43 +08:00
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def : WriteRes<WriteAESIMC, [SLM_FPC_RSV0]> {
|
2014-04-23 16:57:09 +08:00
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let Latency = 8;
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let ResourceCycles = [5];
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}
|
2018-03-25 09:28:43 +08:00
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def : WriteRes<WriteAESIMCLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
|
2014-04-23 16:57:09 +08:00
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let Latency = 8;
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let ResourceCycles = [5, 1];
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}
|
2013-09-14 03:23:28 +08:00
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2018-03-25 09:28:43 +08:00
|
|
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def : WriteRes<WriteAESKeyGen, [SLM_FPC_RSV0]> {
|
2014-04-23 16:57:09 +08:00
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let Latency = 8;
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let ResourceCycles = [5];
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}
|
2018-03-25 09:28:43 +08:00
|
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def : WriteRes<WriteAESKeyGenLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
|
2014-04-23 16:57:09 +08:00
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let Latency = 8;
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let ResourceCycles = [5, 1];
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}
|
2013-09-14 03:23:28 +08:00
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2014-04-23 16:57:09 +08:00
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// Carry-less multiplication instructions.
|
2018-03-25 09:28:43 +08:00
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def : WriteRes<WriteCLMul, [SLM_FPC_RSV0]> {
|
2014-04-23 16:57:09 +08:00
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|
let Latency = 10;
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let ResourceCycles = [10];
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}
|
2018-03-25 09:28:43 +08:00
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def : WriteRes<WriteCLMulLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
|
2014-04-23 16:57:09 +08:00
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|
let Latency = 10;
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|
let ResourceCycles = [10, 1];
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|
}
|
2013-09-14 03:23:28 +08:00
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2018-03-25 09:28:43 +08:00
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def : WriteRes<WriteSystem, [SLM_FPC_RSV0]> { let Latency = 100; }
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def : WriteRes<WriteMicrocoded, [SLM_FPC_RSV0]> { let Latency = 100; }
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def : WriteRes<WriteFence, [SLM_MEC_RSV]>;
|
2014-04-23 16:57:09 +08:00
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def : WriteRes<WriteNop, []>;
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|
2017-11-27 18:41:32 +08:00
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|
// AVX/FMA is not supported on that architecture, but we should define the basic
|
2014-04-23 16:57:09 +08:00
|
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|
// scheduling resources anyway.
|
2018-03-25 09:28:43 +08:00
|
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|
def : WriteRes<WriteIMulH, [SLM_FPC_RSV0]>;
|
2018-04-28 02:19:48 +08:00
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|
defm : SLMWriteResPair<WriteFBlendY, [SLM_FPC_RSV0], 1>;
|
2018-03-25 09:28:43 +08:00
|
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|
defm : SLMWriteResPair<WriteVarBlend, [SLM_FPC_RSV0], 1>;
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|
defm : SLMWriteResPair<WriteFVarBlend, [SLM_FPC_RSV0], 1>;
|
2018-04-28 02:19:48 +08:00
|
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|
defm : SLMWriteResPair<WriteFVarBlendY, [SLM_FPC_RSV0], 1>;
|
2018-03-25 09:28:43 +08:00
|
|
|
defm : SLMWriteResPair<WriteFShuffle256, [SLM_FPC_RSV0], 1>;
|
2018-04-11 21:49:19 +08:00
|
|
|
defm : SLMWriteResPair<WriteFVarShuffle256, [SLM_FPC_RSV0], 1>;
|
2018-03-25 09:28:43 +08:00
|
|
|
defm : SLMWriteResPair<WriteShuffle256, [SLM_FPC_RSV0], 1>;
|
2018-04-11 21:49:19 +08:00
|
|
|
defm : SLMWriteResPair<WriteVarShuffle256, [SLM_FPC_RSV0], 1>;
|
2018-03-25 09:28:43 +08:00
|
|
|
defm : SLMWriteResPair<WriteVarVecShift, [SLM_FPC_RSV0], 1>;
|
|
|
|
defm : SLMWriteResPair<WriteFMA, [SLM_FPC_RSV0], 1>;
|
2018-04-25 21:07:58 +08:00
|
|
|
defm : SLMWriteResPair<WriteFMAS, [SLM_FPC_RSV0], 1>;
|
|
|
|
defm : SLMWriteResPair<WriteFMAY, [SLM_FPC_RSV0], 1>;
|
2018-04-02 14:34:16 +08:00
|
|
|
|
|
|
|
// Instruction overrides
|
|
|
|
|
|
|
|
def SLMriteResGroup1 : SchedWriteRes<[SLM_FPC_RSV0,SLMFPDivider]> {
|
|
|
|
let Latency = 69;
|
|
|
|
let NumMicroOps = 1;
|
|
|
|
let ResourceCycles = [1,69];
|
|
|
|
}
|
|
|
|
def: InstRW<[SLMriteResGroup1], (instregex "(V?)DIVPDrr")>;
|
|
|
|
|
|
|
|
def SLMriteResGroup2 : SchedWriteRes<[SLM_FPC_RSV0,SLMFPDivider]> {
|
|
|
|
let Latency = 39;
|
|
|
|
let NumMicroOps = 1;
|
|
|
|
let ResourceCycles = [1,39];
|
|
|
|
}
|
|
|
|
def: InstRW<[SLMriteResGroup2], (instregex "(V?)DIVPSrr")>;
|
|
|
|
|
|
|
|
def SLMriteResGroup3 : SchedWriteRes<[SLM_FPC_RSV0,SLMFPDivider]> {
|
|
|
|
let Latency = 34;
|
|
|
|
let NumMicroOps = 1;
|
|
|
|
let ResourceCycles = [1,32];
|
|
|
|
}
|
|
|
|
def: InstRW<[SLMriteResGroup3], (instregex "(V?)DIVSDrr")>;
|
|
|
|
|
|
|
|
def SLMriteResGroup4 : SchedWriteRes<[SLM_FPC_RSV0,SLMFPDivider]> {
|
|
|
|
let Latency = 19;
|
|
|
|
let NumMicroOps = 1;
|
|
|
|
let ResourceCycles = [1,17];
|
|
|
|
}
|
|
|
|
def: InstRW<[SLMriteResGroup4], (instregex "(V?)DIVSSrr")>;
|
|
|
|
|
|
|
|
def SLMriteResGroup5 : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV0,SLMFPDivider]> {
|
|
|
|
let Latency = 72;
|
|
|
|
let NumMicroOps = 1;
|
|
|
|
let ResourceCycles = [1,1,69];
|
|
|
|
}
|
|
|
|
def: InstRW<[SLMriteResGroup5], (instregex "(V?)DIVPDrm")>;
|
|
|
|
|
|
|
|
def SLMriteResGroup6 : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV0,SLMFPDivider]> {
|
|
|
|
let Latency = 42;
|
|
|
|
let NumMicroOps = 1;
|
|
|
|
let ResourceCycles = [1,1,39];
|
|
|
|
}
|
|
|
|
def: InstRW<[SLMriteResGroup6], (instregex "(V?)DIVPSrm")>;
|
|
|
|
|
|
|
|
def SLMriteResGroup7 : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV0,SLMFPDivider]> {
|
|
|
|
let Latency = 37;
|
|
|
|
let NumMicroOps = 1;
|
|
|
|
let ResourceCycles = [1,1,32];
|
|
|
|
}
|
|
|
|
def: InstRW<[SLMriteResGroup7], (instregex "(V?)DIVSDrm")>;
|
|
|
|
|
|
|
|
def SLMriteResGroup8 : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV0,SLMFPDivider]> {
|
|
|
|
let Latency = 22;
|
|
|
|
let NumMicroOps = 1;
|
|
|
|
let ResourceCycles = [1,1,17];
|
|
|
|
}
|
|
|
|
def: InstRW<[SLMriteResGroup8], (instregex "(V?)DIVSSrm")>;
|
|
|
|
|
|
|
|
def SLMriteResGroup9 : SchedWriteRes<[SLM_FPC_RSV0,SLMFPDivider]> {
|
|
|
|
let Latency = 71;
|
|
|
|
let NumMicroOps = 1;
|
|
|
|
let ResourceCycles = [1,70];
|
|
|
|
}
|
|
|
|
def: InstRW<[SLMriteResGroup9], (instregex "(V?)SQRTPDr")>;
|
|
|
|
|
|
|
|
def SLMriteResGroup10 : SchedWriteRes<[SLM_FPC_RSV0,SLMFPDivider]> {
|
|
|
|
let Latency = 41;
|
|
|
|
let NumMicroOps = 1;
|
|
|
|
let ResourceCycles = [1,40];
|
|
|
|
}
|
|
|
|
def: InstRW<[SLMriteResGroup10], (instregex "(V?)SQRTPSr")>;
|
|
|
|
|
|
|
|
def SLMriteResGroup11 : SchedWriteRes<[SLM_FPC_RSV0,SLMFPDivider]> {
|
|
|
|
let Latency = 35;
|
|
|
|
let NumMicroOps = 1;
|
|
|
|
let ResourceCycles = [1,35];
|
|
|
|
}
|
|
|
|
def: InstRW<[SLMriteResGroup11], (instregex "(V?)SQRTSDr")>;
|
|
|
|
|
|
|
|
def SLMriteResGroup12 : SchedWriteRes<[SLM_FPC_RSV0,SLMFPDivider]> {
|
|
|
|
let Latency = 20;
|
|
|
|
let NumMicroOps = 1;
|
|
|
|
let ResourceCycles = [1,20];
|
|
|
|
}
|
|
|
|
def: InstRW<[SLMriteResGroup12], (instregex "(V?)SQRTSSr")>;
|
|
|
|
|
|
|
|
def SLMriteResGroup13 : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV0,SLMFPDivider]> {
|
|
|
|
let Latency = 74;
|
|
|
|
let NumMicroOps = 1;
|
|
|
|
let ResourceCycles = [1,70];
|
|
|
|
}
|
|
|
|
def: InstRW<[SLMriteResGroup13], (instregex "(V?)SQRTPDm")>;
|
|
|
|
|
|
|
|
def SLMriteResGroup14 : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV0,SLMFPDivider]> {
|
|
|
|
let Latency = 44;
|
|
|
|
let NumMicroOps = 1;
|
|
|
|
let ResourceCycles = [1,1,40];
|
|
|
|
}
|
|
|
|
def: InstRW<[SLMriteResGroup14], (instregex "(V?)SQRTPSm")>;
|
|
|
|
|
|
|
|
def SLMriteResGroup15 : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV0,SLMFPDivider]> {
|
|
|
|
let Latency = 38;
|
|
|
|
let NumMicroOps = 1;
|
|
|
|
let ResourceCycles = [1,1,35];
|
|
|
|
}
|
|
|
|
def: InstRW<[SLMriteResGroup15], (instregex "(V?)SQRTSDm")>;
|
|
|
|
|
|
|
|
def SLMriteResGroup16 : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV0,SLMFPDivider]> {
|
|
|
|
let Latency = 23;
|
|
|
|
let NumMicroOps = 1;
|
|
|
|
let ResourceCycles = [1,1,20];
|
|
|
|
}
|
|
|
|
def: InstRW<[SLMriteResGroup16], (instregex "(V?)SQRTSSm")>;
|
|
|
|
|
2014-04-23 16:57:09 +08:00
|
|
|
} // SchedModel
|