2007-06-06 15:42:06 +08:00
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//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-06-06 15:42:06 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that Mips uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MipsISELLOWERING_H
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#define MipsISELLOWERING_H
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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#include "Mips.h"
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#include "MipsSubtarget.h"
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namespace llvm {
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namespace MipsISD {
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enum NodeType {
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// Start the numbering from where ISD NodeType finishes.
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2008-09-24 02:42:32 +08:00
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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2007-06-06 15:42:06 +08:00
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// Jump and link (call)
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JmpLink,
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// Get the Higher 16 bits from a 32-bit immediate
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// No relation with Mips Hi register
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Hi,
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// Get the Lower 16 bits from a 32-bit immediate
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// No relation with Mips Lo register
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Lo,
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2008-07-22 02:52:34 +08:00
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// Handle gp_rel (small data/bss sections) relocation.
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GPRel,
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2008-08-13 15:13:40 +08:00
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// Conditional Move
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CMov,
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2008-06-06 08:58:26 +08:00
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// Select CC Pseudo Instruction
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SelectCC,
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2008-07-30 03:05:28 +08:00
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// Floating Point Select CC Pseudo Instruction
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FPSelectCC,
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2008-07-09 12:45:36 +08:00
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// Floating Point Branch Conditional
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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FPBrcond,
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2008-07-09 12:45:36 +08:00
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// Floating Point Compare
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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FPCmp,
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2009-05-28 01:23:44 +08:00
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// Floating Point Rounding
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FPRound,
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2007-06-06 15:42:06 +08:00
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// Return
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2007-11-05 11:02:32 +08:00
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Ret
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2007-06-06 15:42:06 +08:00
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};
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}
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//===--------------------------------------------------------------------===//
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// TargetLowering Implementation
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//===--------------------------------------------------------------------===//
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class MipsTargetLowering : public TargetLowering
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{
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// FrameIndex for return slot.
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int ReturnAddrIndex;
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public:
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2007-08-03 05:21:54 +08:00
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explicit MipsTargetLowering(MipsTargetMachine &TM);
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2007-06-06 15:42:06 +08:00
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/// LowerOperation - Provide custom lowering hooks for some operations.
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2008-07-28 05:46:04 +08:00
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
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2007-06-06 15:42:06 +08:00
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/// getTargetNodeName - This method returns the name of a target specific
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// DAG node.
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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2008-03-10 23:42:14 +08:00
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/// getSetCCResultType - get the ISD::SETCC result ValueType
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2009-01-01 23:52:00 +08:00
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MVT getSetCCResultType(MVT VT) const;
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2008-03-10 23:42:14 +08:00
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2007-06-06 15:42:06 +08:00
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private:
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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// Subtarget Info
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const MipsSubtarget *Subtarget;
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2007-06-06 15:42:06 +08:00
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// Lower Operand helpers
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2008-09-13 09:54:27 +08:00
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SDNode *LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
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2007-06-06 15:42:06 +08:00
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unsigned CallingConv, SelectionDAG &DAG);
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2008-07-22 02:52:34 +08:00
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bool IsGlobalInSmallSection(GlobalValue *GV);
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2008-07-24 00:01:50 +08:00
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bool IsInSmallSection(unsigned Size);
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2007-06-06 15:42:06 +08:00
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// Lower Operand specifics
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2008-08-03 03:37:33 +08:00
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SDValue LowerANDOR(SDValue Op, SelectionDAG &DAG);
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2008-08-01 02:31:28 +08:00
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SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG);
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2008-07-28 05:46:04 +08:00
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SDValue LowerCALL(SDValue Op, SelectionDAG &DAG);
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2008-08-01 02:31:28 +08:00
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SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
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2008-08-08 03:08:11 +08:00
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SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG);
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2008-07-28 05:46:04 +08:00
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SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG);
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2009-05-28 01:23:44 +08:00
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SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG);
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2008-07-28 05:46:04 +08:00
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
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SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
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2008-08-01 02:31:28 +08:00
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SDValue LowerRET(SDValue Op, SelectionDAG &DAG);
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SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG);
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2008-07-29 03:11:24 +08:00
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
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2008-06-06 08:58:26 +08:00
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virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
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2009-02-08 00:15:20 +08:00
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MachineBasicBlock *MBB) const;
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2007-06-06 15:42:06 +08:00
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2007-08-22 00:09:25 +08:00
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// Inline asm support
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ConstraintType getConstraintType(const std::string &Constraint) const;
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint,
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2008-06-06 20:08:01 +08:00
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MVT VT) const;
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2007-08-22 00:09:25 +08:00
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std::vector<unsigned>
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getRegClassForInlineAsmConstraint(const std::string &Constraint,
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2008-06-06 20:08:01 +08:00
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MVT VT) const;
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Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)
This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.
This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.
Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.
The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.
llvm-svn: 57748
2008-10-18 10:06:02 +08:00
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virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
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2007-06-06 15:42:06 +08:00
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};
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}
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#endif // MipsISELLOWERING_H
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