forked from OSchip/llvm-project
122 lines
4.0 KiB
LLVM
122 lines
4.0 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown -mattr=+lwp | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=i686-unknown -mcpu=bdver1 | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=i686-unknown -mcpu=bdver2 | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=i686-unknown -mcpu=bdver3 | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=i686-unknown -mcpu=bdver4 | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+lwp | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver1 | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver2 | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver3 | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver4 | FileCheck %s --check-prefix=X64
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define void @test_llwpcb(i8 *%a0) nounwind {
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; X86-LABEL: test_llwpcb:
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; X86: # BB#0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: llwpcb %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test_llwpcb:
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; X64: # BB#0:
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; X64-NEXT: llwpcb %rdi
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; X64-NEXT: retq
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tail call void @llvm.x86.llwpcb(i8 *%a0)
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ret void
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}
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define i8* @test_slwpcb(i8 *%a0) nounwind {
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; X86-LABEL: test_slwpcb:
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; X86: # BB#0:
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; X86-NEXT: slwpcb %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test_slwpcb:
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; X64: # BB#0:
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; X64-NEXT: slwpcb %rax
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; X64-NEXT: retq
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%1 = tail call i8* @llvm.x86.slwpcb()
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ret i8 *%1
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}
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define i8 @test_lwpins32_rri(i32 %a0, i32 %a1) nounwind {
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; X86-LABEL: test_lwpins32_rri:
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; X86: # BB#0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: addl %ecx, %ecx
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; X86-NEXT: lwpins $-1985229329, %ecx, %eax # imm = 0x89ABCDEF
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; X86-NEXT: setb %al
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; X86-NEXT: retl
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;
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; X64-LABEL: test_lwpins32_rri:
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; X64: # BB#0:
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; X64-NEXT: addl %esi, %esi
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; X64-NEXT: lwpins $-1985229329, %esi, %edi # imm = 0x89ABCDEF
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; X64-NEXT: setb %al
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; X64-NEXT: retq
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%1 = add i32 %a1, %a1
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%2 = tail call i8 @llvm.x86.lwpins32(i32 %a0, i32 %1, i32 2309737967)
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ret i8 %2
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}
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define i8 @test_lwpins32_rmi(i32 %a0, i32 *%p1) nounwind {
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; X86-LABEL: test_lwpins32_rmi:
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; X86: # BB#0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: lwpins $1985229328, (%eax), %ecx # imm = 0x76543210
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; X86-NEXT: setb %al
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; X86-NEXT: retl
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;
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; X64-LABEL: test_lwpins32_rmi:
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; X64: # BB#0:
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; X64-NEXT: lwpins $1985229328, (%rsi), %edi # imm = 0x76543210
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; X64-NEXT: setb %al
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; X64-NEXT: retq
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%a1 = load i32, i32 *%p1
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%1 = tail call i8 @llvm.x86.lwpins32(i32 %a0, i32 %a1, i32 1985229328)
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ret i8 %1
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}
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define void @test_lwpval32_rri(i32 %a0, i32 %a1) nounwind {
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; X86-LABEL: test_lwpval32_rri:
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; X86: # BB#0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: addl %ecx, %ecx
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; X86-NEXT: lwpval $-19088744, %ecx, %eax # imm = 0xFEDCBA98
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; X86-NEXT: retl
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;
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; X64-LABEL: test_lwpval32_rri:
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; X64: # BB#0:
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; X64-NEXT: addl %esi, %esi
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; X64-NEXT: lwpval $-19088744, %esi, %edi # imm = 0xFEDCBA98
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; X64-NEXT: retq
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%1 = add i32 %a1, %a1
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tail call void @llvm.x86.lwpval32(i32 %a0, i32 %1, i32 4275878552)
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ret void
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}
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define void @test_lwpval32_rmi(i32 %a0, i32 *%p1) nounwind {
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; X86-LABEL: test_lwpval32_rmi:
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; X86: # BB#0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: lwpval $305419896, (%eax), %ecx # imm = 0x12345678
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; X86-NEXT: retl
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;
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; X64-LABEL: test_lwpval32_rmi:
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; X64: # BB#0:
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; X64-NEXT: lwpval $305419896, (%rsi), %edi # imm = 0x12345678
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; X64-NEXT: retq
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%a1 = load i32, i32 *%p1
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tail call void @llvm.x86.lwpval32(i32 %a0, i32 %a1, i32 305419896)
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ret void
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}
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declare void @llvm.x86.llwpcb(i8*) nounwind
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declare i8* @llvm.x86.slwpcb() nounwind
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declare i8 @llvm.x86.lwpins32(i32, i32, i32) nounwind
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declare void @llvm.x86.lwpval32(i32, i32, i32) nounwind
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