2020-01-28 07:11:45 +08:00
|
|
|
# RUN: llc -run-pass=aarch64-ldst-opt -mtriple=arm64-apple-iphoneos -verify-machineinstrs -aarch64-load-store-renaming=true -o - %s | FileCheck %s
|
2020-02-26 19:05:59 +08:00
|
|
|
# RUN: llc -run-pass=aarch64-ldst-opt -mtriple=arm64-apple-iphoneos -verify-machineinstrs -aarch64-load-store-renaming=false -o - %s | FileCheck --check-prefix=NO-RENAME %s
|
[AArch64] Teach Load/Store optimizier to rename store operands for pairing.
In some cases, we can rename a store operand, in order to enable pairing
of stores. For store pairs, that cannot be merged because the first
tored register is defined in between the second store, we try to find
suitable rename register.
First, we check if we can rename the given register:
1. The first store register must be killed at the store, which means we
do not have to rename instructions after the first store.
2. We scan backwards from the first store, to find the definition of the
stored register and check all uses in between are renamable. Along
they way, we collect the minimal register classes of the uses for
overlapping (sub/super)registers.
Second, we try to find an available register from the minimal physical
register class of the original register. A suitable register must not be
1. defined before FirstMI
2. between the previous definition of the register to rename
3. a callee saved register.
We use KILL flags to clear defined registers while scanning from the
beginning to the end of the block.
This triggers quite often, here are the top changes for MultiSource,
SPEC2000, SPEC2006 compiled with -O3 for iOS:
Metric: aarch64-ldst-opt.NumPairCreated
Program base patch diff
test-suite...nch/fourinarow/fourinarow.test 2.00 39.00 1850.0%
test-suite...s/ASC_Sequoia/IRSmk/IRSmk.test 46.00 80.00 73.9%
test-suite...chmarks/Olden/power/power.test 70.00 96.00 37.1%
test-suite...cations/hexxagon/hexxagon.test 29.00 39.00 34.5%
test-suite...nchmarks/McCat/05-eks/eks.test 100.00 132.00 32.0%
test-suite.../Trimaran/enc-rc4/enc-rc4.test 46.00 59.00 28.3%
test-suite...T2006/473.astar/473.astar.test 160.00 200.00 25.0%
test-suite.../Trimaran/enc-md5/enc-md5.test 8.00 10.00 25.0%
test-suite...telecomm-gsm/telecomm-gsm.test 113.00 139.00 23.0%
test-suite...ediabench/gsm/toast/toast.test 113.00 139.00 23.0%
test-suite...Source/Benchmarks/sim/sim.test 91.00 111.00 22.0%
test-suite...C/CFP2000/179.art/179.art.test 41.00 49.00 19.5%
test-suite...peg2/mpeg2dec/mpeg2decode.test 245.00 279.00 13.9%
test-suite...marks/Olden/health/health.test 16.00 18.00 12.5%
test-suite...ks/Prolangs-C/cdecl/cdecl.test 90.00 101.00 12.2%
test-suite...fice-ispell/office-ispell.test 91.00 100.00 9.9%
test-suite...oxyApps-C/miniGMG/miniGMG.test 430.00 465.00 8.1%
test-suite...lowfish/security-blowfish.test 39.00 42.00 7.7%
test-suite.../Applications/spiff/spiff.test 42.00 45.00 7.1%
test-suite...arks/mafft/pairlocalalign.test 2473.00 2646.00 7.0%
test-suite.../VersaBench/ecbdes/ecbdes.test 29.00 31.00 6.9%
test-suite...nch/beamformer/beamformer.test 220.00 235.00 6.8%
test-suite...CFP2000/177.mesa/177.mesa.test 2110.00 2252.00 6.7%
test-suite...ve-susan/automotive-susan.test 109.00 116.00 6.4%
test-suite...s-C/unix-smail/unix-smail.test 65.00 69.00 6.2%
test-suite...CI_Purple/SMG2000/smg2000.test 1194.00 1265.00 5.9%
test-suite.../Benchmarks/nbench/nbench.test 472.00 500.00 5.9%
test-suite...oxyApps-C/miniAMR/miniAMR.test 248.00 262.00 5.6%
test-suite...quoia/CrystalMk/CrystalMk.test 18.00 19.00 5.6%
test-suite...rks/tramp3d-v4/tramp3d-v4.test 7331.00 7710.00 5.2%
test-suite.../Benchmarks/Bullet/bullet.test 5651.00 5938.00 5.1%
test-suite...ternal/HMMER/hmmcalibrate.test 750.00 788.00 5.1%
test-suite...T2006/456.hmmer/456.hmmer.test 764.00 802.00 5.0%
test-suite...ications/JM/ldecod/ldecod.test 1028.00 1079.00 5.0%
test-suite...CFP2006/444.namd/444.namd.test 1368.00 1434.00 4.8%
test-suite...marks/7zip/7zip-benchmark.test 4471.00 4685.00 4.8%
test-suite...6/464.h264ref/464.h264ref.test 3122.00 3271.00 4.8%
test-suite...pplications/oggenc/oggenc.test 1497.00 1565.00 4.5%
test-suite...T2000/300.twolf/300.twolf.test 742.00 774.00 4.3%
test-suite.../Prolangs-C/loader/loader.test 24.00 25.00 4.2%
test-suite...0.perlbench/400.perlbench.test 1983.00 2058.00 3.8%
test-suite...ications/JM/lencod/lencod.test 4612.00 4785.00 3.8%
test-suite...yApps-C++/PENNANT/PENNANT.test 995.00 1032.00 3.7%
test-suite...arks/VersaBench/dbms/dbms.test 54.00 56.00 3.7%
Reviewers: efriedma, thegameg, samparker, dmgreen, paquette, evandro
Reviewed By: paquette
Differential Revision: https://reviews.llvm.org/D70450
2019-12-11 17:59:18 +08:00
|
|
|
|
2020-01-28 07:11:45 +08:00
|
|
|
# NO-RENAME-NOT: STP
|
|
|
|
|
# NO-RENAME: test12
|
|
|
|
|
# NO-RENAME: STP
|
|
|
|
|
# NO-RENAME-NOT: STP
|
|
|
|
|
#
|
[AArch64] Teach Load/Store optimizier to rename store operands for pairing.
In some cases, we can rename a store operand, in order to enable pairing
of stores. For store pairs, that cannot be merged because the first
tored register is defined in between the second store, we try to find
suitable rename register.
First, we check if we can rename the given register:
1. The first store register must be killed at the store, which means we
do not have to rename instructions after the first store.
2. We scan backwards from the first store, to find the definition of the
stored register and check all uses in between are renamable. Along
they way, we collect the minimal register classes of the uses for
overlapping (sub/super)registers.
Second, we try to find an available register from the minimal physical
register class of the original register. A suitable register must not be
1. defined before FirstMI
2. between the previous definition of the register to rename
3. a callee saved register.
We use KILL flags to clear defined registers while scanning from the
beginning to the end of the block.
This triggers quite often, here are the top changes for MultiSource,
SPEC2000, SPEC2006 compiled with -O3 for iOS:
Metric: aarch64-ldst-opt.NumPairCreated
Program base patch diff
test-suite...nch/fourinarow/fourinarow.test 2.00 39.00 1850.0%
test-suite...s/ASC_Sequoia/IRSmk/IRSmk.test 46.00 80.00 73.9%
test-suite...chmarks/Olden/power/power.test 70.00 96.00 37.1%
test-suite...cations/hexxagon/hexxagon.test 29.00 39.00 34.5%
test-suite...nchmarks/McCat/05-eks/eks.test 100.00 132.00 32.0%
test-suite.../Trimaran/enc-rc4/enc-rc4.test 46.00 59.00 28.3%
test-suite...T2006/473.astar/473.astar.test 160.00 200.00 25.0%
test-suite.../Trimaran/enc-md5/enc-md5.test 8.00 10.00 25.0%
test-suite...telecomm-gsm/telecomm-gsm.test 113.00 139.00 23.0%
test-suite...ediabench/gsm/toast/toast.test 113.00 139.00 23.0%
test-suite...Source/Benchmarks/sim/sim.test 91.00 111.00 22.0%
test-suite...C/CFP2000/179.art/179.art.test 41.00 49.00 19.5%
test-suite...peg2/mpeg2dec/mpeg2decode.test 245.00 279.00 13.9%
test-suite...marks/Olden/health/health.test 16.00 18.00 12.5%
test-suite...ks/Prolangs-C/cdecl/cdecl.test 90.00 101.00 12.2%
test-suite...fice-ispell/office-ispell.test 91.00 100.00 9.9%
test-suite...oxyApps-C/miniGMG/miniGMG.test 430.00 465.00 8.1%
test-suite...lowfish/security-blowfish.test 39.00 42.00 7.7%
test-suite.../Applications/spiff/spiff.test 42.00 45.00 7.1%
test-suite...arks/mafft/pairlocalalign.test 2473.00 2646.00 7.0%
test-suite.../VersaBench/ecbdes/ecbdes.test 29.00 31.00 6.9%
test-suite...nch/beamformer/beamformer.test 220.00 235.00 6.8%
test-suite...CFP2000/177.mesa/177.mesa.test 2110.00 2252.00 6.7%
test-suite...ve-susan/automotive-susan.test 109.00 116.00 6.4%
test-suite...s-C/unix-smail/unix-smail.test 65.00 69.00 6.2%
test-suite...CI_Purple/SMG2000/smg2000.test 1194.00 1265.00 5.9%
test-suite.../Benchmarks/nbench/nbench.test 472.00 500.00 5.9%
test-suite...oxyApps-C/miniAMR/miniAMR.test 248.00 262.00 5.6%
test-suite...quoia/CrystalMk/CrystalMk.test 18.00 19.00 5.6%
test-suite...rks/tramp3d-v4/tramp3d-v4.test 7331.00 7710.00 5.2%
test-suite.../Benchmarks/Bullet/bullet.test 5651.00 5938.00 5.1%
test-suite...ternal/HMMER/hmmcalibrate.test 750.00 788.00 5.1%
test-suite...T2006/456.hmmer/456.hmmer.test 764.00 802.00 5.0%
test-suite...ications/JM/ldecod/ldecod.test 1028.00 1079.00 5.0%
test-suite...CFP2006/444.namd/444.namd.test 1368.00 1434.00 4.8%
test-suite...marks/7zip/7zip-benchmark.test 4471.00 4685.00 4.8%
test-suite...6/464.h264ref/464.h264ref.test 3122.00 3271.00 4.8%
test-suite...pplications/oggenc/oggenc.test 1497.00 1565.00 4.5%
test-suite...T2000/300.twolf/300.twolf.test 742.00 774.00 4.3%
test-suite.../Prolangs-C/loader/loader.test 24.00 25.00 4.2%
test-suite...0.perlbench/400.perlbench.test 1983.00 2058.00 3.8%
test-suite...ications/JM/lencod/lencod.test 4612.00 4785.00 3.8%
test-suite...yApps-C++/PENNANT/PENNANT.test 995.00 1032.00 3.7%
test-suite...arks/VersaBench/dbms/dbms.test 54.00 56.00 3.7%
Reviewers: efriedma, thegameg, samparker, dmgreen, paquette, evandro
Reviewed By: paquette
Differential Revision: https://reviews.llvm.org/D70450
2019-12-11 17:59:18 +08:00
|
|
|
---
|
|
|
|
|
# CHECK-LABEL: name: test1
|
|
|
|
|
# CHECK: bb.0:
|
|
|
|
|
# CHECK-NEXT: liveins: $x0, $x1
|
|
|
|
|
# CHECK: $x10, renamable $x8 = LDPXi renamable $x0, 0 :: (load 8)
|
|
|
|
|
# CHECK-NEXT: renamable $x9 = LDRXui renamable $x0, 1 :: (load 8)
|
|
|
|
|
# CHECK-NEXT: STRXui renamable $x9, renamable $x0, 100 :: (store 8, align 4)
|
|
|
|
|
# CHECK-NEXT: renamable $x8 = ADDXrr $x8, $x8
|
|
|
|
|
# CHECK-NEXT: STPXi renamable $x8, killed $x10, renamable $x0, 10 :: (store 8, align 4)
|
|
|
|
|
# CHECK-NEXT: RET undef $lr
|
|
|
|
|
|
|
|
|
|
name: test1
|
|
|
|
|
alignment: 4
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
liveins:
|
|
|
|
|
- { reg: '$x0' }
|
|
|
|
|
- { reg: '$x1' }
|
|
|
|
|
- { reg: '$x8' }
|
|
|
|
|
frameInfo:
|
|
|
|
|
maxAlignment: 1
|
|
|
|
|
maxCallFrameSize: 0
|
|
|
|
|
machineFunctionInfo: {}
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $x0, $x1
|
|
|
|
|
renamable $x9, renamable $x8 = LDPXi renamable $x0, 0 :: (load 8)
|
|
|
|
|
STRXui renamable killed $x9, renamable $x0, 11 :: (store 8, align 4)
|
|
|
|
|
renamable $x9 = LDRXui renamable $x0, 1 :: (load 8)
|
|
|
|
|
STRXui renamable $x9, renamable $x0, 100 :: (store 8, align 4)
|
|
|
|
|
renamable $x8 = ADDXrr $x8, $x8
|
|
|
|
|
STRXui renamable $x8, renamable $x0, 10 :: (store 8, align 4)
|
|
|
|
|
RET undef $lr
|
|
|
|
|
|
|
|
|
|
...
|
|
|
|
|
---
|
|
|
|
|
# CHECK-LABEL: name: test2
|
|
|
|
|
# CHECK-LABEL: bb.0:
|
|
|
|
|
# CHECK-NEXT: liveins: $x0, $x9, $x1
|
|
|
|
|
|
|
|
|
|
# CHECK: $x10, renamable $x8 = LDPXi renamable $x9, 0 :: (load 8)
|
|
|
|
|
# CHECK-NEXT: renamable $x9 = LDRXui renamable $x0, 2 :: (load 8)
|
|
|
|
|
# CHECK-NEXT: STRXui renamable $x9, renamable $x0, 100 :: (store 8, align 4)
|
|
|
|
|
# CHECK-NEXT: renamable $x8 = ADDXrr $x8, $x8
|
|
|
|
|
# CHECK-NEXT: STPXi renamable $x8, killed $x10, renamable $x0, 10 :: (store 8, align 4)
|
|
|
|
|
# CHECK-NEXT: RET undef $lr
|
|
|
|
|
|
|
|
|
|
name: test2
|
|
|
|
|
alignment: 4
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
liveins:
|
|
|
|
|
- { reg: '$x0' }
|
|
|
|
|
- { reg: '$x1' }
|
|
|
|
|
- { reg: '$x9' }
|
|
|
|
|
frameInfo:
|
|
|
|
|
maxAlignment: 1
|
|
|
|
|
maxCallFrameSize: 0
|
|
|
|
|
machineFunctionInfo: {}
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $x0, $x9, $x1
|
|
|
|
|
renamable $x9, renamable $x8 = LDPXi renamable $x9, 0 :: (load 8)
|
|
|
|
|
STRXui renamable killed $x9, renamable $x0, 11 :: (store 8, align 4)
|
|
|
|
|
renamable $x9 = LDRXui renamable $x0, 2 :: (load 8)
|
|
|
|
|
STRXui renamable $x9, renamable $x0, 100 :: (store 8, align 4)
|
|
|
|
|
renamable $x8 = ADDXrr $x8, $x8
|
|
|
|
|
STRXui renamable $x8, renamable $x0, 10 :: (store 8, align 4)
|
|
|
|
|
RET undef $lr
|
|
|
|
|
|
|
|
|
|
...
|
|
|
|
|
---
|
|
|
|
|
# MOVK has a tied operand and we currently do not rename across tied defs.
|
|
|
|
|
# CHECK-LABEL: bb.0:
|
|
|
|
|
# CHECK-NEXT: liveins: $x0
|
|
|
|
|
#
|
|
|
|
|
# CHECK: renamable $x8 = MRS 58880
|
|
|
|
|
# CHECK-NEXT: renamable $x8 = MOVZXi 15309, 0
|
|
|
|
|
# CHECK-NEXT: renamable $x8 = MOVKXi renamable $x8, 26239, 16
|
|
|
|
|
# CHECK-NEXT: STRXui renamable $x8, renamable $x0, 0, implicit killed $x8 :: (store 8)
|
|
|
|
|
# CHECK-NEXT: renamable $x8 = MRS 55840
|
|
|
|
|
# CHECK-NEXT: STRXui killed renamable $x8, killed renamable $x0, 1, implicit killed $x8 :: (store 8)
|
|
|
|
|
# CHECK-NEXT: RET undef $lr
|
|
|
|
|
#
|
|
|
|
|
name: test3
|
|
|
|
|
alignment: 2
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
liveins:
|
|
|
|
|
- { reg: '$x0' }
|
|
|
|
|
frameInfo:
|
|
|
|
|
maxCallFrameSize: 0
|
|
|
|
|
machineFunctionInfo: {}
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $x0
|
|
|
|
|
|
|
|
|
|
renamable $x8 = MRS 58880
|
|
|
|
|
renamable $x8 = MOVZXi 15309, 0
|
|
|
|
|
renamable $x8 = MOVKXi renamable $x8, 26239, 16
|
|
|
|
|
STRXui renamable $x8, renamable $x0, 0, implicit killed $x8 :: (store 8)
|
|
|
|
|
renamable $x8 = MRS 55840
|
|
|
|
|
STRXui killed renamable $x8, renamable killed $x0, 1, implicit killed $x8 :: (store 8)
|
|
|
|
|
RET undef $lr
|
|
|
|
|
|
|
|
|
|
...
|
|
|
|
|
---
|
|
|
|
|
# CHECK-LABEL: name: test4
|
|
|
|
|
# CHECK-LABEL: bb.0:
|
|
|
|
|
# CHECK-NEXT: liveins: $x0, $x1
|
|
|
|
|
|
|
|
|
|
# CHECK: $x9 = MRS 58880
|
|
|
|
|
# CHECK-NEXT: renamable $x8 = MRS 55840
|
|
|
|
|
# CHECK-NEXT: STPXi $x9, killed renamable $x8, killed renamable $x0, 0 :: (store 4)
|
|
|
|
|
# CHECK-NEXT: RET undef $lr
|
|
|
|
|
|
|
|
|
|
name: test4
|
|
|
|
|
alignment: 4
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
liveins:
|
|
|
|
|
- { reg: '$x0' }
|
|
|
|
|
- { reg: '$x1' }
|
|
|
|
|
- { reg: '$x8' }
|
|
|
|
|
frameInfo:
|
|
|
|
|
maxAlignment: 1
|
|
|
|
|
maxCallFrameSize: 0
|
|
|
|
|
machineFunctionInfo: {}
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $x0, $x1
|
|
|
|
|
|
|
|
|
|
renamable $x8 = MRS 58880
|
|
|
|
|
STRXui renamable $x8, renamable $x0, 0, implicit killed $x8 :: (store 4)
|
|
|
|
|
renamable $x8 = MRS 55840
|
|
|
|
|
STRXui killed renamable $x8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
|
|
|
|
|
RET undef $lr
|
|
|
|
|
|
|
|
|
|
...
|
|
|
|
|
---
|
|
|
|
|
# CHECK-LABEL: name: test5
|
|
|
|
|
# CHECK-LABEL: bb.0:
|
|
|
|
|
# CHECK-NEXT: liveins: $x0, $x1
|
|
|
|
|
|
|
|
|
|
# CHECK: $x9 = MRS 58880
|
|
|
|
|
# CHECK-NEXT: renamable $x8 = MRS 55840
|
|
|
|
|
# CHECK-NEXT: STPWi $w9, killed renamable $w8, killed renamable $x0, 0 :: (store 4)
|
|
|
|
|
# CHECK-NEXT: RET undef $lr
|
|
|
|
|
|
|
|
|
|
name: test5
|
|
|
|
|
alignment: 4
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
liveins:
|
|
|
|
|
- { reg: '$x0' }
|
|
|
|
|
- { reg: '$x1' }
|
|
|
|
|
- { reg: '$x8' }
|
|
|
|
|
frameInfo:
|
|
|
|
|
maxAlignment: 1
|
|
|
|
|
maxCallFrameSize: 0
|
|
|
|
|
machineFunctionInfo: {}
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $x0, $x1
|
|
|
|
|
|
|
|
|
|
renamable $x8 = MRS 58880
|
|
|
|
|
STRWui renamable $w8, renamable $x0, 0, implicit killed $x8 :: (store 4)
|
|
|
|
|
renamable $x8 = MRS 55840
|
|
|
|
|
STRWui killed renamable $w8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
|
|
|
|
|
RET undef $lr
|
|
|
|
|
|
|
|
|
|
...
|
|
|
|
|
---
|
|
|
|
|
# CHECK-LABEL: name: test6
|
2020-04-03 06:28:32 +08:00
|
|
|
# CHECK-LABEL: bb.0:
|
[AArch64] Teach Load/Store optimizier to rename store operands for pairing.
In some cases, we can rename a store operand, in order to enable pairing
of stores. For store pairs, that cannot be merged because the first
tored register is defined in between the second store, we try to find
suitable rename register.
First, we check if we can rename the given register:
1. The first store register must be killed at the store, which means we
do not have to rename instructions after the first store.
2. We scan backwards from the first store, to find the definition of the
stored register and check all uses in between are renamable. Along
they way, we collect the minimal register classes of the uses for
overlapping (sub/super)registers.
Second, we try to find an available register from the minimal physical
register class of the original register. A suitable register must not be
1. defined before FirstMI
2. between the previous definition of the register to rename
3. a callee saved register.
We use KILL flags to clear defined registers while scanning from the
beginning to the end of the block.
This triggers quite often, here are the top changes for MultiSource,
SPEC2000, SPEC2006 compiled with -O3 for iOS:
Metric: aarch64-ldst-opt.NumPairCreated
Program base patch diff
test-suite...nch/fourinarow/fourinarow.test 2.00 39.00 1850.0%
test-suite...s/ASC_Sequoia/IRSmk/IRSmk.test 46.00 80.00 73.9%
test-suite...chmarks/Olden/power/power.test 70.00 96.00 37.1%
test-suite...cations/hexxagon/hexxagon.test 29.00 39.00 34.5%
test-suite...nchmarks/McCat/05-eks/eks.test 100.00 132.00 32.0%
test-suite.../Trimaran/enc-rc4/enc-rc4.test 46.00 59.00 28.3%
test-suite...T2006/473.astar/473.astar.test 160.00 200.00 25.0%
test-suite.../Trimaran/enc-md5/enc-md5.test 8.00 10.00 25.0%
test-suite...telecomm-gsm/telecomm-gsm.test 113.00 139.00 23.0%
test-suite...ediabench/gsm/toast/toast.test 113.00 139.00 23.0%
test-suite...Source/Benchmarks/sim/sim.test 91.00 111.00 22.0%
test-suite...C/CFP2000/179.art/179.art.test 41.00 49.00 19.5%
test-suite...peg2/mpeg2dec/mpeg2decode.test 245.00 279.00 13.9%
test-suite...marks/Olden/health/health.test 16.00 18.00 12.5%
test-suite...ks/Prolangs-C/cdecl/cdecl.test 90.00 101.00 12.2%
test-suite...fice-ispell/office-ispell.test 91.00 100.00 9.9%
test-suite...oxyApps-C/miniGMG/miniGMG.test 430.00 465.00 8.1%
test-suite...lowfish/security-blowfish.test 39.00 42.00 7.7%
test-suite.../Applications/spiff/spiff.test 42.00 45.00 7.1%
test-suite...arks/mafft/pairlocalalign.test 2473.00 2646.00 7.0%
test-suite.../VersaBench/ecbdes/ecbdes.test 29.00 31.00 6.9%
test-suite...nch/beamformer/beamformer.test 220.00 235.00 6.8%
test-suite...CFP2000/177.mesa/177.mesa.test 2110.00 2252.00 6.7%
test-suite...ve-susan/automotive-susan.test 109.00 116.00 6.4%
test-suite...s-C/unix-smail/unix-smail.test 65.00 69.00 6.2%
test-suite...CI_Purple/SMG2000/smg2000.test 1194.00 1265.00 5.9%
test-suite.../Benchmarks/nbench/nbench.test 472.00 500.00 5.9%
test-suite...oxyApps-C/miniAMR/miniAMR.test 248.00 262.00 5.6%
test-suite...quoia/CrystalMk/CrystalMk.test 18.00 19.00 5.6%
test-suite...rks/tramp3d-v4/tramp3d-v4.test 7331.00 7710.00 5.2%
test-suite.../Benchmarks/Bullet/bullet.test 5651.00 5938.00 5.1%
test-suite...ternal/HMMER/hmmcalibrate.test 750.00 788.00 5.1%
test-suite...T2006/456.hmmer/456.hmmer.test 764.00 802.00 5.0%
test-suite...ications/JM/ldecod/ldecod.test 1028.00 1079.00 5.0%
test-suite...CFP2006/444.namd/444.namd.test 1368.00 1434.00 4.8%
test-suite...marks/7zip/7zip-benchmark.test 4471.00 4685.00 4.8%
test-suite...6/464.h264ref/464.h264ref.test 3122.00 3271.00 4.8%
test-suite...pplications/oggenc/oggenc.test 1497.00 1565.00 4.5%
test-suite...T2000/300.twolf/300.twolf.test 742.00 774.00 4.3%
test-suite.../Prolangs-C/loader/loader.test 24.00 25.00 4.2%
test-suite...0.perlbench/400.perlbench.test 1983.00 2058.00 3.8%
test-suite...ications/JM/lencod/lencod.test 4612.00 4785.00 3.8%
test-suite...yApps-C++/PENNANT/PENNANT.test 995.00 1032.00 3.7%
test-suite...arks/VersaBench/dbms/dbms.test 54.00 56.00 3.7%
Reviewers: efriedma, thegameg, samparker, dmgreen, paquette, evandro
Reviewed By: paquette
Differential Revision: https://reviews.llvm.org/D70450
2019-12-11 17:59:18 +08:00
|
|
|
# CHECK: liveins: $x0, $x1, $q3
|
|
|
|
|
|
|
|
|
|
# CHECK: renamable $q9 = LDRQui $x0, 0 :: (load 16)
|
|
|
|
|
# CHECK-NEXT: renamable $q9 = XTNv8i16 renamable $q9, killed renamable $q3
|
|
|
|
|
# CHECK-NEXT: STRQui renamable $q9, renamable $x0, 11 :: (store 16, align 4)
|
|
|
|
|
# CHECK-NEXT: renamable $q9 = FADDv2f64 renamable $q9, renamable $q9
|
|
|
|
|
# CHECK-NEXT: STRQui renamable $q9, renamable $x0, 10 :: (store 16, align 4)
|
|
|
|
|
# CHECK-NEXT: RET undef $lr
|
|
|
|
|
|
|
|
|
|
# XTN has a tied use-def.
|
|
|
|
|
name: test6
|
|
|
|
|
alignment: 4
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
liveins:
|
|
|
|
|
- { reg: '$x0' }
|
|
|
|
|
- { reg: '$x1' }
|
|
|
|
|
- { reg: '$x8' }
|
|
|
|
|
- { reg: '$q3' }
|
|
|
|
|
frameInfo:
|
|
|
|
|
maxAlignment: 1
|
|
|
|
|
maxCallFrameSize: 0
|
|
|
|
|
machineFunctionInfo: {}
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $x0, $x1, $q3
|
|
|
|
|
renamable $q9 = LDRQui $x0, 0 :: (load 16)
|
|
|
|
|
renamable $q9 = XTNv8i16 renamable $q9, killed renamable $q3
|
|
|
|
|
STRQui renamable $q9, renamable $x0, 11 :: (store 16, align 4)
|
|
|
|
|
renamable $q9 = FADDv2f64 renamable $q9, renamable $q9
|
|
|
|
|
STRQui renamable $q9, renamable $x0, 10 :: (store 16, align 4)
|
|
|
|
|
RET undef $lr
|
|
|
|
|
|
|
|
|
|
...
|
|
|
|
|
---
|
|
|
|
|
# Currently we do not rename across frame-setup instructions.
|
|
|
|
|
# CHECK-LABEL: name: test7
|
|
|
|
|
# CHECK-LABEL: bb.0:
|
|
|
|
|
# CHECK-NEXT: liveins: $x0, $x1
|
|
|
|
|
|
|
|
|
|
# CHECK: $sp = frame-setup SUBXri $sp, 64, 0
|
|
|
|
|
# CHECK-NEXT: renamable $x9 = frame-setup LDRXui renamable $x0, 0 :: (load 8)
|
|
|
|
|
# CHECK-NEXT: STRXui renamable $x9, $x0, 10 :: (store 8, align 4)
|
|
|
|
|
# CHECK-NEXT: renamable $x9 = LDRXui renamable $x0, 1 :: (load 8)
|
|
|
|
|
# CHECK-NEXT: STRXui renamable $x9, $x0, 11 :: (store 8, align 4)
|
|
|
|
|
# CHECK-NEXT: RET undef $lr
|
|
|
|
|
#
|
|
|
|
|
name: test7
|
|
|
|
|
alignment: 4
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
liveins:
|
|
|
|
|
- { reg: '$x0' }
|
|
|
|
|
- { reg: '$x1' }
|
|
|
|
|
- { reg: '$x8' }
|
|
|
|
|
frameInfo:
|
|
|
|
|
stackSize: 64
|
|
|
|
|
maxAlignment: 16
|
|
|
|
|
adjustsStack: true
|
|
|
|
|
hasCalls: true
|
|
|
|
|
maxCallFrameSize: 0
|
|
|
|
|
stack:
|
|
|
|
|
- { id: 0, type: spill-slot, offset: -48, size: 16, alignment: 16 }
|
|
|
|
|
- { id: 1, type: spill-slot, offset: -64, size: 16, alignment: 16 }
|
|
|
|
|
machineFunctionInfo: {}
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $x0, $x1
|
|
|
|
|
$sp = frame-setup SUBXri $sp, 64, 0
|
|
|
|
|
renamable $x9 = frame-setup LDRXui renamable $x0, 0 :: (load 8)
|
|
|
|
|
STRXui renamable $x9, $x0, 10 :: (store 8, align 4)
|
|
|
|
|
renamable $x9 = LDRXui renamable $x0, 1 :: (load 8)
|
|
|
|
|
STRXui renamable $x9, $x0, 11 :: (store 8, align 4)
|
|
|
|
|
RET undef $lr
|
|
|
|
|
...
|
|
|
|
|
---
|
|
|
|
|
# CHECK-LABEL: name: test8
|
|
|
|
|
# CHECK-LABEL: bb.0:
|
|
|
|
|
# CHECK-NEXT: liveins: $x0, $x1
|
|
|
|
|
|
|
|
|
|
# CHECK: renamable $x8 = MRS 58880
|
|
|
|
|
# CHECK-NEXT: $w9 = ORRWrs $wzr, killed renamable $w8, 0, implicit-def $x9
|
|
|
|
|
# CHECK-NEXT: renamable $x8 = MRS 55840
|
|
|
|
|
# CHECK-NEXT: STPWi $w9, killed renamable $w8, killed renamable $x0, 0 :: (store 4)
|
|
|
|
|
# CHECK-NEXT: RET undef $lr
|
|
|
|
|
|
|
|
|
|
name: test8
|
|
|
|
|
alignment: 4
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
liveins:
|
|
|
|
|
- { reg: '$x0' }
|
|
|
|
|
- { reg: '$x1' }
|
|
|
|
|
- { reg: '$x8' }
|
|
|
|
|
frameInfo:
|
|
|
|
|
maxAlignment: 1
|
|
|
|
|
maxCallFrameSize: 0
|
|
|
|
|
machineFunctionInfo: {}
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $x0, $x1
|
|
|
|
|
|
|
|
|
|
renamable $x8 = MRS 58880
|
|
|
|
|
renamable $w8 = ORRWrs $wzr, killed renamable $w8, 0, implicit-def $x8
|
|
|
|
|
STRWui renamable $w8, renamable $x0, 0, implicit killed $x8 :: (store 4)
|
|
|
|
|
renamable $x8 = MRS 55840
|
|
|
|
|
STRWui killed renamable $w8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
|
|
|
|
|
RET undef $lr
|
|
|
|
|
|
|
|
|
|
...
|
|
|
|
|
---
|
|
|
|
|
# The reg class returned for $q9 contains only the first 16 Q registers.
|
|
|
|
|
# TODO: Can we check that all instructions that require renaming also support
|
|
|
|
|
# the second 16 Q registers?
|
|
|
|
|
# CHECK-LABEL: name: test9
|
2020-04-03 06:28:32 +08:00
|
|
|
# CHECK-LABEL: bb.0:
|
[AArch64] Teach Load/Store optimizier to rename store operands for pairing.
In some cases, we can rename a store operand, in order to enable pairing
of stores. For store pairs, that cannot be merged because the first
tored register is defined in between the second store, we try to find
suitable rename register.
First, we check if we can rename the given register:
1. The first store register must be killed at the store, which means we
do not have to rename instructions after the first store.
2. We scan backwards from the first store, to find the definition of the
stored register and check all uses in between are renamable. Along
they way, we collect the minimal register classes of the uses for
overlapping (sub/super)registers.
Second, we try to find an available register from the minimal physical
register class of the original register. A suitable register must not be
1. defined before FirstMI
2. between the previous definition of the register to rename
3. a callee saved register.
We use KILL flags to clear defined registers while scanning from the
beginning to the end of the block.
This triggers quite often, here are the top changes for MultiSource,
SPEC2000, SPEC2006 compiled with -O3 for iOS:
Metric: aarch64-ldst-opt.NumPairCreated
Program base patch diff
test-suite...nch/fourinarow/fourinarow.test 2.00 39.00 1850.0%
test-suite...s/ASC_Sequoia/IRSmk/IRSmk.test 46.00 80.00 73.9%
test-suite...chmarks/Olden/power/power.test 70.00 96.00 37.1%
test-suite...cations/hexxagon/hexxagon.test 29.00 39.00 34.5%
test-suite...nchmarks/McCat/05-eks/eks.test 100.00 132.00 32.0%
test-suite.../Trimaran/enc-rc4/enc-rc4.test 46.00 59.00 28.3%
test-suite...T2006/473.astar/473.astar.test 160.00 200.00 25.0%
test-suite.../Trimaran/enc-md5/enc-md5.test 8.00 10.00 25.0%
test-suite...telecomm-gsm/telecomm-gsm.test 113.00 139.00 23.0%
test-suite...ediabench/gsm/toast/toast.test 113.00 139.00 23.0%
test-suite...Source/Benchmarks/sim/sim.test 91.00 111.00 22.0%
test-suite...C/CFP2000/179.art/179.art.test 41.00 49.00 19.5%
test-suite...peg2/mpeg2dec/mpeg2decode.test 245.00 279.00 13.9%
test-suite...marks/Olden/health/health.test 16.00 18.00 12.5%
test-suite...ks/Prolangs-C/cdecl/cdecl.test 90.00 101.00 12.2%
test-suite...fice-ispell/office-ispell.test 91.00 100.00 9.9%
test-suite...oxyApps-C/miniGMG/miniGMG.test 430.00 465.00 8.1%
test-suite...lowfish/security-blowfish.test 39.00 42.00 7.7%
test-suite.../Applications/spiff/spiff.test 42.00 45.00 7.1%
test-suite...arks/mafft/pairlocalalign.test 2473.00 2646.00 7.0%
test-suite.../VersaBench/ecbdes/ecbdes.test 29.00 31.00 6.9%
test-suite...nch/beamformer/beamformer.test 220.00 235.00 6.8%
test-suite...CFP2000/177.mesa/177.mesa.test 2110.00 2252.00 6.7%
test-suite...ve-susan/automotive-susan.test 109.00 116.00 6.4%
test-suite...s-C/unix-smail/unix-smail.test 65.00 69.00 6.2%
test-suite...CI_Purple/SMG2000/smg2000.test 1194.00 1265.00 5.9%
test-suite.../Benchmarks/nbench/nbench.test 472.00 500.00 5.9%
test-suite...oxyApps-C/miniAMR/miniAMR.test 248.00 262.00 5.6%
test-suite...quoia/CrystalMk/CrystalMk.test 18.00 19.00 5.6%
test-suite...rks/tramp3d-v4/tramp3d-v4.test 7331.00 7710.00 5.2%
test-suite.../Benchmarks/Bullet/bullet.test 5651.00 5938.00 5.1%
test-suite...ternal/HMMER/hmmcalibrate.test 750.00 788.00 5.1%
test-suite...T2006/456.hmmer/456.hmmer.test 764.00 802.00 5.0%
test-suite...ications/JM/ldecod/ldecod.test 1028.00 1079.00 5.0%
test-suite...CFP2006/444.namd/444.namd.test 1368.00 1434.00 4.8%
test-suite...marks/7zip/7zip-benchmark.test 4471.00 4685.00 4.8%
test-suite...6/464.h264ref/464.h264ref.test 3122.00 3271.00 4.8%
test-suite...pplications/oggenc/oggenc.test 1497.00 1565.00 4.5%
test-suite...T2000/300.twolf/300.twolf.test 742.00 774.00 4.3%
test-suite.../Prolangs-C/loader/loader.test 24.00 25.00 4.2%
test-suite...0.perlbench/400.perlbench.test 1983.00 2058.00 3.8%
test-suite...ications/JM/lencod/lencod.test 4612.00 4785.00 3.8%
test-suite...yApps-C++/PENNANT/PENNANT.test 995.00 1032.00 3.7%
test-suite...arks/VersaBench/dbms/dbms.test 54.00 56.00 3.7%
Reviewers: efriedma, thegameg, samparker, dmgreen, paquette, evandro
Reviewed By: paquette
Differential Revision: https://reviews.llvm.org/D70450
2019-12-11 17:59:18 +08:00
|
|
|
# CHECK: liveins: $x0, $x1, $q0, $q1, $q2, $q3, $q4, $q5, $q6, $q7
|
|
|
|
|
|
|
|
|
|
# CHECK: renamable $q9 = LDRQui $x0, 0 :: (load 16)
|
|
|
|
|
# CHECK-NEXT: STRQui killed renamable $q9, renamable $x0, 10 :: (store 16, align 4)
|
|
|
|
|
# CHECK: renamable $q9 = LDRQui $x0, 1 :: (load 16)
|
|
|
|
|
# CHECK-NEXT: STRQui renamable $q9, renamable $x0, 11 :: (store 16, align 4)
|
|
|
|
|
# CHECK-NEXT: RET undef $lr
|
|
|
|
|
|
|
|
|
|
name: test9
|
|
|
|
|
alignment: 4
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
liveins:
|
|
|
|
|
- { reg: '$x0' }
|
|
|
|
|
- { reg: '$x1' }
|
|
|
|
|
- { reg: '$x8' }
|
|
|
|
|
- { reg: '$q3' }
|
|
|
|
|
frameInfo:
|
|
|
|
|
maxAlignment: 1
|
|
|
|
|
maxCallFrameSize: 0
|
|
|
|
|
machineFunctionInfo: {}
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $x0, $x1, $q0, $q1, $q2, $q3, $q4, $q5, $q6, $q7
|
|
|
|
|
renamable $q9 = LDRQui $x0, 0 :: (load 16)
|
|
|
|
|
STRQui renamable killed $q9, renamable $x0, 10 :: (store 16, align 4)
|
|
|
|
|
renamable $q9 = LDRQui $x0, 1 :: (load 16)
|
|
|
|
|
STRQui renamable $q9, renamable $x0, 11 :: (store 16, align 4)
|
|
|
|
|
RET undef $lr
|
|
|
|
|
|
|
|
|
|
...
|
|
|
|
|
---
|
|
|
|
|
# The livein $q7 is killed early, so we can re-use it for renaming.
|
|
|
|
|
# CHECK-LABEL: name: test10
|
2020-04-03 06:28:32 +08:00
|
|
|
# CHECK-LABEL: bb.0:
|
[AArch64] Teach Load/Store optimizier to rename store operands for pairing.
In some cases, we can rename a store operand, in order to enable pairing
of stores. For store pairs, that cannot be merged because the first
tored register is defined in between the second store, we try to find
suitable rename register.
First, we check if we can rename the given register:
1. The first store register must be killed at the store, which means we
do not have to rename instructions after the first store.
2. We scan backwards from the first store, to find the definition of the
stored register and check all uses in between are renamable. Along
they way, we collect the minimal register classes of the uses for
overlapping (sub/super)registers.
Second, we try to find an available register from the minimal physical
register class of the original register. A suitable register must not be
1. defined before FirstMI
2. between the previous definition of the register to rename
3. a callee saved register.
We use KILL flags to clear defined registers while scanning from the
beginning to the end of the block.
This triggers quite often, here are the top changes for MultiSource,
SPEC2000, SPEC2006 compiled with -O3 for iOS:
Metric: aarch64-ldst-opt.NumPairCreated
Program base patch diff
test-suite...nch/fourinarow/fourinarow.test 2.00 39.00 1850.0%
test-suite...s/ASC_Sequoia/IRSmk/IRSmk.test 46.00 80.00 73.9%
test-suite...chmarks/Olden/power/power.test 70.00 96.00 37.1%
test-suite...cations/hexxagon/hexxagon.test 29.00 39.00 34.5%
test-suite...nchmarks/McCat/05-eks/eks.test 100.00 132.00 32.0%
test-suite.../Trimaran/enc-rc4/enc-rc4.test 46.00 59.00 28.3%
test-suite...T2006/473.astar/473.astar.test 160.00 200.00 25.0%
test-suite.../Trimaran/enc-md5/enc-md5.test 8.00 10.00 25.0%
test-suite...telecomm-gsm/telecomm-gsm.test 113.00 139.00 23.0%
test-suite...ediabench/gsm/toast/toast.test 113.00 139.00 23.0%
test-suite...Source/Benchmarks/sim/sim.test 91.00 111.00 22.0%
test-suite...C/CFP2000/179.art/179.art.test 41.00 49.00 19.5%
test-suite...peg2/mpeg2dec/mpeg2decode.test 245.00 279.00 13.9%
test-suite...marks/Olden/health/health.test 16.00 18.00 12.5%
test-suite...ks/Prolangs-C/cdecl/cdecl.test 90.00 101.00 12.2%
test-suite...fice-ispell/office-ispell.test 91.00 100.00 9.9%
test-suite...oxyApps-C/miniGMG/miniGMG.test 430.00 465.00 8.1%
test-suite...lowfish/security-blowfish.test 39.00 42.00 7.7%
test-suite.../Applications/spiff/spiff.test 42.00 45.00 7.1%
test-suite...arks/mafft/pairlocalalign.test 2473.00 2646.00 7.0%
test-suite.../VersaBench/ecbdes/ecbdes.test 29.00 31.00 6.9%
test-suite...nch/beamformer/beamformer.test 220.00 235.00 6.8%
test-suite...CFP2000/177.mesa/177.mesa.test 2110.00 2252.00 6.7%
test-suite...ve-susan/automotive-susan.test 109.00 116.00 6.4%
test-suite...s-C/unix-smail/unix-smail.test 65.00 69.00 6.2%
test-suite...CI_Purple/SMG2000/smg2000.test 1194.00 1265.00 5.9%
test-suite.../Benchmarks/nbench/nbench.test 472.00 500.00 5.9%
test-suite...oxyApps-C/miniAMR/miniAMR.test 248.00 262.00 5.6%
test-suite...quoia/CrystalMk/CrystalMk.test 18.00 19.00 5.6%
test-suite...rks/tramp3d-v4/tramp3d-v4.test 7331.00 7710.00 5.2%
test-suite.../Benchmarks/Bullet/bullet.test 5651.00 5938.00 5.1%
test-suite...ternal/HMMER/hmmcalibrate.test 750.00 788.00 5.1%
test-suite...T2006/456.hmmer/456.hmmer.test 764.00 802.00 5.0%
test-suite...ications/JM/ldecod/ldecod.test 1028.00 1079.00 5.0%
test-suite...CFP2006/444.namd/444.namd.test 1368.00 1434.00 4.8%
test-suite...marks/7zip/7zip-benchmark.test 4471.00 4685.00 4.8%
test-suite...6/464.h264ref/464.h264ref.test 3122.00 3271.00 4.8%
test-suite...pplications/oggenc/oggenc.test 1497.00 1565.00 4.5%
test-suite...T2000/300.twolf/300.twolf.test 742.00 774.00 4.3%
test-suite.../Prolangs-C/loader/loader.test 24.00 25.00 4.2%
test-suite...0.perlbench/400.perlbench.test 1983.00 2058.00 3.8%
test-suite...ications/JM/lencod/lencod.test 4612.00 4785.00 3.8%
test-suite...yApps-C++/PENNANT/PENNANT.test 995.00 1032.00 3.7%
test-suite...arks/VersaBench/dbms/dbms.test 54.00 56.00 3.7%
Reviewers: efriedma, thegameg, samparker, dmgreen, paquette, evandro
Reviewed By: paquette
Differential Revision: https://reviews.llvm.org/D70450
2019-12-11 17:59:18 +08:00
|
|
|
# CHECK: liveins: $x0, $x1, $q0, $q1, $q2, $q3, $q4, $q5, $q6, $q7
|
|
|
|
|
|
|
|
|
|
# CHECK: renamable $q7 = FADDv2f64 renamable $q7, renamable $q7
|
|
|
|
|
# CHECK-NEXT: STRQui killed renamable $q7, renamable $x0, 100 :: (store 16, align 4)
|
|
|
|
|
# CHECK-NEXT: $q7 = LDRQui $x0, 0 :: (load 16)
|
|
|
|
|
# CHECK-NEXT: renamable $q9 = LDRQui $x0, 1 :: (load 16)
|
|
|
|
|
# CHECK-NEXT: STPQi killed renamable $q9, killed $q7, renamable $x0, 10 :: (store 16, align 4)
|
|
|
|
|
# CHECK-NEXT: RET undef $lr
|
|
|
|
|
|
|
|
|
|
name: test10
|
|
|
|
|
alignment: 4
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
liveins:
|
|
|
|
|
- { reg: '$x0' }
|
|
|
|
|
- { reg: '$x1' }
|
|
|
|
|
- { reg: '$x8' }
|
|
|
|
|
- { reg: '$q3' }
|
|
|
|
|
frameInfo:
|
|
|
|
|
maxAlignment: 1
|
|
|
|
|
maxCallFrameSize: 0
|
|
|
|
|
machineFunctionInfo: {}
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $x0, $x1, $q0, $q1, $q2, $q3, $q4, $q5, $q6, $q7
|
|
|
|
|
renamable $q7 = FADDv2f64 renamable $q7, renamable $q7
|
|
|
|
|
STRQui renamable killed $q7, renamable $x0, 100 :: (store 16, align 4)
|
|
|
|
|
renamable $q9 = LDRQui $x0, 0 :: (load 16)
|
|
|
|
|
STRQui renamable killed $q9, renamable $x0, 11 :: (store 16, align 4)
|
|
|
|
|
renamable $q9 = LDRQui $x0, 1 :: (load 16)
|
|
|
|
|
STRQui renamable killed $q9, renamable $x0, 10 :: (store 16, align 4)
|
|
|
|
|
RET undef $lr
|
|
|
|
|
|
|
|
|
|
...
|
|
|
|
|
---
|
|
|
|
|
# Make sure we do not use any registers that are defined between paired candidates
|
|
|
|
|
# ($x14 in this example)
|
|
|
|
|
# CHECK-LABEL: name: test11
|
|
|
|
|
# CHECK: bb.0:
|
|
|
|
|
# CHECK-NEXT: liveins: $x0, $x1, $x11, $x12, $x13
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|
|
|
|
|
|
|
|
|
# CHECK: renamable $w10 = LDRWui renamable $x0, 0 :: (load 8)
|
|
|
|
|
# CHECK-NEXT: $x15, renamable $x8 = LDPXi renamable $x0, 1 :: (load 8)
|
|
|
|
|
# CHECK-NEXT: renamable $x9 = LDRXui renamable $x0, 3 :: (load 8)
|
|
|
|
|
# CHECK-NEXT: renamable $x14 = LDRXui renamable $x0, 5 :: (load 8)
|
|
|
|
|
# CHECK-NEXT: STPXi renamable $x9, killed $x15, renamable $x0, 10 :: (store 8, align 4)
|
|
|
|
|
# CHECK-NEXT: STRXui killed renamable $x14, renamable $x0, 200 :: (store 8, align 4)
|
|
|
|
|
# CHECK-NEXT: renamable $w8 = ADDWrr $w10, $w10
|
|
|
|
|
# CHECK-NEXT: STRWui renamable $w8, renamable $x0, 100 :: (store 8, align 4)
|
|
|
|
|
# CHECK-NEXT: RET undef $lr
|
|
|
|
|
#
|
|
|
|
|
name: test11
|
|
|
|
|
alignment: 4
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
liveins:
|
|
|
|
|
- { reg: '$x0' }
|
|
|
|
|
- { reg: '$x1' }
|
|
|
|
|
- { reg: '$x8' }
|
|
|
|
|
frameInfo:
|
|
|
|
|
maxAlignment: 1
|
|
|
|
|
maxCallFrameSize: 0
|
|
|
|
|
machineFunctionInfo: {}
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $x0, $x1, $x11, $x12, $x13
|
|
|
|
|
renamable $w10 = LDRWui renamable $x0, 0 :: (load 8)
|
|
|
|
|
renamable $x9, renamable $x8 = LDPXi renamable $x0, 1 :: (load 8)
|
|
|
|
|
STRXui renamable killed $x9, renamable $x0, 11 :: (store 8, align 4)
|
|
|
|
|
renamable $x9 = LDRXui renamable $x0, 3 :: (load 8)
|
|
|
|
|
renamable $x14 = LDRXui renamable $x0, 5 :: (load 8)
|
|
|
|
|
STRXui renamable $x9, renamable $x0, 10 :: (store 8, align 4)
|
|
|
|
|
STRXui renamable killed $x14, renamable $x0, 200 :: (store 8, align 4)
|
|
|
|
|
renamable $w8 = ADDWrr $w10, $w10
|
|
|
|
|
STRWui renamable $w8, renamable $x0, 100 :: (store 8, align 4)
|
|
|
|
|
RET undef $lr
|
|
|
|
|
|
|
|
|
|
...
|
|
|
|
|
---
|
|
|
|
|
# Check that we correctly deal with killed registers in stores that get merged forward,
|
|
|
|
|
# which extends the live range of the first store operand.
|
|
|
|
|
# CHECK-LABEL: name: test12
|
|
|
|
|
# CHECK: bb.0:
|
|
|
|
|
# CHECK-NEXT: liveins: $x0, $x1
|
|
|
|
|
#
|
|
|
|
|
# CHECK: renamable $x10 = LDRXui renamable $x0, 0 :: (load 8)
|
|
|
|
|
# CHECK-NEXT: $x11, renamable $x8 = LDPXi renamable $x0, 3 :: (load 8)
|
|
|
|
|
# CHECK-NEXT: renamable $x9 = LDRXui renamable $x0, 2 :: (load 8)
|
|
|
|
|
# CHECK-NEXT: renamable $x8 = ADDXrr $x8, $x8
|
|
|
|
|
# CHECK-NEXT: STPXi renamable $x8, killed $x11, renamable $x0, 10 :: (store 8, align 4)
|
|
|
|
|
# CHECK-NEXT: STPXi killed renamable $x10, renamable $x9, renamable $x0, 20 :: (store 8, align 4)
|
|
|
|
|
# CHECK-NEXT: RET undef $lr
|
|
|
|
|
|
|
|
|
|
name: test12
|
|
|
|
|
alignment: 4
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
liveins:
|
|
|
|
|
- { reg: '$x0' }
|
|
|
|
|
- { reg: '$x1' }
|
|
|
|
|
- { reg: '$x8' }
|
|
|
|
|
frameInfo:
|
|
|
|
|
maxAlignment: 1
|
|
|
|
|
maxCallFrameSize: 0
|
|
|
|
|
machineFunctionInfo: {}
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $x0, $x1
|
|
|
|
|
renamable $x10 = LDRXui renamable $x0, 0 :: (load 8)
|
|
|
|
|
STRXui renamable killed $x10, renamable $x0, 20 :: (store 8, align 4)
|
|
|
|
|
renamable $x9, renamable $x8 = LDPXi renamable $x0, 3 :: (load 8)
|
|
|
|
|
STRXui renamable killed $x9, renamable $x0, 11 :: (store 8, align 4)
|
|
|
|
|
renamable $x9 = LDRXui renamable $x0, 2 :: (load 8)
|
|
|
|
|
renamable $x8 = ADDXrr $x8, $x8
|
|
|
|
|
STRXui renamable $x8, renamable $x0, 10 :: (store 8, align 4)
|
|
|
|
|
STRXui renamable $x9, renamable $x0, 21 :: (store 8, align 4)
|
|
|
|
|
RET undef $lr
|
|
|
|
|
|
|
|
|
|
...
|
|
|
|
|
---
|
|
|
|
|
# Make sure we do not use any registers that are defined between def to rename and the first
|
|
|
|
|
# paired store. ($x14 in this example)
|
|
|
|
|
# CHECK-LABEL: name: test13
|
|
|
|
|
# CHECK: bb.0:
|
|
|
|
|
# CHECK-NEXT: liveins: $x0, $x1, $x10, $x11, $x12, $x13
|
|
|
|
|
# CHECK: $x15, renamable $x8 = LDPXi renamable $x0, 0 :: (load 8)
|
|
|
|
|
# CHECK-NEXT: renamable $x14 = LDRXui renamable $x0, 4 :: (load 8)
|
|
|
|
|
# CHECK-NEXT: STRXui killed renamable $x14, renamable $x0, 100 :: (store 8, align 4)
|
|
|
|
|
# CHECK-NEXT: renamable $x9 = LDRXui renamable $x0, 2 :: (load 8)
|
|
|
|
|
# CHECK-NEXT: STPXi renamable $x9, killed $x15, renamable $x0, 10 :: (store 8, align 4)
|
|
|
|
|
# CHECK-NEXT: RET undef $lr
|
|
|
|
|
#
|
|
|
|
|
name: test13
|
|
|
|
|
alignment: 4
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
liveins:
|
|
|
|
|
- { reg: '$x0' }
|
|
|
|
|
- { reg: '$x1' }
|
|
|
|
|
- { reg: '$x8' }
|
|
|
|
|
frameInfo:
|
|
|
|
|
maxAlignment: 1
|
|
|
|
|
maxCallFrameSize: 0
|
|
|
|
|
machineFunctionInfo: {}
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $x0, $x1, $x10, $x11, $x12, $x13
|
|
|
|
|
renamable $x9, renamable $x8 = LDPXi renamable $x0, 0 :: (load 8)
|
|
|
|
|
renamable $x14 = LDRXui renamable $x0, 4 :: (load 8)
|
|
|
|
|
STRXui renamable killed $x14, renamable $x0, 100 :: (store 8, align 4)
|
|
|
|
|
STRXui renamable killed $x9, renamable $x0, 11 :: (store 8, align 4)
|
|
|
|
|
renamable $x9 = LDRXui renamable $x0, 2 :: (load 8)
|
|
|
|
|
STRXui renamable $x9, renamable $x0, 10 :: (store 8)
|
|
|
|
|
RET undef $lr
|
|
|
|
|
|
|
|
|
|
...
|
2020-01-23 01:16:40 +08:00
|
|
|
# Make sure we do not rename if pseudo-defs. Noop pseudo instructions like KILL
|
|
|
|
|
# may lead to a missing definition of the rename register.
|
|
|
|
|
#
|
|
|
|
|
# CHECK-LABEL: name: test14_pseudo
|
|
|
|
|
# CHECK: bb.0:
|
|
|
|
|
# CHECK-NEXT: liveins: $w8, $fp, $w25
|
|
|
|
|
# CHECK: renamable $w8 = KILL killed renamable $w8, implicit-def $x8
|
|
|
|
|
# CHECK-NEXT: STURXi killed renamable $x8, $fp, -40 :: (store 8)
|
|
|
|
|
# CHECK-NEXT: $w8 = ORRWrs $wzr, killed $w25, 0, implicit-def $x8
|
|
|
|
|
# CHECK-NEXT: STURXi killed renamable $x8, $fp, -32 :: (store 8)
|
|
|
|
|
# CHECK-NEXT: RET undef $lr
|
|
|
|
|
#
|
|
|
|
|
name: test14_pseudo
|
|
|
|
|
alignment: 4
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
liveins:
|
|
|
|
|
- { reg: '$x0' }
|
|
|
|
|
- { reg: '$x1' }
|
|
|
|
|
- { reg: '$x8' }
|
|
|
|
|
frameInfo:
|
|
|
|
|
maxAlignment: 1
|
|
|
|
|
maxCallFrameSize: 0
|
|
|
|
|
machineFunctionInfo: {}
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $w8, $fp, $w25
|
|
|
|
|
|
|
|
|
|
renamable $w8 = KILL killed renamable $w8, implicit-def $x8
|
|
|
|
|
STURXi killed renamable $x8, $fp, -40 :: (store 8)
|
|
|
|
|
$w8 = ORRWrs $wzr, killed $w25, 0, implicit-def $x8
|
|
|
|
|
STURXi killed renamable $x8, $fp, -32 :: (store 8)
|
|
|
|
|
RET undef $lr
|
|
|
|
|
...
|