2016-11-02 07:40:28 +08:00
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//===-- RISCVInstrFormats.td - RISCV Instruction Formats ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//
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// These instruction format definitions are structured to match the
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// description in the RISC-V User-Level ISA specification as closely as
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// possible. For instance, the specification describes instructions with the
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// MSB (31st bit) on the left and the LSB (0th bit) on the right. This is
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// reflected in the order of parameters to each instruction class.
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//
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// One area of divergence is in the description of immediates. The
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// specification describes immediate encoding in terms of bit-slicing
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// operations on the logical value represented. The immediate argument to
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// these instruction formats instead represents the bit sequence that will be
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// inserted into the instruction. e.g. although JAL's immediate is logically
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// a 21-bit value (where the LSB is always zero), we describe it as an imm20
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// to match how it is encoded.
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//
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//===----------------------------------------------------------------------===//
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2017-09-28 16:26:24 +08:00
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// Format specifies the encoding used by the instruction. This is used by
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// RISCVMCCodeEmitter to determine which form of fixup to use. These
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// definitions must be kept in-sync with RISCVBaseInfo.h.
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class InstFormat<bits<4> val> {
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bits<4> Value = val;
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}
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def InstFormatPseudo : InstFormat<0>;
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def InstFormatR : InstFormat<1>;
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def InstFormatI : InstFormat<2>;
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def InstFormatS : InstFormat<3>;
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def InstFormatSB : InstFormat<4>;
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def InstFormatU : InstFormat<5>;
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def InstFormatOther : InstFormat<6>;
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class RISCVInst<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstFormat format>
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: Instruction {
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field bits<32> Inst;
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2017-09-17 22:36:28 +08:00
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// SoftFail is a field the disassembler can use to provide a way for
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// instructions to not match without killing the whole decode process. It is
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// mainly used for ARM, but Tablegen expects this field to exist or it fails
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// to build the decode table.
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field bits<32> SoftFail = 0;
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let Size = 4;
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bits<7> Opcode = 0;
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let Inst{6-0} = Opcode;
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let Namespace = "RISCV";
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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let TSFlags{3-0} = format.Value;
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}
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// Pseudo instructions
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class Pseudo<dag outs, dag ins, list<dag> pattern>
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: RISCVInst<outs, ins, "", pattern, InstFormatPseudo> {
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let isPseudo = 1;
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let isCodeGenOnly = 1;
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}
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class FR<bits<7> funct7, bits<3> funct3, bits<7> opcode, dag outs, dag ins,
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string asmstr, list<dag> pattern> : RISCVInst<outs, ins, asmstr, pattern, InstFormatR>
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{
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bits<5> rs2;
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bits<5> rs1;
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bits<5> rd;
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let Inst{31-25} = funct7;
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let Inst{24-20} = rs2;
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let Inst{19-15} = rs1;
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let Inst{14-12} = funct3;
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let Inst{11-7} = rd;
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let Opcode = opcode;
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}
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class FI<bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
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: RISCVInst<outs, ins, asmstr, pattern, InstFormatI>
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{
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bits<12> imm12;
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bits<5> rs1;
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bits<5> rd;
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let Inst{31-20} = imm12;
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let Inst{19-15} = rs1;
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let Inst{14-12} = funct3;
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let Inst{11-7} = rd;
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let Opcode = opcode;
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}
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class FI32Shift<bit arithshift, bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
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: RISCVInst<outs, ins, asmstr, pattern, InstFormatI>
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{
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bits<5> shamt;
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bits<5> rs1;
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bits<5> rd;
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let Inst{31} = 0;
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let Inst{30} = arithshift;
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let Inst{29-25} = 0;
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let Inst{24-20} = shamt;
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let Inst{19-15} = rs1;
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let Inst{14-12} = funct3;
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let Inst{11-7} = rd;
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let Opcode = opcode;
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}
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class FS<bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
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: RISCVInst<outs, ins, asmstr, pattern, InstFormatS>
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{
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bits<12> imm12;
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bits<5> rs2;
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bits<5> rs1;
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let Inst{31-25} = imm12{11-5};
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let Inst{24-20} = rs2;
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let Inst{19-15} = rs1;
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let Inst{14-12} = funct3;
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let Inst{11-7} = imm12{4-0};
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let Opcode = opcode;
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}
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class FSB<bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
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: RISCVInst<outs, ins, asmstr, pattern, InstFormatSB>
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{
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bits<12> imm12;
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bits<5> rs2;
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bits<5> rs1;
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let Inst{31} = imm12{11};
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let Inst{30-25} = imm12{9-4};
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let Inst{24-20} = rs2;
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let Inst{19-15} = rs1;
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let Inst{14-12} = funct3;
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let Inst{11-8} = imm12{3-0};
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let Inst{7} = imm12{10};
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let Opcode = opcode;
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}
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class FU<bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
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: RISCVInst<outs, ins, asmstr, pattern, InstFormatU>
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{
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bits<20> imm20;
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bits<5> rd;
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let Inst{31-12} = imm20;
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let Inst{11-7} = rd;
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let Opcode = opcode;
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}
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class FUJ<bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
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: RISCVInst<outs, ins, asmstr, pattern, InstFormatU>
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{
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bits<20> imm20;
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bits<5> rd;
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let Inst{31} = imm20{19};
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let Inst{30-21} = imm20{9-0};
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let Inst{20} = imm20{10};
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let Inst{19-12} = imm20{18-11};
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let Inst{11-7} = rd;
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let Opcode = opcode;
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}
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