llvm-project/llvm/docs/CommandGuide/tblgen.rst

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tblgen - Target Description To C++ Code Generator
=================================================
SYNOPSIS
--------
:program:`tblgen` [*options*] [*filename*]
DESCRIPTION
-----------
:program:`tblgen` translates from target description (``.td``) files into C++
code that can be included in the definition of an LLVM target library. Most
users of LLVM will not need to use this program. It is only for assisting with
writing an LLVM target backend.
The input and output of :program:`tblgen` is beyond the scope of this short
introduction; please see the :doc:`introduction to TableGen
<../TableGen/index>`.
The *filename* argument specifies the name of a Target Description (``.td``)
file to read as input.
OPTIONS
-------
.. program:: tblgen
.. option:: -help
Print a summary of command line options.
.. option:: -o filename
Specify the output file name. If ``filename`` is ``-``, then
:program:`tblgen` sends its output to standard output.
.. option:: -I directory
Specify where to find other target description files for inclusion. The
``directory`` value should be a full or partial path to a directory that
contains target description files.
.. option:: -asmparsernum N
Make -gen-asm-parser emit assembly writer number ``N``.
.. option:: -asmwriternum N
Make -gen-asm-writer emit assembly writer number ``N``.
.. option:: -class className
Print the enumeration list for this class.
.. option:: -print-records
Print all records to standard output (default).
[TableGen] Add a general-purpose JSON backend. The aim of this backend is to output everything TableGen knows about the record set, similarly to the default -print-records backend. But where -print-records produces output in TableGen's input syntax (convenient for humans to read), this backend produces it as structured JSON data, which is convenient for loading into standard scripting languages such as Python, in order to extract information from the data set in an automated way. The output data contains a JSON representation of the variable definitions in output 'def' records, and a few pieces of metadata such as which of those definitions are tagged with the 'field' prefix and which defs are derived from which classes. It doesn't dump out absolutely every piece of knowledge it _could_ produce, such as type information and complicated arithmetic operator nodes in abstract superclasses; the main aim is to allow consumers of this JSON dump to essentially act as new backends, and backends don't generally need to depend on that kind of data. The new backend is implemented as an EmitJSON() function similar to all of llvm-tblgen's other EmitFoo functions, except that it lives in lib/TableGen instead of utils/TableGen on the basis that I'm expecting to add it to clang-tblgen too in a future patch. To test it, I've written a Python script that loads the JSON output and tests properties of it based on comments in the .td source - more or less like FileCheck, except that the CHECK: lines have Python expressions after them instead of textual pattern matches. Reviewers: nhaehnle Reviewed By: nhaehnle Subscribers: arichardson, labath, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D46054 llvm-svn: 336771
2018-07-11 16:40:19 +08:00
.. option:: -dump-json
Print a JSON representation of all records, suitable for further
automated processing.
.. option:: -print-enums
Print enumeration values for a class.
.. option:: -print-sets
Print expanded sets for testing DAG exprs.
.. option:: -gen-emitter
Generate machine code emitter.
.. option:: -gen-register-info
Generate registers and register classes info.
.. option:: -gen-instr-info
Generate instruction descriptions.
.. option:: -gen-asm-writer
Generate the assembly writer.
.. option:: -gen-disassembler
Generate disassembler.
.. option:: -gen-pseudo-lowering
Generate pseudo instruction lowering.
.. option:: -gen-dag-isel
Generate a DAG (Directed Acycle Graph) instruction selector.
.. option:: -gen-asm-matcher
Generate assembly instruction matcher.
.. option:: -gen-dfa-packetizer
Generate DFA Packetizer for VLIW targets.
.. option:: -gen-fast-isel
Generate a "fast" instruction selector.
.. option:: -gen-subtarget
Generate subtarget enumerations.
.. option:: -gen-intrinsic-enums
Generate intrinsic enums.
.. option:: -gen-intrinsic-impl
Generate intrinsic implementation.
.. option:: -gen-tgt-intrinsic
Generate target intrinsic information.
.. option:: -gen-enhanced-disassembly-info
Generate enhanced disassembly info.
.. option:: -version
Show the version number of this program.
EXIT STATUS
-----------
If :program:`tblgen` succeeds, it will exit with 0. Otherwise, if an error
occurs, it will exit with a non-zero value.