2018-06-08 06:28:32 +08:00
|
|
|
# RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass si-memory-legalizer %s -o - | FileCheck -check-prefix=GCN %s
|
2017-09-08 00:14:21 +08:00
|
|
|
|
|
|
|
---
|
|
|
|
|
2018-06-08 06:28:32 +08:00
|
|
|
# GCN-LABEL: name: multiple_mem_operands
|
2017-09-08 00:14:21 +08:00
|
|
|
|
2018-06-08 06:28:32 +08:00
|
|
|
# GCN-LABEL: bb.3:
|
|
|
|
# GCN: S_WAITCNT 3952
|
|
|
|
# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
|
|
|
|
# GCN-NEXT: S_WAITCNT 3952
|
|
|
|
# GCN-NEXT: BUFFER_WBINVL1_VOL
|
2017-09-08 00:14:21 +08:00
|
|
|
|
|
|
|
name: multiple_mem_operands
|
|
|
|
body: |
|
|
|
|
bb.0.entry:
|
2018-06-08 06:28:32 +08:00
|
|
|
successors: %bb.1(0x30000000), %bb.2(0x50000000)
|
2018-02-01 06:04:26 +08:00
|
|
|
liveins: $sgpr0_sgpr1, $sgpr3
|
|
|
|
|
2019-05-01 06:08:23 +08:00
|
|
|
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 44, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`)
|
2018-02-01 06:04:26 +08:00
|
|
|
$sgpr8 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
|
2019-05-01 06:08:23 +08:00
|
|
|
$sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM $sgpr0_sgpr1, 36, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
|
2018-02-01 06:04:26 +08:00
|
|
|
$sgpr9 = S_MOV_B32 &SCRATCH_RSRC_DWORD1, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
|
|
|
|
$sgpr10 = S_MOV_B32 4294967295, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
|
|
|
|
$sgpr11 = S_MOV_B32 15204352, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
|
|
|
|
$vgpr0 = V_MOV_B32_e32 1, implicit $exec
|
[AMDGPU] Extend buffer intrinsics with swizzling
Summary:
Extend cachepolicy operand in the new VMEM buffer intrinsics
to supply information whether the buffer data is swizzled.
Also, propagate this information to MIR.
Intrinsics updated:
int_amdgcn_raw_buffer_load
int_amdgcn_raw_buffer_load_format
int_amdgcn_raw_buffer_store
int_amdgcn_raw_buffer_store_format
int_amdgcn_raw_tbuffer_load
int_amdgcn_raw_tbuffer_store
int_amdgcn_struct_buffer_load
int_amdgcn_struct_buffer_load_format
int_amdgcn_struct_buffer_store
int_amdgcn_struct_buffer_store_format
int_amdgcn_struct_tbuffer_load
int_amdgcn_struct_tbuffer_store
Furthermore, disable merging of VMEM buffer instructions
in SI Load/Store optimizer, if the "swizzled" bit on the instruction
is on.
The default value of the bit is 0, meaning that data in buffer
is linear and buffer instructions can be merged.
There is no difference in the generated code with this commit.
However, in the future it will be expected that front-ends
use buffer intrinsics with correct "swizzled" bit set.
Reviewers: arsenm, nhaehnle, tpr
Reviewed By: nhaehnle
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68200
llvm-svn: 373491
2019-10-03 01:22:36 +08:00
|
|
|
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 4, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into `i32 addrspace(5)* undef`)
|
2017-09-08 00:14:21 +08:00
|
|
|
S_WAITCNT 127
|
2018-02-01 06:04:26 +08:00
|
|
|
S_CMP_LG_U32 killed $sgpr2, 0, implicit-def $scc
|
2017-09-08 00:14:21 +08:00
|
|
|
S_WAITCNT 3855
|
2018-02-01 06:04:26 +08:00
|
|
|
$vgpr0 = V_MOV_B32_e32 2, implicit $exec
|
|
|
|
$vgpr1 = V_MOV_B32_e32 32772, implicit $exec
|
[AMDGPU] Extend buffer intrinsics with swizzling
Summary:
Extend cachepolicy operand in the new VMEM buffer intrinsics
to supply information whether the buffer data is swizzled.
Also, propagate this information to MIR.
Intrinsics updated:
int_amdgcn_raw_buffer_load
int_amdgcn_raw_buffer_load_format
int_amdgcn_raw_buffer_store
int_amdgcn_raw_buffer_store_format
int_amdgcn_raw_tbuffer_load
int_amdgcn_raw_tbuffer_store
int_amdgcn_struct_buffer_load
int_amdgcn_struct_buffer_load_format
int_amdgcn_struct_buffer_store
int_amdgcn_struct_buffer_store_format
int_amdgcn_struct_tbuffer_load
int_amdgcn_struct_tbuffer_store
Furthermore, disable merging of VMEM buffer instructions
in SI Load/Store optimizer, if the "swizzled" bit on the instruction
is on.
The default value of the bit is 0, meaning that data in buffer
is linear and buffer instructions can be merged.
There is no difference in the generated code with this commit.
However, in the future it will be expected that front-ends
use buffer intrinsics with correct "swizzled" bit set.
Reviewers: arsenm, nhaehnle, tpr
Reviewed By: nhaehnle
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68200
llvm-svn: 373491
2019-10-03 01:22:36 +08:00
|
|
|
BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into `i32 addrspace(5)* undef`)
|
2018-06-08 06:28:32 +08:00
|
|
|
S_CBRANCH_SCC0 %bb.1, implicit killed $scc
|
2017-09-08 00:14:21 +08:00
|
|
|
|
2018-06-08 06:28:32 +08:00
|
|
|
bb.2:
|
|
|
|
successors: %bb.3(0x80000000)
|
2018-02-01 06:04:26 +08:00
|
|
|
liveins: $sgpr0_sgpr1, $sgpr4_sgpr5, $sgpr3, $sgpr8_sgpr9_sgpr10_sgpr11
|
2017-09-08 00:14:21 +08:00
|
|
|
|
2019-05-01 06:08:23 +08:00
|
|
|
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 52, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`)
|
2017-09-08 00:14:21 +08:00
|
|
|
S_WAITCNT 3855
|
2018-02-01 06:04:26 +08:00
|
|
|
$vgpr0 = V_MOV_B32_e32 32772, implicit $exec
|
2018-06-08 06:28:32 +08:00
|
|
|
S_BRANCH %bb.3
|
2017-09-08 00:14:21 +08:00
|
|
|
|
2018-06-08 06:28:32 +08:00
|
|
|
bb.1:
|
|
|
|
successors: %bb.3(0x80000000)
|
2018-02-01 06:04:26 +08:00
|
|
|
liveins: $sgpr0_sgpr1, $sgpr4_sgpr5, $sgpr3, $sgpr8_sgpr9_sgpr10_sgpr11
|
2017-09-08 00:14:21 +08:00
|
|
|
|
2019-05-01 06:08:23 +08:00
|
|
|
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 48, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`)
|
2017-09-08 00:14:21 +08:00
|
|
|
S_WAITCNT 3855
|
2018-02-01 06:04:26 +08:00
|
|
|
$vgpr0 = V_MOV_B32_e32 4, implicit $exec
|
2017-09-08 00:14:21 +08:00
|
|
|
|
2018-06-08 06:28:32 +08:00
|
|
|
bb.3:
|
2018-02-01 06:04:26 +08:00
|
|
|
liveins: $sgpr3, $sgpr4_sgpr5, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $sgpr0
|
2017-09-08 00:14:21 +08:00
|
|
|
|
|
|
|
S_WAITCNT 127
|
2018-02-01 06:04:26 +08:00
|
|
|
$sgpr0 = S_LSHL_B32 killed $sgpr0, 2, implicit-def dead $scc
|
2020-07-14 21:18:36 +08:00
|
|
|
$vgpr0 = V_ADD_CO_U32_e32 killed $sgpr0, killed $vgpr0, implicit-def dead $vcc, implicit $exec
|
[AMDGPU] Extend buffer intrinsics with swizzling
Summary:
Extend cachepolicy operand in the new VMEM buffer intrinsics
to supply information whether the buffer data is swizzled.
Also, propagate this information to MIR.
Intrinsics updated:
int_amdgcn_raw_buffer_load
int_amdgcn_raw_buffer_load_format
int_amdgcn_raw_buffer_store
int_amdgcn_raw_buffer_store_format
int_amdgcn_raw_tbuffer_load
int_amdgcn_raw_tbuffer_store
int_amdgcn_struct_buffer_load
int_amdgcn_struct_buffer_load_format
int_amdgcn_struct_buffer_store
int_amdgcn_struct_buffer_store_format
int_amdgcn_struct_tbuffer_load
int_amdgcn_struct_tbuffer_store
Furthermore, disable merging of VMEM buffer instructions
in SI Load/Store optimizer, if the "swizzled" bit on the instruction
is on.
The default value of the bit is 0, meaning that data in buffer
is linear and buffer instructions can be merged.
There is no difference in the generated code with this commit.
However, in the future it will be expected that front-ends
use buffer intrinsics with correct "swizzled" bit set.
Reviewers: arsenm, nhaehnle, tpr
Reviewed By: nhaehnle
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68200
llvm-svn: 373491
2019-10-03 01:22:36 +08:00
|
|
|
$vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec :: (load syncscope("agent-one-as") unordered 4 from `i32 addrspace(1)* undef`), (load syncscope("workgroup-one-as") seq_cst 4 from `[8192 x i32] addrspace(5)* undef`)
|
2018-02-01 06:04:26 +08:00
|
|
|
$vgpr1 = V_MOV_B32_e32 $sgpr4, implicit $exec, implicit-def $vgpr1_vgpr2, implicit $sgpr4_sgpr5
|
|
|
|
$vgpr2 = V_MOV_B32_e32 killed $sgpr5, implicit $exec, implicit $sgpr4_sgpr5, implicit $exec
|
2017-09-08 00:14:21 +08:00
|
|
|
S_WAITCNT 3952
|
2019-05-01 06:08:23 +08:00
|
|
|
FLAT_STORE_DWORD killed $vgpr1_vgpr2, killed $vgpr0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32 addrspace(1)* undef`)
|
[AMDGPU] Add support for immediate operand for S_ENDPGM
Summary:
Add support for immediate operand in S_ENDPGM
Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6
Reviewers: alexshap
Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59213
llvm-svn: 355902
2019-03-12 17:52:58 +08:00
|
|
|
S_ENDPGM 0
|
2017-09-08 00:14:21 +08:00
|
|
|
|
|
|
|
...
|