forked from OSchip/llvm-project
124 lines
6.0 KiB
LLVM
124 lines
6.0 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -amdgpu-lower-intrinsics -amdgpu-mem-intrinsic-expand-size=8 %s | FileCheck -check-prefix=OPT8 %s
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; RUN: opt -S -amdgpu-lower-intrinsics -amdgpu-mem-intrinsic-expand-size=4 %s | FileCheck -check-prefix=OPT4 %s
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; RUN: opt -S -amdgpu-lower-intrinsics -amdgpu-mem-intrinsic-expand-size=0 %s | FileCheck -check-prefix=OPT0 %s
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; RUN: opt -S -amdgpu-lower-intrinsics -amdgpu-mem-intrinsic-expand-size=-1 %s | FileCheck -check-prefix=OPT_NEG %s
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; Test the -amdgpu-mem-intrinsic-expand-size flag works.
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; Make sure we can always eliminate the intrinsic, even at 0.
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define amdgpu_kernel void @memset_size_0(i8 addrspace(1)* %dst, i8 %val) {
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; OPT8-LABEL: @memset_size_0(
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; OPT8-NEXT: call void @llvm.memset.p1i8.i64(i8 addrspace(1)* [[DST:%.*]], i8 [[VAL:%.*]], i64 0, i1 false)
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; OPT8-NEXT: ret void
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;
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; OPT4-LABEL: @memset_size_0(
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; OPT4-NEXT: call void @llvm.memset.p1i8.i64(i8 addrspace(1)* [[DST:%.*]], i8 [[VAL:%.*]], i64 0, i1 false)
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; OPT4-NEXT: ret void
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;
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; OPT0-LABEL: @memset_size_0(
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; OPT0-NEXT: call void @llvm.memset.p1i8.i64(i8 addrspace(1)* [[DST:%.*]], i8 [[VAL:%.*]], i64 0, i1 false)
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; OPT0-NEXT: ret void
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;
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; OPT_NEG-LABEL: @memset_size_0(
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; OPT_NEG-NEXT: br i1 true, label [[SPLIT:%.*]], label [[LOADSTORELOOP:%.*]]
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; OPT_NEG: loadstoreloop:
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; OPT_NEG-NEXT: [[TMP1:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], [[LOADSTORELOOP]] ]
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; OPT_NEG-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[DST:%.*]], i64 [[TMP1]]
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; OPT_NEG-NEXT: store i8 [[VAL:%.*]], i8 addrspace(1)* [[TMP2]]
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; OPT_NEG-NEXT: [[TMP3]] = add i64 [[TMP1]], 1
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; OPT_NEG-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 0
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; OPT_NEG-NEXT: br i1 [[TMP4]], label [[LOADSTORELOOP]], label [[SPLIT]]
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; OPT_NEG: split:
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; OPT_NEG-NEXT: ret void
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;
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call void @llvm.memset.p1i8.i64(i8 addrspace(1)* %dst, i8 %val, i64 0, i1 false)
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ret void
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}
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define amdgpu_kernel void @memset_size_4(i8 addrspace(1)* %dst, i8 %val) {
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; OPT8-LABEL: @memset_size_4(
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; OPT8-NEXT: call void @llvm.memset.p1i8.i64(i8 addrspace(1)* [[DST:%.*]], i8 [[VAL:%.*]], i64 4, i1 false)
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; OPT8-NEXT: ret void
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;
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; OPT4-LABEL: @memset_size_4(
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; OPT4-NEXT: call void @llvm.memset.p1i8.i64(i8 addrspace(1)* [[DST:%.*]], i8 [[VAL:%.*]], i64 4, i1 false)
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; OPT4-NEXT: ret void
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;
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; OPT0-LABEL: @memset_size_4(
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; OPT0-NEXT: br i1 false, label [[SPLIT:%.*]], label [[LOADSTORELOOP:%.*]]
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; OPT0: loadstoreloop:
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; OPT0-NEXT: [[TMP1:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], [[LOADSTORELOOP]] ]
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; OPT0-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[DST:%.*]], i64 [[TMP1]]
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; OPT0-NEXT: store i8 [[VAL:%.*]], i8 addrspace(1)* [[TMP2]]
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; OPT0-NEXT: [[TMP3]] = add i64 [[TMP1]], 1
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; OPT0-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 4
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; OPT0-NEXT: br i1 [[TMP4]], label [[LOADSTORELOOP]], label [[SPLIT]]
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; OPT0: split:
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; OPT0-NEXT: ret void
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;
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; OPT_NEG-LABEL: @memset_size_4(
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; OPT_NEG-NEXT: br i1 false, label [[SPLIT:%.*]], label [[LOADSTORELOOP:%.*]]
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; OPT_NEG: loadstoreloop:
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; OPT_NEG-NEXT: [[TMP1:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], [[LOADSTORELOOP]] ]
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; OPT_NEG-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[DST:%.*]], i64 [[TMP1]]
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; OPT_NEG-NEXT: store i8 [[VAL:%.*]], i8 addrspace(1)* [[TMP2]]
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; OPT_NEG-NEXT: [[TMP3]] = add i64 [[TMP1]], 1
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; OPT_NEG-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 4
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; OPT_NEG-NEXT: br i1 [[TMP4]], label [[LOADSTORELOOP]], label [[SPLIT]]
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; OPT_NEG: split:
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; OPT_NEG-NEXT: ret void
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;
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call void @llvm.memset.p1i8.i64(i8 addrspace(1)* %dst, i8 %val, i64 4, i1 false)
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ret void
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}
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define amdgpu_kernel void @memset_size_8(i8 addrspace(1)* %dst, i8 %val) {
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; OPT8-LABEL: @memset_size_8(
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; OPT8-NEXT: call void @llvm.memset.p1i8.i64(i8 addrspace(1)* [[DST:%.*]], i8 [[VAL:%.*]], i64 8, i1 false)
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; OPT8-NEXT: ret void
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;
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; OPT4-LABEL: @memset_size_8(
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; OPT4-NEXT: br i1 false, label [[SPLIT:%.*]], label [[LOADSTORELOOP:%.*]]
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; OPT4: loadstoreloop:
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; OPT4-NEXT: [[TMP1:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], [[LOADSTORELOOP]] ]
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; OPT4-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[DST:%.*]], i64 [[TMP1]]
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; OPT4-NEXT: store i8 [[VAL:%.*]], i8 addrspace(1)* [[TMP2]]
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; OPT4-NEXT: [[TMP3]] = add i64 [[TMP1]], 1
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; OPT4-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 8
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; OPT4-NEXT: br i1 [[TMP4]], label [[LOADSTORELOOP]], label [[SPLIT]]
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; OPT4: split:
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; OPT4-NEXT: ret void
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;
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; OPT0-LABEL: @memset_size_8(
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; OPT0-NEXT: br i1 false, label [[SPLIT:%.*]], label [[LOADSTORELOOP:%.*]]
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; OPT0: loadstoreloop:
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; OPT0-NEXT: [[TMP1:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], [[LOADSTORELOOP]] ]
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; OPT0-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[DST:%.*]], i64 [[TMP1]]
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; OPT0-NEXT: store i8 [[VAL:%.*]], i8 addrspace(1)* [[TMP2]]
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; OPT0-NEXT: [[TMP3]] = add i64 [[TMP1]], 1
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; OPT0-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 8
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; OPT0-NEXT: br i1 [[TMP4]], label [[LOADSTORELOOP]], label [[SPLIT]]
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; OPT0: split:
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; OPT0-NEXT: ret void
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;
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; OPT_NEG-LABEL: @memset_size_8(
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; OPT_NEG-NEXT: br i1 false, label [[SPLIT:%.*]], label [[LOADSTORELOOP:%.*]]
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; OPT_NEG: loadstoreloop:
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; OPT_NEG-NEXT: [[TMP1:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], [[LOADSTORELOOP]] ]
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; OPT_NEG-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[DST:%.*]], i64 [[TMP1]]
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; OPT_NEG-NEXT: store i8 [[VAL:%.*]], i8 addrspace(1)* [[TMP2]]
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; OPT_NEG-NEXT: [[TMP3]] = add i64 [[TMP1]], 1
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; OPT_NEG-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 8
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; OPT_NEG-NEXT: br i1 [[TMP4]], label [[LOADSTORELOOP]], label [[SPLIT]]
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; OPT_NEG: split:
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; OPT_NEG-NEXT: ret void
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;
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call void @llvm.memset.p1i8.i64(i8 addrspace(1)* %dst, i8 %val, i64 8, i1 false)
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ret void
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}
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declare void @llvm.memset.p1i8.i64(i8 addrspace(1)* nocapture writeonly, i8, i64, i1 immarg) #0
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attributes #0 = { argmemonly nounwind willreturn writeonly }
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