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llvm-project/llvm/test/CodeGen/SystemZ/pr32505.ll

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[SystemZ] Prevent Merging Bitcast with non-normal loads Fixes PR32505. Reviewers: uweigand, jonpa Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31609 llvm-svn: 299552
2017-04-05 23:42:48 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=zEC12 -o - %s | FileCheck %s
target triple = "s390x-ibm-linux"
define <2 x float> @pr32505(<2 x i8> * %a) {
; CHECK-LABEL: pr32505:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0:
[SystemZ] Prevent Merging Bitcast with non-normal loads Fixes PR32505. Reviewers: uweigand, jonpa Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31609 llvm-svn: 299552
2017-04-05 23:42:48 +08:00
; CHECK-NEXT: lbh %r0, 1(%r2)
[SystemZ] Enable machine scheduler. The machine scheduler (before register allocation) is enabled by default for SystemZ. The SelectionDAG scheduling preference now becomes source order scheduling (was regpressure). Review: Ulrich Weigand https://reviews.llvm.org/D37977 llvm-svn: 315063
2017-10-06 21:59:28 +08:00
; CHECK-NEXT: lbh %r1, 0(%r2)
; CHECK-NEXT: ldgr %f0, %r1
[SystemZ] Prevent Merging Bitcast with non-normal loads Fixes PR32505. Reviewers: uweigand, jonpa Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31609 llvm-svn: 299552
2017-04-05 23:42:48 +08:00
; CHECK-NEXT: ldgr %f2, %r0
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
; CHECK-NEXT: # kill: def $f0s killed $f0s killed $f0d
; CHECK-NEXT: # kill: def $f2s killed $f2s killed $f2d
[SystemZ] Prevent Merging Bitcast with non-normal loads Fixes PR32505. Reviewers: uweigand, jonpa Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31609 llvm-svn: 299552
2017-04-05 23:42:48 +08:00
; CHECK-NEXT: br %r14
%L17 = load <2 x i8>, <2 x i8>* %a
%Se21 = sext <2 x i8> %L17 to <2 x i32>
%BC = bitcast <2 x i32> %Se21 to <2 x float>
ret <2 x float> %BC
}