forked from OSchip/llvm-project
73 lines
2.1 KiB
LLVM
73 lines
2.1 KiB
LLVM
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; RUN: llc -march=hexagon -O3 < %s | FileCheck %s
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target triple = "hexagon"
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; CHECK-LABEL: f0:
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; CHECK: p{{[0-9]+}} = sfcmp.ge(r{{[0-9]+}},r{{[0-9]+}})
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; CHECK: p{{[0-9]+}} = sfcmp.gt(r{{[0-9]+}},r{{[0-9]+}})
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define i32 @f0(float* nocapture %a0) #0 {
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b0:
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%v0 = load float, float* %a0, align 4, !tbaa !0
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%v1 = fcmp olt float %v0, 6.000000e+01
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br i1 %v1, label %b1, label %b2
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b1: ; preds = %b0
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%v2 = getelementptr inbounds float, float* %a0, i32 1
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%v3 = load float, float* %v2, align 4, !tbaa !0
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%v4 = fcmp ogt float %v3, 0x3FECCCCCC0000000
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br label %b2
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b2: ; preds = %b1, %b0
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%v5 = phi i1 [ false, %b0 ], [ %v4, %b1 ]
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%v6 = zext i1 %v5 to i32
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ret i32 %v6
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}
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; CHECK-LABEL: f1:
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; CHECK: p{{[0-9]+}} = sfcmp.eq(r{{[0-9]+}},r{{[0-9]+}})
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define i32 @f1(float* nocapture %a0) #0 {
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b0:
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%v0 = load float, float* %a0, align 4, !tbaa !0
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%v1 = fcmp oeq float %v0, 6.000000e+01
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%v2 = zext i1 %v1 to i32
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ret i32 %v2
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}
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; CHECK-LABEL: f2:
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; CHECK: p{{[0-9]+}} = dfcmp.ge(r{{[0-9]+}}:{{[0-9]+}},r{{[0-9]+}}:{{[0-9]+}})
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; CHECK: p{{[0-9]+}} = dfcmp.gt(r{{[0-9]+}}:{{[0-9]+}},r{{[0-9]+}}:{{[0-9]+}})
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define i32 @f2(double* nocapture %a0) #0 {
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b0:
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%v0 = load double, double* %a0, align 8, !tbaa !4
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%v1 = fcmp olt double %v0, 6.000000e+01
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br i1 %v1, label %b1, label %b2
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b1: ; preds = %b0
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%v2 = getelementptr inbounds double, double* %a0, i32 1
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%v3 = load double, double* %v2, align 8, !tbaa !4
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%v4 = fcmp ogt double %v3, 0x3FECCCCCC0000000
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br label %b2
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b2: ; preds = %b1, %b0
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%v5 = phi i1 [ false, %b0 ], [ %v4, %b1 ]
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%v6 = zext i1 %v5 to i32
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ret i32 %v6
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}
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define i32 @f3(double* nocapture %a0) #0 {
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b0:
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%v0 = load double, double* %a0, align 8, !tbaa !4
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%v1 = fcmp oeq double %v0, 6.000000e+01
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%v2 = zext i1 %v1 to i32
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ret i32 %v2
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}
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attributes #0 = { nounwind readonly "target-cpu"="hexagonv55" "no-nans-fp-math"="true" }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"float", !2}
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!2 = !{!"omnipotent char", !3}
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!3 = !{!"Simple C/C++ TBAA"}
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!4 = !{!5, !5, i64 0}
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!5 = !{!"double", !2}
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