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llvm-project/llvm/test/MC/ARM/thumb-load-store-multiple.s

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ARM: fix an off-by-one in the register list access Fix an off-by-one access introduced in 224502 for push.w and pop.w with single register operands. Add test cases for both scenarios. Thanks to Asiri Rathnayake for pointing out the failure! llvm-svn: 224521
2014-12-19 00:16:53 +08:00
@ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o - %s 2>&1 \
ARM: improve instruction validation for thumb mode The ARM Architecture Reference Manual states the following: LDM{,IA,DB}: The SP cannot be in the list. The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. POP: The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. PUSH: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. STM:{,IA,DB}: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. llvm-svn: 224502
2014-12-18 13:24:38 +08:00
@ RUN: | FileCheck %s
Correct POP handling for v7m llvm-svn: 225972
2015-01-14 18:48:16 +08:00
@ RUN: not llvm-mc -triple thumbv7a-eabi -filetype asm -o - %s 2>&1 \
@ RUN: | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7A %s
@ RUN: not llvm-mc -triple thumbv7m-eabi -filetype asm -o - %s 2>&1 \
@ RUN: | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7M %s
ARM: improve instruction validation for thumb mode The ARM Architecture Reference Manual states the following: LDM{,IA,DB}: The SP cannot be in the list. The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. POP: The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. PUSH: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. STM:{,IA,DB}: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. llvm-svn: 224502
2014-12-18 13:24:38 +08:00
.syntax unified
.thumb
.global ldm
.type ldm,%function
Correct POP handling for v7m llvm-svn: 225972
2015-01-14 18:48:16 +08:00
ldm:
ARM: improve instruction validation for thumb mode The ARM Architecture Reference Manual states the following: LDM{,IA,DB}: The SP cannot be in the list. The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. POP: The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. PUSH: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. STM:{,IA,DB}: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. llvm-svn: 224502
2014-12-18 13:24:38 +08:00
ldm r0!, {r1, sp}
@ CHECK: error: SP may not be in the register list
@ CHECK: ldm r0!, {r1, sp}
@ CHECK: ^
ldm r0!, {lr, pc}
@ CHECK: error: PC and LR may not be in the register list simultaneously
@ CHECK: ldm r0!, {lr, pc}
@ CHECK: ^
itt eq
ldmeq r0!, {r1, pc}
ldmeq r0!, {r2, lr}
@ CHECK: error: instruction must be outside of IT block or the last instruction in an IT block
@ CHECK: ldmeq r0!, {r1, pc}
@ CHECK: ^
.global ldmdb
.type ldmdb,%function
ldmdb:
ldmdb r0!, {r1, sp}
@ CHECK: error: SP may not be in the register list
Correct POP handling for v7m llvm-svn: 225972
2015-01-14 18:48:16 +08:00
ldmdb r0!, {lr, pc}
ARM: improve instruction validation for thumb mode The ARM Architecture Reference Manual states the following: LDM{,IA,DB}: The SP cannot be in the list. The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. POP: The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. PUSH: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. STM:{,IA,DB}: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. llvm-svn: 224502
2014-12-18 13:24:38 +08:00
@ error: PC and LR may not be in the register list simultaneously
itt eq
ldmeq r0!, {r1, pc}
ldmeq r0!, {r2, lr}
@ CHECK: error: instruction must be outside of IT block or the last instruction in an IT block
@ CHECK: ldmeq r0!, {r1, pc}
@ CHECK: ^
.global stm
.type stm,%function
stm:
stm r0!, {r1, sp}
@ CHECK: error: SP may not be in the register list
stm r0!, {r2, pc}
@ CHECK: error: PC may not be in the register list
stm r0!, {sp, pc}
@ CHECK: error: SP and PC may not be in the register list
.global stmdb
.type stmdb,%function
stmdb:
stmdb r0!, {r1, sp}
@ CHECK: error: SP may not be in the register list
stmdb r0!, {r2, pc}
@ CHECK: error: PC may not be in the register list
stmdb r0!, {sp, pc}
@ CHECK: error: SP and PC may not be in the register list
.global push
.type push,%function
push:
push {sp}
@ CHECK: error: SP may not be in the register list
push {pc}
@ CHECK: error: PC may not be in the register list
Correct POP handling for v7m llvm-svn: 225972
2015-01-14 18:48:16 +08:00
push {sp, pc}
ARM: improve instruction validation for thumb mode The ARM Architecture Reference Manual states the following: LDM{,IA,DB}: The SP cannot be in the list. The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. POP: The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. PUSH: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. STM:{,IA,DB}: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. llvm-svn: 224502
2014-12-18 13:24:38 +08:00
@ CHECK: error: SP and PC may not be in the register list
.global pop
.type pop,%function
pop:
Correct POP handling for v7m llvm-svn: 225972
2015-01-14 18:48:16 +08:00
pop {sp}
@ CHECK-V7M: error: SP may not be in the register list
ARM: improve instruction validation for thumb mode The ARM Architecture Reference Manual states the following: LDM{,IA,DB}: The SP cannot be in the list. The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. POP: The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. PUSH: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. STM:{,IA,DB}: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. llvm-svn: 224502
2014-12-18 13:24:38 +08:00
pop {lr, pc}
@ CHECK: error: PC and LR may not be in the register list simultaneously
@ CHECK: pop {lr, pc}
@ CHECK: ^
itt eq
popeq {r1, pc}
popeq {r2, lr}
@ CHECK: error: instruction must be outside of IT block or the last instruction in an IT block
@ CHECK: popeq {r1, pc}
@ CHECK: ^
ARM: fix an off-by-one in the register list access Fix an off-by-one access introduced in 224502 for push.w and pop.w with single register operands. Add test cases for both scenarios. Thanks to Asiri Rathnayake for pointing out the failure! llvm-svn: 224521
2014-12-19 00:16:53 +08:00
.global valid
.type valid,%function
valid:
pop {sp}
Correct POP handling for v7m llvm-svn: 225972
2015-01-14 18:48:16 +08:00
@ CHECK-V7A: ldr sp, [sp], #4
ARM: fix an off-by-one in the register list access Fix an off-by-one access introduced in 224502 for push.w and pop.w with single register operands. Add test cases for both scenarios. Thanks to Asiri Rathnayake for pointing out the failure! llvm-svn: 224521
2014-12-19 00:16:53 +08:00
pop {sp, pc}
Correct POP handling for v7m llvm-svn: 225972
2015-01-14 18:48:16 +08:00
@ CHECK-V7A: pop.w {sp, pc}
ARM: fix an off-by-one in the register list access Fix an off-by-one access introduced in 224502 for push.w and pop.w with single register operands. Add test cases for both scenarios. Thanks to Asiri Rathnayake for pointing out the failure! llvm-svn: 224521
2014-12-19 00:16:53 +08:00
push.w {r0}
@ CHECK: str r0, [sp, #-4]
pop.w {r0}
@ CHECK: ldr r0, [sp], #4