2014-05-09 17:46:21 +08:00
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//=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips32r6 instructions.
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//
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//===----------------------------------------------------------------------===//
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2014-05-12 23:12:45 +08:00
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include "Mips32r6InstrFormats.td"
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2014-05-09 17:46:21 +08:00
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// Notes about removals/changes from MIPS32r6:
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// Unclear: ssnop
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// Reencoded: cache, pref
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// Reencoded: clo, clz
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// Reencoded: jr -> jalr
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// Reencoded: jr.hb -> jalr.hb
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// Reencoded: ldc2
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// Reencoded: ll, sc
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// Reencoded: lwc2
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// Reencoded: sdbbp
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// Reencoded: sdc2
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// Reencoded: swc2
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// Removed: /.ps$/, cvt.ps.s, cvt.ps.pw
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// Removed: addi
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// Removed: bc1any2, bc1any4
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// Removed: bc2[ft]
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// Removed: bc2f, bc2t
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// Removed: bgezal
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// Removed: bltzal
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// Removed: c.cond.fmt, bc1[ft]
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// Removed: div, divu
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// Removed: jalx
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// Removed: ldxc1
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// Removed: luxc1
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// Removed: lwl, lwr, lwle, lwre, swl, swr, swle, swre
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// Removed: lwxc1
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// Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds]
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// Removed: mfhi, mflo, mthi, mtlo, madd, maddu, msub, msubu, mul
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// Removed: movf, movt
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// Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
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// Removed: movn, movz
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// Removed: mult, multu
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// Removed: prefx
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// Removed: sdxc1
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// Removed: suxc1
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// Removed: swxc1
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// Removed: teqi, tgei, tgeiu, tlti, tltiu, tnei
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// Rencoded: [ls][wd]c2
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2014-05-12 23:12:45 +08:00
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//===----------------------------------------------------------------------===//
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//
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// Instruction Encodings
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//
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//===----------------------------------------------------------------------===//
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2014-05-15 18:45:58 +08:00
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class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
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2014-05-15 20:06:36 +08:00
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class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
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2014-05-15 18:45:58 +08:00
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class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
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2014-05-15 18:27:19 +08:00
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class AUI_ENC : AUI_FM;
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2014-05-15 18:45:58 +08:00
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class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
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2014-05-15 20:18:23 +08:00
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class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
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2014-05-12 23:24:16 +08:00
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class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
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class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
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class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
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class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
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2014-05-12 23:12:45 +08:00
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class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
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class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
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class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
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class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
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2014-05-14 23:29:44 +08:00
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class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
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class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
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2014-05-12 23:12:45 +08:00
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2014-05-15 22:54:06 +08:00
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class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
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class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
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class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
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class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
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class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
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class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
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class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
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class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
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2014-05-12 23:12:45 +08:00
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//===----------------------------------------------------------------------===//
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//
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// Instruction Descriptions
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//
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//===----------------------------------------------------------------------===//
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2014-05-15 18:45:58 +08:00
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class ADDIUPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
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dag OutOperandList = (outs GPROpnd:$rs);
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dag InOperandList = (ins simm19_lsl2:$imm);
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string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
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list<dag> Pattern = [];
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}
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class ADDIUPC_DESC : ADDIUPC_DESC_BASE<"addiupc", GPR32Opnd>;
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2014-05-15 20:06:36 +08:00
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class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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Operand ImmOpnd> {
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dag OutOperandList = (outs GPROpnd:$rd);
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dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
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string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
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list<dag> Pattern = [];
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}
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class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
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2014-05-15 18:45:58 +08:00
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class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
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dag OutOperandList = (outs GPROpnd:$rs);
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dag InOperandList = (ins simm16:$imm);
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string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
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list<dag> Pattern = [];
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}
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class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
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class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
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2014-05-15 18:27:19 +08:00
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class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
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dag OutOperandList = (outs GPROpnd:$rs);
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dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
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string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
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list<dag> Pattern = [];
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}
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class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
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2014-05-15 20:18:23 +08:00
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class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
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dag OutOperandList = (outs GPROpnd:$rd);
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dag InOperandList = (ins GPROpnd:$rt);
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string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
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list<dag> Pattern = [];
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}
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class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
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2014-05-12 23:24:16 +08:00
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class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
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dag OutOperandList = (outs GPROpnd:$rd);
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dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
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string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
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list<dag> Pattern = [];
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}
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class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd>;
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class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd>;
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class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd>;
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class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd>;
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2014-05-12 23:12:45 +08:00
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class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
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dag OutOperandList = (outs GPROpnd:$rd);
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dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
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string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
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list<dag> Pattern = [];
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}
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class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd>;
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class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd>;
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class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd>;
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class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
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2014-05-14 23:29:44 +08:00
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class SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
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dag OutOperandList = (outs FGROpnd:$fd);
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dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
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string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
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list<dag> Pattern = [];
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string Constraints = "$fd_in = $fd";
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}
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class SEL_D_DESC : SEL_DESC_BASE<"sel.d", FGR64Opnd>;
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class SEL_S_DESC : SEL_DESC_BASE<"sel.s", FGR32Opnd>;
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2014-05-15 22:54:06 +08:00
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class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
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dag OutOperandList = (outs FGROpnd:$fd);
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dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
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string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
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list<dag> Pattern = [];
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}
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class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
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class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
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class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
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class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
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class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
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class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
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class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
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class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
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2014-05-12 23:12:45 +08:00
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//===----------------------------------------------------------------------===//
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//
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// Instruction Definitions
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//
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//===----------------------------------------------------------------------===//
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2014-05-15 18:45:58 +08:00
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def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
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2014-05-15 20:06:36 +08:00
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def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
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2014-05-15 18:45:58 +08:00
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def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
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2014-05-15 18:27:19 +08:00
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def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
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2014-05-15 18:45:58 +08:00
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def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
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2014-05-09 17:46:21 +08:00
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def BALC;
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def BC1EQZ;
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def BC1NEZ;
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def BC2EQZ;
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def BC2NEZ;
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def BC;
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def BEQC;
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def BEQZALC;
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def BEQZC;
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def BGEC; // Also aliased to blec with operands swapped
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def BGEUC; // Also aliased to bleuc with operands swapped
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def BGEZALC;
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def BGEZC;
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def BGTZALC;
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def BGTZC;
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2014-05-15 20:18:23 +08:00
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def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
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2014-05-09 17:46:21 +08:00
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def BLEZALC;
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def BLEZC;
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def BLTC; // Also aliased to bgtc with operands swapped
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def BLTUC; // Also aliased to bgtuc with operands swapped
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def BLTZALC;
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def BLTZC;
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def BNEC;
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def BNEZALC;
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def BNEZC;
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def BNVC;
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def BOVC;
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def CLASS_D;
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def CLASS_S;
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def CMP_CC_D;
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def CMP_CC_S;
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2014-05-12 23:24:16 +08:00
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def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
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def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
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2014-05-09 17:46:21 +08:00
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def JIALC;
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def JIC;
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// def LSA; // See MSA
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def LWPC;
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def LWUPC;
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def MADDF;
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2014-05-15 22:54:06 +08:00
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def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
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def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
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def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
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def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
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def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
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def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
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def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
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def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
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2014-05-12 23:24:16 +08:00
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def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
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def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
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2014-05-09 17:46:21 +08:00
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def MSUBF;
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2014-05-12 23:12:45 +08:00
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def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
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def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
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def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
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def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
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2014-05-09 17:46:21 +08:00
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def NAL; // BAL with rd=0
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def RINT_D;
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def RINT_S;
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def SELEQZ;
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def SELEQZ_D;
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def SELEQZ_S;
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def SELNEZ;
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def SELNEZ_D;
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def SELNEZ_S;
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2014-05-14 23:29:44 +08:00
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def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
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def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;
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