maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/lib/Target/MBlaze/MBlazeInstrFPU.td

223 lines
10 KiB
TableGen
Raw Normal View History

fix emacs language spec's, patch by Edmund Grimley-Evans! llvm-svn: 111241
2010-08-18 00:20:04 +08:00
//===- MBlazeInstrFPU.td - MBlaze FPU Instruction defs -----*- tablegen -*-===//
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// MBlaze profiles and nodes
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// MBlaze Operand, Complex Patterns and Transformations Definitions.
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Memory Access Instructions
//===----------------------------------------------------------------------===//
class LoadFM<bits<6> op, string instr_asm, PatFrag OpNode> :
Adding initial AsmParser implementation for the MBlaze backend. It is mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. llvm-svn: 117054
2010-10-22 03:48:38 +08:00
TA<op, 0x000, (outs GPR:$dst), (ins memrr:$addr),
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
!strconcat(instr_asm, " $dst, $addr"),
Adding initial AsmParser implementation for the MBlaze backend. It is mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. llvm-svn: 117054
2010-10-22 03:48:38 +08:00
[(set (f32 GPR:$dst), (OpNode xaddr:$addr))], IILoad>;
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
class LoadFMI<bits<6> op, string instr_asm, PatFrag OpNode> :
Adding initial AsmParser implementation for the MBlaze backend. It is mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. llvm-svn: 117054
2010-10-22 03:48:38 +08:00
TB<op, (outs GPR:$dst), (ins memri:$addr),
Recommit 116986 with capitalization typo fixed. llvm-svn: 116993
2010-10-21 11:57:26 +08:00
!strconcat(instr_asm, " $dst, $addr"),
Adding initial AsmParser implementation for the MBlaze backend. It is mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. llvm-svn: 117054
2010-10-22 03:48:38 +08:00
[(set (f32 GPR:$dst), (OpNode iaddr:$addr))], IILoad>;
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
class StoreFM<bits<6> op, string instr_asm, PatFrag OpNode> :
Adding initial AsmParser implementation for the MBlaze backend. It is mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. llvm-svn: 117054
2010-10-22 03:48:38 +08:00
TA<op, 0x000, (outs), (ins GPR:$dst, memrr:$addr),
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
!strconcat(instr_asm, " $dst, $addr"),
Adding initial AsmParser implementation for the MBlaze backend. It is mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. llvm-svn: 117054
2010-10-22 03:48:38 +08:00
[(OpNode (f32 GPR:$dst), xaddr:$addr)], IIStore>;
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
class StoreFMI<bits<6> op, string instr_asm, PatFrag OpNode> :
Adding initial AsmParser implementation for the MBlaze backend. It is mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. llvm-svn: 117054
2010-10-22 03:48:38 +08:00
TB<op, (outs), (ins GPR:$dst, memrr:$addr),
Recommit 116986 with capitalization typo fixed. llvm-svn: 116993
2010-10-21 11:57:26 +08:00
!strconcat(instr_asm, " $dst, $addr"),
Adding initial AsmParser implementation for the MBlaze backend. It is mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. llvm-svn: 117054
2010-10-22 03:48:38 +08:00
[(OpNode (f32 GPR:$dst), iaddr:$addr)], IIStore>;
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
class ArithF<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
InstrItinClass itin> :
Adding initial AsmParser implementation for the MBlaze backend. It is mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. llvm-svn: 117054
2010-10-22 03:48:38 +08:00
TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
!strconcat(instr_asm, " $dst, $b, $c"),
Adding initial AsmParser implementation for the MBlaze backend. It is mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. llvm-svn: 117054
2010-10-22 03:48:38 +08:00
[(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
class CmpFN<bits<6> op, bits<11> flags, string instr_asm,
InstrItinClass itin> :
Adding initial AsmParser implementation for the MBlaze backend. It is mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. llvm-svn: 117054
2010-10-22 03:48:38 +08:00
TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
!strconcat(instr_asm, " $dst, $b, $c"),
[], itin>;
class ArithFR<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
InstrItinClass itin> :
Adding initial AsmParser implementation for the MBlaze backend. It is mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. llvm-svn: 117054
2010-10-22 03:48:38 +08:00
TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
!strconcat(instr_asm, " $dst, $c, $b"),
Adding initial AsmParser implementation for the MBlaze backend. It is mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. llvm-svn: 117054
2010-10-22 03:48:38 +08:00
[(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
class LogicF<bits<6> op, string instr_asm> :
Adding initial AsmParser implementation for the MBlaze backend. It is mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. llvm-svn: 117054
2010-10-22 03:48:38 +08:00
TB<op, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
Recommit 116986 with capitalization typo fixed. llvm-svn: 116993
2010-10-21 11:57:26 +08:00
!strconcat(instr_asm, " $dst, $b, $c"),
[], IIAlu>;
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
class LogicFI<bits<6> op, string instr_asm> :
Adding initial AsmParser implementation for the MBlaze backend. It is mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. llvm-svn: 117054
2010-10-22 03:48:38 +08:00
TB<op, (outs GPR:$dst), (ins GPR:$b, fimm:$c),
Recommit 116986 with capitalization typo fixed. llvm-svn: 116993
2010-10-21 11:57:26 +08:00
!strconcat(instr_asm, " $dst, $b, $c"),
[], IIAlu>;
let rb=0 in {
class ArithF2<bits<6> op, bits<11> flags, string instr_asm,
InstrItinClass itin> :
Adding initial AsmParser implementation for the MBlaze backend. It is mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. llvm-svn: 117054
2010-10-22 03:48:38 +08:00
TA<op, flags, (outs GPR:$dst), (ins GPR:$b),
Recommit 116986 with capitalization typo fixed. llvm-svn: 116993
2010-10-21 11:57:26 +08:00
!strconcat(instr_asm, " $dst, $b"),
[], itin>;
class ArithIF<bits<6> op, bits<11> flags, string instr_asm,
InstrItinClass itin> :
Adding initial AsmParser implementation for the MBlaze backend. It is mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. llvm-svn: 117054
2010-10-22 03:48:38 +08:00
TA<op, flags, (outs GPR:$dst), (ins GPR:$b),
Recommit 116986 with capitalization typo fixed. llvm-svn: 116993
2010-10-21 11:57:26 +08:00
!strconcat(instr_asm, " $dst, $b"),
[], itin>;
class ArithFI<bits<6> op, bits<11> flags, string instr_asm,
InstrItinClass itin> :
Adding initial AsmParser implementation for the MBlaze backend. It is mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. llvm-svn: 117054
2010-10-22 03:48:38 +08:00
TA<op, flags, (outs GPR:$dst), (ins GPR:$b),
Recommit 116986 with capitalization typo fixed. llvm-svn: 116993
2010-10-21 11:57:26 +08:00
!strconcat(instr_asm, " $dst, $b"),
[], itin>;
}
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
//===----------------------------------------------------------------------===//
// Pseudo instructions
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// FPU Arithmetic Instructions
//===----------------------------------------------------------------------===//
let Predicates=[HasFPU] in {
def FORI : LogicFI<0x28, "ori ">;
def FADD : ArithF<0x16, 0x000, "fadd ", fadd, IIAlu>;
def FRSUB : ArithFR<0x16, 0x080, "frsub ", fsub, IIAlu>;
def FMUL : ArithF<0x16, 0x100, "fmul ", fmul, IIAlu>;
def FDIV : ArithF<0x16, 0x180, "fdiv ", fdiv, IIAlu>;
def LWF : LoadFM<0x32, "lw ", load>;
def LWFI : LoadFMI<0x32, "lwi ", load>;
def SWF : StoreFM<0x32, "sw ", store>;
def SWFI : StoreFMI<0x32, "swi ", store>;
}
let Predicates=[HasFPU,HasSqrt] in {
def FLT : ArithIF<0x16, 0x280, "flt ", IIAlu>;
def FINT : ArithFI<0x16, 0x300, "fint ", IIAlu>;
def FSQRT : ArithF2<0x16, 0x300, "fsqrt ", IIAlu>;
}
let isAsCheapAsAMove = 1 in {
def FCMP_UN : CmpFN<0x16, 0x200, "fcmp.un", IIAlu>;
def FCMP_LT : CmpFN<0x16, 0x210, "fcmp.lt", IIAlu>;
def FCMP_EQ : CmpFN<0x16, 0x220, "fcmp.eq", IIAlu>;
def FCMP_LE : CmpFN<0x16, 0x230, "fcmp.le", IIAlu>;
def FCMP_GT : CmpFN<0x16, 0x240, "fcmp.gt", IIAlu>;
def FCMP_NE : CmpFN<0x16, 0x250, "fcmp.ne", IIAlu>;
def FCMP_GE : CmpFN<0x16, 0x260, "fcmp.ge", IIAlu>;
}
mark a few codegenonly instructions. llvm-svn: 118092
2010-11-03 06:26:33 +08:00
let usesCustomInserter = 1, isCodeGenOnly = 1 in {
Adding initial AsmParser implementation for the MBlaze backend. It is mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. llvm-svn: 117054
2010-10-22 03:48:38 +08:00
def Select_FCC : MBlazePseudo<(outs GPR:$dst),
(ins GPR:$T, GPR:$F, GPR:$CMP, i32imm:$CC),
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
"; SELECT_FCC PSEUDO!",
[]>;
}
// Floating point conversions
let Predicates=[HasFPU] in {
Adding initial AsmParser implementation for the MBlaze backend. It is mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. llvm-svn: 117054
2010-10-22 03:48:38 +08:00
def : Pat<(sint_to_fp GPR:$V), (FLT GPR:$V)>;
def : Pat<(fp_to_sint GPR:$V), (FINT GPR:$V)>;
def : Pat<(fsqrt GPR:$V), (FSQRT GPR:$V)>;
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
}
// SET_CC operations
let Predicates=[HasFPU] in {
Adding initial AsmParser implementation for the MBlaze backend. It is mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. llvm-svn: 117054
2010-10-22 03:48:38 +08:00
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETEQ),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
(FCMP_EQ GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETNE),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
(FCMP_EQ GPR:$L, GPR:$R), 1)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOEQ),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
(FCMP_EQ GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
(XOR (FCMP_UN GPR:$L, GPR:$R),
(FCMP_EQ GPR:$L, GPR:$R)), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
(OR (FCMP_UN GPR:$L, GPR:$R),
(FCMP_EQ GPR:$L, GPR:$R)), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETGT),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
(FCMP_GT GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETLT),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
(FCMP_LT GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETGE),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
(FCMP_GE GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETLE),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
(FCMP_LE GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOGT),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
(FCMP_GT GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOLT),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
(FCMP_LT GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOGE),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
(FCMP_GE GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOLE),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
(FCMP_LE GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUEQ),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
(OR (FCMP_UN GPR:$L, GPR:$R),
(FCMP_EQ GPR:$L, GPR:$R)), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUNE),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
(FCMP_NE GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUGT),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
(OR (FCMP_UN GPR:$L, GPR:$R),
(FCMP_GT GPR:$L, GPR:$R)), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETULT),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
(OR (FCMP_UN GPR:$L, GPR:$R),
(FCMP_LT GPR:$L, GPR:$R)), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUGE),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
(OR (FCMP_UN GPR:$L, GPR:$R),
(FCMP_GE GPR:$L, GPR:$R)), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETULE),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
(OR (FCMP_UN GPR:$L, GPR:$R),
(FCMP_LE GPR:$L, GPR:$R)), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETO),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
(FCMP_UN GPR:$L, GPR:$R), 1)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUO),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
(FCMP_UN GPR:$L, GPR:$R), 2)>;
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
}
// SELECT operations
Adding initial AsmParser implementation for the MBlaze backend. It is mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. llvm-svn: 117054
2010-10-22 03:48:38 +08:00
def : Pat<(select (i32 GPR:$C), (f32 GPR:$T), (f32 GPR:$F)),
(Select_FCC GPR:$T, GPR:$F, GPR:$C, 2)>;
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
//===----------------------------------------------------------------------===//
// Patterns for Floating Point Instructions
//===----------------------------------------------------------------------===//
Adding initial AsmParser implementation for the MBlaze backend. It is mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. llvm-svn: 117054
2010-10-22 03:48:38 +08:00
def : Pat<(f32 fpimm:$imm), (FORI (i32 R0), fpimm:$imm)>;