2007-06-06 15:42:06 +08:00
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//===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-06-06 15:42:06 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the MIPS target.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-isel"
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#include "Mips.h"
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#include "MipsISelLowering.h"
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2007-11-05 11:02:32 +08:00
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#include "MipsMachineFunction.h"
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2007-06-06 15:42:06 +08:00
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#include "MipsRegisterInfo.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetMachine.h"
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#include "llvm/GlobalValue.h"
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#include "llvm/Instructions.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/Support/CFG.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2007-12-31 12:13:23 +08:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2007-06-06 15:42:06 +08:00
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Debug.h"
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2009-07-09 04:53:28 +08:00
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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2007-06-06 15:42:06 +08:00
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MipsDAGToDAGISel - MIPS specific code to select MIPS machine
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// instructions for SelectionDAG operations.
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//===----------------------------------------------------------------------===//
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namespace {
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2009-10-25 14:33:48 +08:00
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class MipsDAGToDAGISel : public SelectionDAGISel {
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2007-06-06 15:42:06 +08:00
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/// TM - Keep a reference to MipsTargetMachine.
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MipsTargetMachine &TM;
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/// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
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/// make the right decision when generating code for different targets.
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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const MipsSubtarget &Subtarget;
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2007-06-06 15:42:06 +08:00
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public:
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2008-07-08 02:00:37 +08:00
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explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
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2009-01-16 03:20:50 +08:00
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SelectionDAGISel(tm),
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2008-10-04 00:55:19 +08:00
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TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
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2007-06-06 15:42:06 +08:00
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2008-08-23 10:25:05 +08:00
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virtual void InstructionSelect();
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2007-06-06 15:42:06 +08:00
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// Pass Name
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virtual const char *getPassName() const {
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return "MIPS DAG->DAG Pattern Instruction Selection";
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}
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private:
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// Include the pieces autogenerated from the target description.
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#include "MipsGenDAGISel.inc"
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2009-06-04 04:30:14 +08:00
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/// getTargetMachine - Return a reference to the TargetMachine, casted
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/// to the target-specific type.
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const MipsTargetMachine &getTargetMachine() {
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return static_cast<const MipsTargetMachine &>(TM);
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}
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/// getInstrInfo - Return a reference to the TargetInstrInfo, casted
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/// to the target-specific type.
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const MipsInstrInfo *getInstrInfo() {
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return getTargetMachine().getInstrInfo();
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}
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SDNode *getGlobalBaseReg();
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2010-01-05 09:24:18 +08:00
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SDNode *Select(SDNode *N);
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2007-06-06 15:42:06 +08:00
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// Complex Pattern.
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2010-01-05 09:24:18 +08:00
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bool SelectAddr(SDNode *Op, SDValue N,
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2008-07-28 05:46:04 +08:00
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SDValue &Base, SDValue &Offset);
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2007-06-06 15:42:06 +08:00
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2010-01-05 09:24:18 +08:00
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SDNode *SelectLoadFp64(SDNode *N);
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SDNode *SelectStoreFp64(SDNode *N);
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2007-06-06 15:42:06 +08:00
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// getI32Imm - Return a target constant with the specified
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// value, of type i32.
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2008-07-28 05:46:04 +08:00
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inline SDValue getI32Imm(unsigned Imm) {
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2009-08-12 04:47:22 +08:00
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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2007-06-06 15:42:06 +08:00
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}
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#ifndef NDEBUG
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unsigned Indent;
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#endif
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};
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}
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2008-07-01 04:45:06 +08:00
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/// InstructionSelect - This callback is invoked by
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2007-06-06 15:42:06 +08:00
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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2009-08-23 14:49:22 +08:00
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void MipsDAGToDAGISel::InstructionSelect() {
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2007-06-06 15:42:06 +08:00
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// Codegen the basic block.
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2009-08-23 14:49:22 +08:00
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DEBUG(errs() << "===== Instruction selection begins:\n");
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2009-08-23 16:50:52 +08:00
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DEBUG(Indent = 0);
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2007-06-06 15:42:06 +08:00
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// Select target instructions for the DAG.
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2008-10-28 05:56:29 +08:00
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SelectRoot(*CurDAG);
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2007-06-06 15:42:06 +08:00
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2009-08-23 14:49:22 +08:00
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DEBUG(errs() << "===== Instruction selection ends:\n");
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2007-06-06 15:42:06 +08:00
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2008-08-23 10:25:05 +08:00
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CurDAG->RemoveDeadNodes();
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2007-06-06 15:42:06 +08:00
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}
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2007-11-13 03:49:57 +08:00
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/// getGlobalBaseReg - Output the instructions required to put the
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/// GOT address into a register.
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2009-06-04 04:30:14 +08:00
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SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
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unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
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return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
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2007-11-13 03:49:57 +08:00
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}
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2007-06-06 15:42:06 +08:00
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/// ComplexPattern used on MipsInstrInfo
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/// Used on Mips Load/Store instructions
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bool MipsDAGToDAGISel::
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2010-01-05 09:24:18 +08:00
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SelectAddr(SDNode *Op, SDValue Addr, SDValue &Offset, SDValue &Base)
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2007-06-06 15:42:06 +08:00
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{
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// if Address is FI, get the TargetFrameIndex.
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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2009-08-12 04:47:22 +08:00
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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2007-06-06 15:42:06 +08:00
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return true;
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}
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2007-11-05 11:02:32 +08:00
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// on PIC code Load GA
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if (TM.getRelocationModel() == Reloc::PIC_) {
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2007-11-13 03:49:57 +08:00
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if ((Addr.getOpcode() == ISD::TargetGlobalAddress) ||
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2009-11-25 20:17:58 +08:00
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(Addr.getOpcode() == ISD::TargetConstantPool) ||
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2007-11-13 03:49:57 +08:00
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(Addr.getOpcode() == ISD::TargetJumpTable)){
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2009-08-12 04:47:22 +08:00
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Base = CurDAG->getRegister(Mips::GP, MVT::i32);
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2007-11-05 11:02:32 +08:00
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Offset = Addr;
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return true;
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}
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} else {
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2008-09-17 05:48:12 +08:00
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if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
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2007-11-05 11:02:32 +08:00
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Addr.getOpcode() == ISD::TargetGlobalAddress))
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return false;
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}
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2007-06-06 15:42:06 +08:00
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2007-08-18 10:16:30 +08:00
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// Operand is a result from an ADD.
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2007-11-05 11:02:32 +08:00
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if (Addr.getOpcode() == ISD::ADD) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
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if (Predicate_immSExt16(CN)) {
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2007-06-06 15:42:06 +08:00
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// If the first operand is a FI, get the TargetFI Node
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
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(Addr.getOperand(0))) {
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2009-08-12 04:47:22 +08:00
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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2007-06-06 15:42:06 +08:00
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} else {
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Base = Addr.getOperand(0);
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}
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2009-08-12 04:47:22 +08:00
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Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
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2007-06-06 15:42:06 +08:00
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return true;
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}
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}
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2009-11-16 12:33:42 +08:00
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// When loading from constant pools, load the lower address part in
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2009-11-25 20:17:58 +08:00
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// the instruction itself. Example, instead of:
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2009-11-16 12:33:42 +08:00
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// lui $2, %hi($CPI1_0)
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// addiu $2, $2, %lo($CPI1_0)
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// lwc1 $f0, 0($2)
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// Generate:
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// lui $2, %hi($CPI1_0)
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// lwc1 $f0, %lo($CPI1_0)($2)
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2009-11-25 20:17:58 +08:00
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if ((Addr.getOperand(0).getOpcode() == MipsISD::Hi ||
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Addr.getOperand(0).getOpcode() == ISD::LOAD) &&
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2009-11-16 12:33:42 +08:00
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Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
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SDValue LoVal = Addr.getOperand(1);
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2009-11-25 20:17:58 +08:00
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if (dyn_cast<ConstantPoolSDNode>(LoVal.getOperand(0))) {
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Base = Addr.getOperand(0);
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Offset = LoVal.getOperand(0);
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return true;
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2009-11-16 12:33:42 +08:00
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}
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}
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2007-06-06 15:42:06 +08:00
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}
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2007-07-12 07:24:41 +08:00
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Base = Addr;
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2009-08-12 04:47:22 +08:00
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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2007-06-06 15:42:06 +08:00
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return true;
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}
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2010-01-05 09:24:18 +08:00
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SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDNode *N) {
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2009-11-19 14:06:13 +08:00
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MVT::SimpleValueType NVT =
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2010-01-05 09:24:18 +08:00
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N->getValueType(0).getSimpleVT().SimpleTy;
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2009-11-19 14:06:13 +08:00
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if (!Subtarget.isMips1() || NVT != MVT::f64)
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return NULL;
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2010-01-05 09:24:18 +08:00
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if (!Predicate_unindexedload(N) ||
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!Predicate_load(N))
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2009-11-19 14:06:13 +08:00
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return NULL;
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2010-01-05 09:24:18 +08:00
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SDValue Chain = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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2009-11-19 14:06:13 +08:00
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SDValue Offset0, Offset1, Base;
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if (!SelectAddr(N, N1, Offset0, Base) ||
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N1.getValueType() != MVT::i32)
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return NULL;
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MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
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MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
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2010-01-05 09:24:18 +08:00
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DebugLoc dl = N->getDebugLoc();
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2009-11-19 14:06:13 +08:00
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// The second load should start after for 4 bytes.
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
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Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
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else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Offset0))
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Offset1 = CurDAG->getTargetConstantPool(CP->getConstVal(),
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MVT::i32,
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CP->getAlignment(),
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CP->getOffset()+4,
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CP->getTargetFlags());
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else
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return NULL;
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2009-11-25 09:05:25 +08:00
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// Choose the offsets depending on the endianess
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if (TM.getTargetData()->isBigEndian())
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std::swap(Offset0, Offset1);
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2009-11-19 14:06:13 +08:00
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// Instead of:
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// ldc $f0, X($3)
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// Generate:
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// lwc $f0, X($3)
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// lwc $f1, X+4($3)
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SDNode *LD0 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
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MVT::Other, Offset0, Base, Chain);
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2010-02-10 03:54:29 +08:00
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SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
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2009-11-19 14:06:13 +08:00
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dl, NVT), 0);
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SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::SUBREG_FPEVEN, dl,
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MVT::f64, Undef, SDValue(LD0, 0));
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SDNode *LD1 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
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MVT::Other, Offset1, Base, SDValue(LD0, 1));
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SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::SUBREG_FPODD, dl,
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MVT::f64, I0, SDValue(LD1, 0));
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2010-01-05 09:24:18 +08:00
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ReplaceUses(SDValue(N, 0), I1);
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ReplaceUses(SDValue(N, 1), Chain);
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2009-11-19 14:06:13 +08:00
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cast<MachineSDNode>(LD0)->setMemRefs(MemRefs0, MemRefs0 + 1);
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cast<MachineSDNode>(LD1)->setMemRefs(MemRefs0, MemRefs0 + 1);
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return I1.getNode();
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}
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2010-01-05 09:24:18 +08:00
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SDNode *MipsDAGToDAGISel::SelectStoreFp64(SDNode *N) {
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2009-11-19 14:06:13 +08:00
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if (!Subtarget.isMips1() ||
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2010-01-05 09:24:18 +08:00
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N->getOperand(1).getValueType() != MVT::f64)
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2009-11-19 14:06:13 +08:00
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return NULL;
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2010-01-05 09:24:18 +08:00
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SDValue Chain = N->getOperand(0);
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2009-11-19 14:06:13 +08:00
|
|
|
|
2010-01-05 09:24:18 +08:00
|
|
|
if (!Predicate_unindexedstore(N) ||
|
|
|
|
!Predicate_store(N))
|
2009-11-19 14:06:13 +08:00
|
|
|
return NULL;
|
|
|
|
|
2010-01-05 09:24:18 +08:00
|
|
|
SDValue N1 = N->getOperand(1);
|
|
|
|
SDValue N2 = N->getOperand(2);
|
2009-11-19 14:06:13 +08:00
|
|
|
SDValue Offset0, Offset1, Base;
|
|
|
|
|
|
|
|
if (!SelectAddr(N, N2, Offset0, Base) ||
|
|
|
|
N1.getValueType() != MVT::f64 ||
|
|
|
|
N2.getValueType() != MVT::i32)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
|
|
|
|
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
|
2010-01-05 09:24:18 +08:00
|
|
|
DebugLoc dl = N->getDebugLoc();
|
2009-11-19 14:06:13 +08:00
|
|
|
|
|
|
|
// Get the even and odd part from the f64 register
|
|
|
|
SDValue FPOdd = CurDAG->getTargetExtractSubreg(Mips::SUBREG_FPODD,
|
|
|
|
dl, MVT::f32, N1);
|
|
|
|
SDValue FPEven = CurDAG->getTargetExtractSubreg(Mips::SUBREG_FPEVEN,
|
|
|
|
dl, MVT::f32, N1);
|
|
|
|
|
|
|
|
// The second store should start after for 4 bytes.
|
|
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
|
|
|
|
Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
|
|
|
|
else
|
|
|
|
return NULL;
|
|
|
|
|
2009-11-25 09:05:25 +08:00
|
|
|
// Choose the offsets depending on the endianess
|
|
|
|
if (TM.getTargetData()->isBigEndian())
|
|
|
|
std::swap(Offset0, Offset1);
|
|
|
|
|
2009-11-19 14:06:13 +08:00
|
|
|
// Instead of:
|
|
|
|
// sdc $f0, X($3)
|
|
|
|
// Generate:
|
|
|
|
// swc $f0, X($3)
|
|
|
|
// swc $f1, X+4($3)
|
|
|
|
SDValue Ops0[] = { FPEven, Offset0, Base, Chain };
|
|
|
|
Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
|
|
|
|
MVT::Other, Ops0, 4), 0);
|
|
|
|
cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
|
|
|
|
|
|
|
|
SDValue Ops1[] = { FPOdd, Offset1, Base, Chain };
|
|
|
|
Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
|
|
|
|
MVT::Other, Ops1, 4), 0);
|
|
|
|
cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
|
|
|
|
|
2010-01-05 09:24:18 +08:00
|
|
|
ReplaceUses(SDValue(N, 0), Chain);
|
2009-11-19 14:06:13 +08:00
|
|
|
return Chain.getNode();
|
|
|
|
}
|
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
/// Select instructions not customized! Used for
|
|
|
|
/// expanded, promoted and normal instructions
|
2010-01-05 09:24:18 +08:00
|
|
|
SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
|
2007-06-06 15:42:06 +08:00
|
|
|
unsigned Opcode = Node->getOpcode();
|
2009-02-05 07:02:30 +08:00
|
|
|
DebugLoc dl = Node->getDebugLoc();
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// Dump information about the Node being selected
|
2009-08-23 14:49:22 +08:00
|
|
|
DEBUG(errs().indent(Indent) << "Selecting: ";
|
|
|
|
Node->dump(CurDAG);
|
|
|
|
errs() << "\n");
|
2009-08-23 16:50:52 +08:00
|
|
|
DEBUG(Indent += 2);
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// If we have a custom node, we already have selected!
|
2008-07-18 03:10:17 +08:00
|
|
|
if (Node->isMachineOpcode()) {
|
2009-08-23 14:49:22 +08:00
|
|
|
DEBUG(errs().indent(Indent-2) << "== ";
|
|
|
|
Node->dump(CurDAG);
|
|
|
|
errs() << "\n");
|
2009-08-23 16:50:52 +08:00
|
|
|
DEBUG(Indent -= 2);
|
2007-06-06 15:42:06 +08:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
///
|
2007-09-25 04:15:11 +08:00
|
|
|
// Instruction Selection not handled by the auto-generated
|
|
|
|
// tablegen selection should be handled here.
|
2007-06-06 15:42:06 +08:00
|
|
|
///
|
|
|
|
switch(Opcode) {
|
|
|
|
|
|
|
|
default: break;
|
|
|
|
|
2008-06-06 14:37:31 +08:00
|
|
|
case ISD::SUBE:
|
2008-06-06 08:58:26 +08:00
|
|
|
case ISD::ADDE: {
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue InFlag = Node->getOperand(2), CmpLHS;
|
2008-12-15 05:38:24 +08:00
|
|
|
unsigned Opc = InFlag.getOpcode(); Opc=Opc;
|
2008-06-06 14:37:31 +08:00
|
|
|
assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
|
|
|
|
(Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
|
|
|
|
"(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
|
|
|
|
|
2008-12-15 05:38:24 +08:00
|
|
|
unsigned MOp;
|
2008-06-06 14:37:31 +08:00
|
|
|
if (Opcode == ISD::ADDE) {
|
|
|
|
CmpLHS = InFlag.getValue(0);
|
|
|
|
MOp = Mips::ADDu;
|
|
|
|
} else {
|
|
|
|
CmpLHS = InFlag.getOperand(0);
|
|
|
|
MOp = Mips::SUBu;
|
|
|
|
}
|
|
|
|
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
|
2008-06-06 08:58:26 +08:00
|
|
|
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue LHS = Node->getOperand(0);
|
|
|
|
SDValue RHS = Node->getOperand(1);
|
2008-06-06 08:58:26 +08:00
|
|
|
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT VT = LHS.getValueType();
|
2009-09-26 02:54:59 +08:00
|
|
|
SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
|
|
|
|
SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
|
|
|
|
SDValue(Carry,0), RHS);
|
2008-06-06 08:58:26 +08:00
|
|
|
|
2010-01-05 09:24:18 +08:00
|
|
|
return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Flag,
|
2008-07-28 05:46:04 +08:00
|
|
|
LHS, SDValue(AddCarry,0));
|
2008-06-06 08:58:26 +08:00
|
|
|
}
|
|
|
|
|
2008-06-06 14:37:31 +08:00
|
|
|
/// Mul/Div with two results
|
|
|
|
case ISD::SDIVREM:
|
|
|
|
case ISD::UDIVREM:
|
|
|
|
case ISD::SMUL_LOHI:
|
|
|
|
case ISD::UMUL_LOHI: {
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue Op1 = Node->getOperand(0);
|
|
|
|
SDValue Op2 = Node->getOperand(1);
|
2008-06-06 08:58:26 +08:00
|
|
|
|
2008-06-06 14:37:31 +08:00
|
|
|
unsigned Op;
|
|
|
|
if (Opcode == ISD::UMUL_LOHI || Opcode == ISD::SMUL_LOHI)
|
|
|
|
Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
|
|
|
|
else
|
|
|
|
Op = (Opcode == ISD::UDIVREM ? Mips::DIVu : Mips::DIV);
|
2008-06-06 08:58:26 +08:00
|
|
|
|
2010-01-20 03:57:07 +08:00
|
|
|
SDNode *MulDiv = CurDAG->getMachineNode(Op, dl, MVT::Flag, Op1, Op2);
|
2008-06-06 08:58:26 +08:00
|
|
|
|
2010-01-20 03:57:07 +08:00
|
|
|
SDValue InFlag = SDValue(MulDiv, 0);
|
2009-09-26 02:54:59 +08:00
|
|
|
SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32,
|
|
|
|
MVT::Flag, InFlag);
|
2008-07-28 05:46:04 +08:00
|
|
|
InFlag = SDValue(Lo,1);
|
2009-09-26 02:54:59 +08:00
|
|
|
SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
|
2008-06-06 14:37:31 +08:00
|
|
|
|
2010-01-05 09:24:18 +08:00
|
|
|
if (!SDValue(Node, 0).use_empty())
|
|
|
|
ReplaceUses(SDValue(Node, 0), SDValue(Lo,0));
|
2008-06-06 14:37:31 +08:00
|
|
|
|
2010-01-05 09:24:18 +08:00
|
|
|
if (!SDValue(Node, 1).use_empty())
|
|
|
|
ReplaceUses(SDValue(Node, 1), SDValue(Hi,0));
|
2008-06-06 14:37:31 +08:00
|
|
|
|
|
|
|
return NULL;
|
2008-06-06 08:58:26 +08:00
|
|
|
}
|
|
|
|
|
2008-06-06 14:37:31 +08:00
|
|
|
/// Special Muls
|
|
|
|
case ISD::MUL:
|
2007-06-06 15:42:06 +08:00
|
|
|
case ISD::MULHS:
|
|
|
|
case ISD::MULHU: {
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue MulOp1 = Node->getOperand(0);
|
|
|
|
SDValue MulOp2 = Node->getOperand(1);
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
|
2009-09-26 02:54:59 +08:00
|
|
|
SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl,
|
|
|
|
MVT::Flag, MulOp1, MulOp2);
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue InFlag = SDValue(MulNode, 0);
|
2008-06-06 14:37:31 +08:00
|
|
|
|
2010-02-01 20:16:39 +08:00
|
|
|
if (Opcode == ISD::MUL)
|
2009-09-26 02:54:59 +08:00
|
|
|
return CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32, InFlag);
|
2008-06-06 14:37:31 +08:00
|
|
|
else
|
2009-09-26 02:54:59 +08:00
|
|
|
return CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
|
|
|
|
2008-06-06 14:37:31 +08:00
|
|
|
/// Div/Rem operations
|
|
|
|
case ISD::SREM:
|
|
|
|
case ISD::UREM:
|
2007-06-06 15:42:06 +08:00
|
|
|
case ISD::SDIV:
|
|
|
|
case ISD::UDIV: {
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue Op1 = Node->getOperand(0);
|
|
|
|
SDValue Op2 = Node->getOperand(1);
|
2008-06-06 14:37:31 +08:00
|
|
|
|
|
|
|
unsigned Op, MOp;
|
|
|
|
if (Opcode == ISD::SDIV || Opcode == ISD::UDIV) {
|
|
|
|
Op = (Opcode == ISD::SDIV ? Mips::DIV : Mips::DIVu);
|
|
|
|
MOp = Mips::MFLO;
|
|
|
|
} else {
|
|
|
|
Op = (Opcode == ISD::SREM ? Mips::DIV : Mips::DIVu);
|
|
|
|
MOp = Mips::MFHI;
|
|
|
|
}
|
2009-09-26 02:54:59 +08:00
|
|
|
SDNode *Node = CurDAG->getMachineNode(Op, dl, MVT::Flag, Op1, Op2);
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue InFlag = SDValue(Node, 0);
|
2009-09-26 02:54:59 +08:00
|
|
|
return CurDAG->getMachineNode(MOp, dl, MVT::i32, InFlag);
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
2007-11-05 11:02:32 +08:00
|
|
|
|
2007-11-13 03:49:57 +08:00
|
|
|
// Get target GOT address.
|
2009-06-04 04:30:14 +08:00
|
|
|
case ISD::GLOBAL_OFFSET_TABLE:
|
|
|
|
return getGlobalBaseReg();
|
2007-11-13 03:49:57 +08:00
|
|
|
|
2009-11-14 02:49:59 +08:00
|
|
|
case ISD::ConstantFP: {
|
2010-01-05 09:24:18 +08:00
|
|
|
ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
|
|
|
|
if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
|
2010-01-19 20:53:04 +08:00
|
|
|
SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
|
|
|
|
Mips::ZERO, MVT::i32);
|
|
|
|
SDValue Undef = SDValue(
|
2010-02-10 03:54:29 +08:00
|
|
|
CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::f64), 0);
|
2010-01-19 20:53:04 +08:00
|
|
|
SDNode *MTC = CurDAG->getMachineNode(Mips::MTC1, dl, MVT::f32, Zero);
|
|
|
|
SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::SUBREG_FPEVEN, dl,
|
|
|
|
MVT::f64, Undef, SDValue(MTC, 0));
|
|
|
|
SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::SUBREG_FPODD, dl,
|
|
|
|
MVT::f64, I0, SDValue(MTC, 0));
|
|
|
|
ReplaceUses(SDValue(Node, 0), I1);
|
|
|
|
return I1.getNode();
|
2009-11-14 02:49:59 +08:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2009-11-19 14:06:13 +08:00
|
|
|
case ISD::LOAD:
|
2010-01-05 09:24:18 +08:00
|
|
|
if (SDNode *ResNode = SelectLoadFp64(Node))
|
2009-11-19 14:06:13 +08:00
|
|
|
return ResNode;
|
|
|
|
// Other cases are autogenerated.
|
|
|
|
break;
|
|
|
|
|
|
|
|
case ISD::STORE:
|
2010-01-05 09:24:18 +08:00
|
|
|
if (SDNode *ResNode = SelectStoreFp64(Node))
|
2009-11-19 14:06:13 +08:00
|
|
|
return ResNode;
|
|
|
|
// Other cases are autogenerated.
|
|
|
|
break;
|
|
|
|
|
2007-11-05 11:02:32 +08:00
|
|
|
/// Handle direct and indirect calls when using PIC. On PIC, when
|
|
|
|
/// GOT is smaller than about 64k (small code) the GA target is
|
|
|
|
/// loaded with only one instruction. Otherwise GA's target must
|
|
|
|
/// be loaded with 3 instructions.
|
|
|
|
case MipsISD::JmpLink: {
|
|
|
|
if (TM.getRelocationModel() == Reloc::PIC_) {
|
2010-01-20 01:00:43 +08:00
|
|
|
unsigned LastOpNum = Node->getNumOperands()-1;
|
|
|
|
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue Chain = Node->getOperand(0);
|
|
|
|
SDValue Callee = Node->getOperand(1);
|
2010-01-20 01:00:43 +08:00
|
|
|
SDValue InFlag;
|
|
|
|
|
|
|
|
// Skip the incomming flag if present
|
|
|
|
if (Node->getOperand(LastOpNum).getValueType() == MVT::Flag)
|
|
|
|
LastOpNum--;
|
2007-11-05 11:02:32 +08:00
|
|
|
|
|
|
|
if ( (isa<GlobalAddressSDNode>(Callee)) ||
|
2008-09-17 05:48:12 +08:00
|
|
|
(isa<ExternalSymbolSDNode>(Callee)) )
|
2007-11-05 11:02:32 +08:00
|
|
|
{
|
|
|
|
/// Direct call for global addresses and external symbols
|
2009-08-12 04:47:22 +08:00
|
|
|
SDValue GPReg = CurDAG->getRegister(Mips::GP, MVT::i32);
|
2007-11-05 11:02:32 +08:00
|
|
|
|
|
|
|
// Use load to get GOT target
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue Ops[] = { Callee, GPReg, Chain };
|
2009-09-26 02:54:59 +08:00
|
|
|
SDValue Load = SDValue(CurDAG->getMachineNode(Mips::LW, dl, MVT::i32,
|
2009-08-12 04:47:22 +08:00
|
|
|
MVT::Other, Ops, 3), 0);
|
2007-11-05 11:02:32 +08:00
|
|
|
Chain = Load.getValue(1);
|
|
|
|
|
|
|
|
// Call target must be on T9
|
2010-01-20 01:00:43 +08:00
|
|
|
Chain = CurDAG->getCopyToReg(Chain, dl, Mips::T9, Load, InFlag);
|
2007-11-05 11:02:32 +08:00
|
|
|
} else
|
|
|
|
/// Indirect call
|
2010-01-20 01:00:43 +08:00
|
|
|
Chain = CurDAG->getCopyToReg(Chain, dl, Mips::T9, Callee, InFlag);
|
|
|
|
|
|
|
|
// Map the JmpLink operands to JALR
|
|
|
|
SDVTList NodeTys = CurDAG->getVTList(MVT::Other, MVT::Flag);
|
|
|
|
SmallVector<SDValue, 8> Ops;
|
|
|
|
Ops.push_back(CurDAG->getRegister(Mips::T9, MVT::i32));
|
|
|
|
|
|
|
|
for (unsigned i = 2, e = LastOpNum+1; i != e; ++i)
|
|
|
|
Ops.push_back(Node->getOperand(i));
|
|
|
|
Ops.push_back(Chain);
|
|
|
|
Ops.push_back(Chain.getValue(1));
|
2007-11-05 11:02:32 +08:00
|
|
|
|
|
|
|
// Emit Jump and Link Register
|
2010-01-20 01:00:43 +08:00
|
|
|
SDNode *ResNode = CurDAG->getMachineNode(Mips::JALR, dl, NodeTys,
|
|
|
|
&Ops[0], Ops.size());
|
|
|
|
|
|
|
|
// Replace Chain and InFlag
|
|
|
|
ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
|
|
|
|
ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 1));
|
2007-11-05 11:02:32 +08:00
|
|
|
return ResNode;
|
|
|
|
}
|
|
|
|
}
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Select the default instruction
|
2010-01-05 09:24:18 +08:00
|
|
|
SDNode *ResNode = SelectCode(Node);
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2009-08-23 14:49:22 +08:00
|
|
|
DEBUG(errs().indent(Indent-2) << "=> ");
|
2010-01-05 09:24:18 +08:00
|
|
|
if (ResNode == NULL || ResNode == Node)
|
|
|
|
DEBUG(Node->dump(CurDAG));
|
2007-06-06 15:42:06 +08:00
|
|
|
else
|
|
|
|
DEBUG(ResNode->dump(CurDAG));
|
2009-08-23 14:49:22 +08:00
|
|
|
DEBUG(errs() << "\n");
|
2009-08-23 16:50:52 +08:00
|
|
|
DEBUG(Indent -= 2);
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
return ResNode;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// createMipsISelDag - This pass converts a legalized DAG into a
|
|
|
|
/// MIPS-specific DAG, ready for instruction scheduling.
|
|
|
|
FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
|
|
|
|
return new MipsDAGToDAGISel(TM);
|
|
|
|
}
|