2012-12-12 05:25:42 +08:00
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//===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains instruction defs that are common to all hw codegen
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// targets.
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//
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//===----------------------------------------------------------------------===//
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class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
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2013-02-07 01:32:29 +08:00
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field bit isRegisterLoad = 0;
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field bit isRegisterStore = 0;
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2012-12-12 05:25:42 +08:00
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let Namespace = "AMDGPU";
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let OutOperandList = outs;
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let InOperandList = ins;
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let AsmString = asm;
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let Pattern = pattern;
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let Itinerary = NullALU;
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2013-02-07 01:32:29 +08:00
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let TSFlags{63} = isRegisterLoad;
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let TSFlags{62} = isRegisterStore;
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2012-12-12 05:25:42 +08:00
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}
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class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
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: AMDGPUInst<outs, ins, asm, pattern> {
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field bits<32> Inst = 0xffffffff;
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}
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def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
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def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
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2012-12-12 05:25:42 +08:00
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2013-11-23 07:07:58 +08:00
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//===----------------------------------------------------------------------===//
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// PatLeafs for floating-point comparisons
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//===----------------------------------------------------------------------===//
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2012-12-12 05:25:42 +08:00
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2013-09-28 10:50:50 +08:00
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def COND_OEQ : PatLeaf <
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(cond),
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[{return N->get() == ISD::SETOEQ || N->get() == ISD::SETEQ;}]
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>;
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2013-11-23 07:07:58 +08:00
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def COND_OGT : PatLeaf <
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2012-12-12 05:25:42 +08:00
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(cond),
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[{return N->get() == ISD::SETOGT || N->get() == ISD::SETGT;}]
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2012-12-12 05:25:42 +08:00
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>;
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2013-11-23 07:07:58 +08:00
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def COND_OGE : PatLeaf <
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(cond),
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[{return N->get() == ISD::SETOGE || N->get() == ISD::SETGE;}]
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>;
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2013-11-23 07:07:58 +08:00
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def COND_OLT : PatLeaf <
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(cond),
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[{return N->get() == ISD::SETOLT || N->get() == ISD::SETLT;}]
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2012-12-12 05:25:42 +08:00
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>;
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2013-11-23 07:07:58 +08:00
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def COND_OLE : PatLeaf <
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(cond),
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[{return N->get() == ISD::SETOLE || N->get() == ISD::SETLE;}]
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>;
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2013-11-23 07:07:58 +08:00
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def COND_UNE : PatLeaf <
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(cond),
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2013-11-23 07:07:58 +08:00
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[{return N->get() == ISD::SETUNE || N->get() == ISD::SETNE;}]
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2012-12-12 05:25:42 +08:00
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>;
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2013-11-23 07:07:58 +08:00
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def COND_O : PatLeaf <(cond), [{return N->get() == ISD::SETO;}]>;
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def COND_UO : PatLeaf <(cond), [{return N->get() == ISD::SETUO;}]>;
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//===----------------------------------------------------------------------===//
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// PatLeafs for unsigned comparisons
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//===----------------------------------------------------------------------===//
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def COND_UGT : PatLeaf <(cond), [{return N->get() == ISD::SETUGT;}]>;
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def COND_UGE : PatLeaf <(cond), [{return N->get() == ISD::SETUGE;}]>;
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def COND_ULT : PatLeaf <(cond), [{return N->get() == ISD::SETULT;}]>;
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def COND_ULE : PatLeaf <(cond), [{return N->get() == ISD::SETULE;}]>;
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//===----------------------------------------------------------------------===//
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// PatLeafs for signed comparisons
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//===----------------------------------------------------------------------===//
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def COND_SGT : PatLeaf <(cond), [{return N->get() == ISD::SETGT;}]>;
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def COND_SGE : PatLeaf <(cond), [{return N->get() == ISD::SETGE;}]>;
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def COND_SLT : PatLeaf <(cond), [{return N->get() == ISD::SETLT;}]>;
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def COND_SLE : PatLeaf <(cond), [{return N->get() == ISD::SETLE;}]>;
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//===----------------------------------------------------------------------===//
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// PatLeafs for integer equality
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//===----------------------------------------------------------------------===//
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def COND_EQ : PatLeaf <
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(cond),
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[{return N->get() == ISD::SETEQ || N->get() == ISD::SETUEQ;}]
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2012-12-12 05:25:42 +08:00
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>;
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2013-11-23 07:07:58 +08:00
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def COND_NE : PatLeaf <
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(cond),
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2013-11-23 07:07:58 +08:00
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[{return N->get() == ISD::SETNE || N->get() == ISD::SETUNE;}]
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2012-12-12 05:25:42 +08:00
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>;
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2013-02-21 23:17:04 +08:00
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def COND_NULL : PatLeaf <
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(cond),
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[{return false;}]
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>;
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2012-12-12 05:25:42 +08:00
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//===----------------------------------------------------------------------===//
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// Load/Store Pattern Fragments
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//===----------------------------------------------------------------------===//
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2013-07-16 03:00:09 +08:00
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def az_extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
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LoadSDNode *L = cast<LoadSDNode>(N);
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return L->getExtensionType() == ISD::ZEXTLOAD ||
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L->getExtensionType() == ISD::EXTLOAD;
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}]>;
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2013-07-23 09:47:52 +08:00
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def az_extloadi8 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
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}]>;
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2013-08-26 23:05:59 +08:00
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def az_extloadi8_global : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
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return isGlobalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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2013-07-23 09:48:35 +08:00
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def sextloadi8_global : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
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return isGlobalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def az_extloadi8_constant : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
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return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
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}]>;
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def sextloadi8_constant : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
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return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
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}]>;
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2013-08-26 23:05:59 +08:00
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def az_extloadi8_local : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
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return isLocalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def sextloadi8_local : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
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return isLocalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def az_extloadi16 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
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}]>;
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def az_extloadi16_global : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
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return isGlobalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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2013-07-23 09:48:35 +08:00
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def sextloadi16_global : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
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2013-06-04 01:39:43 +08:00
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return isGlobalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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2013-07-23 09:48:35 +08:00
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def az_extloadi16_constant : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
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return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
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}]>;
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def sextloadi16_constant : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
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return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
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}]>;
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2013-08-26 23:05:59 +08:00
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def az_extloadi16_local : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
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return isLocalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def sextloadi16_local : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
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return isLocalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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2013-07-16 03:00:09 +08:00
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def az_extloadi32 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
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}]>;
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def az_extloadi32_global : PatFrag<(ops node:$ptr),
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(az_extloadi32 node:$ptr), [{
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return isGlobalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def az_extloadi32_constant : PatFrag<(ops node:$ptr),
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(az_extloadi32 node:$ptr), [{
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return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
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}]>;
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2013-08-16 09:12:06 +08:00
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def truncstorei8_global : PatFrag<(ops node:$val, node:$ptr),
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(truncstorei8 node:$val, node:$ptr), [{
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return isGlobalStore(dyn_cast<StoreSDNode>(N));
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}]>;
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def truncstorei16_global : PatFrag<(ops node:$val, node:$ptr),
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(truncstorei16 node:$val, node:$ptr), [{
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return isGlobalStore(dyn_cast<StoreSDNode>(N));
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}]>;
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2013-06-28 23:47:08 +08:00
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def local_store : PatFrag<(ops node:$val, node:$ptr),
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(store node:$val, node:$ptr), [{
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2013-08-26 23:05:49 +08:00
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return isLocalStore(dyn_cast<StoreSDNode>(N));
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}]>;
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def truncstorei8_local : PatFrag<(ops node:$val, node:$ptr),
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(truncstorei8 node:$val, node:$ptr), [{
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return isLocalStore(dyn_cast<StoreSDNode>(N));
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}]>;
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def truncstorei16_local : PatFrag<(ops node:$val, node:$ptr),
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(truncstorei16 node:$val, node:$ptr), [{
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return isLocalStore(dyn_cast<StoreSDNode>(N));
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}]>;
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def local_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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return isLocalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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2013-09-06 02:38:09 +08:00
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def atomic_load_add_local : PatFrag<(ops node:$ptr, node:$value),
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(atomic_load_add node:$ptr, node:$value), [{
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return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
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}]>;
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2013-09-07 04:17:42 +08:00
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def atomic_load_sub_local : PatFrag<(ops node:$ptr, node:$value),
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(atomic_load_sub node:$ptr, node:$value), [{
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return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
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}]>;
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2013-08-16 09:12:06 +08:00
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def mskor_global : PatFrag<(ops node:$val, node:$ptr),
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(AMDGPUstore_mskor node:$val, node:$ptr), [{
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return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
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}]>;
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2012-12-12 05:25:42 +08:00
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class Constants {
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int TWO_PI = 0x40c90fdb;
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int PI = 0x40490fdb;
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int TWO_PI_INV = 0x3e22f983;
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int FP_UINT_MAX_PLUS_1 = 0x4f800000; // 1 << 32 in floating point encoding
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}
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def CONST : Constants;
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def FP_ZERO : PatLeaf <
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(fpimm),
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[{return N->getValueAPF().isZero();}]
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>;
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def FP_ONE : PatLeaf <
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(fpimm),
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[{return N->isExactlyValue(1.0);}]
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>;
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2013-07-23 09:48:42 +08:00
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def U24 : ComplexPattern<i32, 1, "SelectU24", [], []>;
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def I24 : ComplexPattern<i32, 1, "SelectI24", [], []>;
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2013-02-07 01:32:29 +08:00
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let isCodeGenOnly = 1, isPseudo = 1 in {
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let usesCustomInserter = 1 in {
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2012-12-12 05:25:42 +08:00
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class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
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(outs rc:$dst),
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(ins rc:$src0),
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"CLAMP $dst, $src0",
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2013-05-02 23:30:12 +08:00
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[(set f32:$dst, (int_AMDIL_clamp f32:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
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2012-12-12 05:25:42 +08:00
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>;
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class FABS <RegisterClass rc> : AMDGPUShaderInst <
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(outs rc:$dst),
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(ins rc:$src0),
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"FABS $dst, $src0",
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2013-05-02 23:30:12 +08:00
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[(set f32:$dst, (fabs f32:$src0))]
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2012-12-12 05:25:42 +08:00
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>;
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class FNEG <RegisterClass rc> : AMDGPUShaderInst <
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(outs rc:$dst),
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(ins rc:$src0),
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"FNEG $dst, $src0",
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2013-05-02 23:30:12 +08:00
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[(set f32:$dst, (fneg f32:$src0))]
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2012-12-12 05:25:42 +08:00
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>;
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2013-02-07 01:32:29 +08:00
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} // usesCustomInserter = 1
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multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass,
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ComplexPattern addrPat> {
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2013-11-14 07:36:50 +08:00
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let UseNamedOperandTable = 1 in {
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2013-02-07 01:32:29 +08:00
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def RegisterLoad : AMDGPUShaderInst <
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(outs dstClass:$dst),
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(ins addrClass:$addr, i32imm:$chan),
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"RegisterLoad $dst, $addr",
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2013-05-02 23:30:12 +08:00
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[(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))]
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2013-02-07 01:32:29 +08:00
|
|
|
> {
|
|
|
|
let isRegisterLoad = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
def RegisterStore : AMDGPUShaderInst <
|
|
|
|
(outs),
|
|
|
|
(ins dstClass:$val, addrClass:$addr, i32imm:$chan),
|
|
|
|
"RegisterStore $val, $addr",
|
2013-05-02 23:30:12 +08:00
|
|
|
[(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))]
|
2013-02-07 01:32:29 +08:00
|
|
|
> {
|
|
|
|
let isRegisterStore = 1;
|
|
|
|
}
|
|
|
|
}
|
2013-11-14 07:36:50 +08:00
|
|
|
}
|
2013-02-07 01:32:29 +08:00
|
|
|
|
|
|
|
} // End isCodeGenOnly = 1, isPseudo = 1
|
2012-12-12 05:25:42 +08:00
|
|
|
|
|
|
|
/* Generic helper patterns for intrinsics */
|
|
|
|
/* -------------------------------------- */
|
|
|
|
|
2013-05-02 23:30:12 +08:00
|
|
|
class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul>
|
|
|
|
: Pat <
|
|
|
|
(fpow f32:$src0, f32:$src1),
|
|
|
|
(exp_ieee (mul f32:$src1, (log_ieee f32:$src0)))
|
2012-12-12 05:25:42 +08:00
|
|
|
>;
|
|
|
|
|
|
|
|
/* Other helper patterns */
|
|
|
|
/* --------------------- */
|
|
|
|
|
|
|
|
/* Extract element pattern */
|
2014-02-27 07:00:58 +08:00
|
|
|
class Extract_Element <ValueType sub_type, ValueType vec_type, int sub_idx,
|
2013-05-02 23:30:12 +08:00
|
|
|
SubRegIndex sub_reg>
|
|
|
|
: Pat<
|
|
|
|
(sub_type (vector_extract vec_type:$src, sub_idx)),
|
|
|
|
(EXTRACT_SUBREG $src, sub_reg)
|
2012-12-12 05:25:42 +08:00
|
|
|
>;
|
|
|
|
|
|
|
|
/* Insert element pattern */
|
|
|
|
class Insert_Element <ValueType elem_type, ValueType vec_type,
|
2013-05-02 23:30:12 +08:00
|
|
|
int sub_idx, SubRegIndex sub_reg>
|
|
|
|
: Pat <
|
|
|
|
(vector_insert vec_type:$vec, elem_type:$elem, sub_idx),
|
|
|
|
(INSERT_SUBREG $vec, $elem, sub_reg)
|
2012-12-12 05:25:42 +08:00
|
|
|
>;
|
|
|
|
|
2013-05-02 23:30:12 +08:00
|
|
|
// XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
|
|
|
|
// can handle COPY instructions.
|
2012-12-12 05:25:42 +08:00
|
|
|
// bitconvert pattern
|
|
|
|
class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
|
|
|
|
(dt (bitconvert (st rc:$src0))),
|
|
|
|
(dt rc:$src0)
|
|
|
|
>;
|
|
|
|
|
2013-05-02 23:30:12 +08:00
|
|
|
// XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
|
|
|
|
// can handle COPY instructions.
|
2012-12-12 05:25:42 +08:00
|
|
|
class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <
|
|
|
|
(vt (AMDGPUdwordaddr (vt rc:$addr))),
|
|
|
|
(vt rc:$addr)
|
|
|
|
>;
|
|
|
|
|
2013-04-19 10:11:06 +08:00
|
|
|
// BFI_INT patterns
|
|
|
|
|
|
|
|
multiclass BFIPatterns <Instruction BFI_INT> {
|
|
|
|
|
|
|
|
// Definition from ISA doc:
|
|
|
|
// (y & x) | (z & ~x)
|
|
|
|
def : Pat <
|
|
|
|
(or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))),
|
|
|
|
(BFI_INT $x, $y, $z)
|
|
|
|
>;
|
|
|
|
|
|
|
|
// SHA-256 Ch function
|
|
|
|
// z ^ (x & (y ^ z))
|
|
|
|
def : Pat <
|
|
|
|
(xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))),
|
|
|
|
(BFI_INT $x, $y, $z)
|
|
|
|
>;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2013-05-04 01:21:20 +08:00
|
|
|
// SHA-256 Ma patterns
|
|
|
|
|
|
|
|
// ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y
|
|
|
|
class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat <
|
|
|
|
(or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))),
|
|
|
|
(BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y)
|
|
|
|
>;
|
|
|
|
|
2013-05-10 10:09:45 +08:00
|
|
|
// Bitfield extract patterns
|
|
|
|
|
2014-01-24 02:49:33 +08:00
|
|
|
/*
|
|
|
|
|
|
|
|
XXX: The BFE pattern is not working correctly because the XForm is not being
|
|
|
|
applied.
|
|
|
|
|
2013-05-10 10:09:45 +08:00
|
|
|
def legalshift32 : ImmLeaf <i32, [{return Imm >=0 && Imm < 32;}]>;
|
|
|
|
def bfemask : PatLeaf <(imm), [{return isMask_32(N->getZExtValue());}],
|
|
|
|
SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(CountTrailingOnes_32(N->getZExtValue()), MVT::i32);}]>>;
|
|
|
|
|
|
|
|
class BFEPattern <Instruction BFE> : Pat <
|
|
|
|
(and (srl i32:$x, legalshift32:$y), bfemask:$z),
|
|
|
|
(BFE $x, $y, $z)
|
|
|
|
>;
|
|
|
|
|
2014-01-24 02:49:33 +08:00
|
|
|
*/
|
|
|
|
|
2013-05-20 23:02:19 +08:00
|
|
|
// rotr pattern
|
|
|
|
class ROTRPattern <Instruction BIT_ALIGN> : Pat <
|
|
|
|
(rotr i32:$src0, i32:$src1),
|
|
|
|
(BIT_ALIGN $src0, $src0, $src1)
|
|
|
|
>;
|
|
|
|
|
2013-07-23 09:48:42 +08:00
|
|
|
// 24-bit arithmetic patterns
|
|
|
|
def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>;
|
|
|
|
|
|
|
|
/*
|
|
|
|
class UMUL24Pattern <Instruction UMUL24> : Pat <
|
|
|
|
(mul U24:$x, U24:$y),
|
|
|
|
(UMUL24 $x, $y)
|
|
|
|
>;
|
|
|
|
*/
|
|
|
|
|
2012-12-12 05:25:42 +08:00
|
|
|
include "R600Instructions.td"
|
|
|
|
|
|
|
|
include "SIInstrInfo.td"
|
|
|
|
|