2013-01-09 02:27:24 +08:00
|
|
|
; RUN: llc < %s -mattr=-avx -fast-isel -mcpu=core2 -O0 -regalloc=fast -asm-verbose=0 -fast-isel-abort | FileCheck %s
|
|
|
|
; RUN: llc < %s -mattr=+avx -fast-isel -mcpu=core2 -O0 -regalloc=fast -asm-verbose=0 -fast-isel-abort | FileCheck %s --check-prefix=AVX
|
2011-04-17 09:16:47 +08:00
|
|
|
|
|
|
|
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
|
|
|
|
target triple = "x86_64-apple-darwin10.0.0"
|
|
|
|
|
|
|
|
; Make sure that fast-isel folds the immediate into the binop even though it
|
|
|
|
; is non-canonical.
|
|
|
|
define i32 @test1(i32 %i) nounwind ssp {
|
|
|
|
%and = and i32 8, %i
|
|
|
|
ret i32 %and
|
|
|
|
}
|
|
|
|
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: test1:
|
2011-04-17 09:16:47 +08:00
|
|
|
; CHECK: andl $8,
|
2011-04-17 14:35:44 +08:00
|
|
|
|
|
|
|
|
2011-04-23 05:59:37 +08:00
|
|
|
; rdar://9289512 - The load should fold into the compare.
|
|
|
|
define void @test2(i64 %x) nounwind ssp {
|
|
|
|
entry:
|
|
|
|
%x.addr = alloca i64, align 8
|
|
|
|
store i64 %x, i64* %x.addr, align 8
|
|
|
|
%tmp = load i64* %x.addr, align 8
|
|
|
|
%cmp = icmp sgt i64 %tmp, 42
|
|
|
|
br i1 %cmp, label %if.then, label %if.end
|
|
|
|
|
|
|
|
if.then: ; preds = %entry
|
|
|
|
br label %if.end
|
|
|
|
|
|
|
|
if.end: ; preds = %if.then, %entry
|
|
|
|
ret void
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: test2:
|
2011-04-23 05:59:37 +08:00
|
|
|
; CHECK: movq %rdi, -8(%rsp)
|
|
|
|
; CHECK: cmpq $42, -8(%rsp)
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2011-04-18 01:12:08 +08:00
|
|
|
@G = external global i32
|
|
|
|
define i64 @test3() nounwind {
|
|
|
|
%A = ptrtoint i32* @G to i64
|
|
|
|
ret i64 %A
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: test3:
|
2011-04-18 01:12:08 +08:00
|
|
|
; CHECK: movq _G@GOTPCREL(%rip), %rax
|
|
|
|
; CHECK-NEXT: ret
|
2011-04-18 01:47:38 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
; rdar://9289558
|
|
|
|
@rtx_length = external global [153 x i8]
|
|
|
|
|
|
|
|
define i32 @test4(i64 %idxprom9) nounwind {
|
|
|
|
%arrayidx10 = getelementptr inbounds [153 x i8]* @rtx_length, i32 0, i64 %idxprom9
|
|
|
|
%tmp11 = load i8* %arrayidx10, align 1
|
|
|
|
%conv = zext i8 %tmp11 to i32
|
|
|
|
ret i32 %conv
|
|
|
|
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: test4:
|
2011-04-18 01:47:38 +08:00
|
|
|
; CHECK: movq _rtx_length@GOTPCREL(%rip), %rax
|
|
|
|
; CHECK-NEXT: movzbl (%rax,%rdi), %eax
|
|
|
|
; CHECK-NEXT: ret
|
|
|
|
}
|
2011-04-18 04:23:29 +08:00
|
|
|
|
|
|
|
|
|
|
|
; PR3242 - Out of range shifts should not be folded by fastisel.
|
|
|
|
define void @test5(i32 %x, i32* %p) nounwind {
|
|
|
|
%y = ashr i32 %x, 50000
|
|
|
|
store i32 %y, i32* %p
|
|
|
|
ret void
|
|
|
|
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: test5:
|
2011-04-18 04:23:29 +08:00
|
|
|
; CHECK: movl $50000, %ecx
|
|
|
|
; CHECK: sarl %cl, %edi
|
|
|
|
; CHECK: ret
|
|
|
|
}
|
|
|
|
|
|
|
|
; rdar://9289501 - fast isel should fold trivial multiplies to shifts.
|
|
|
|
define i64 @test6(i64 %x) nounwind ssp {
|
|
|
|
entry:
|
|
|
|
%mul = mul nsw i64 %x, 8
|
|
|
|
ret i64 %mul
|
|
|
|
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: test6:
|
2011-11-17 02:44:48 +08:00
|
|
|
; CHECK: shlq $3, %rdi
|
2011-04-18 04:23:29 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @test7(i32 %x) nounwind ssp {
|
|
|
|
entry:
|
|
|
|
%mul = mul nsw i32 %x, 8
|
|
|
|
ret i32 %mul
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: test7:
|
2011-11-17 02:44:48 +08:00
|
|
|
; CHECK: shll $3, %edi
|
2011-04-18 04:23:29 +08:00
|
|
|
}
|
|
|
|
|
2011-04-18 14:22:33 +08:00
|
|
|
|
|
|
|
; rdar://9289507 - folding of immediates into 64-bit operations.
|
|
|
|
define i64 @test8(i64 %x) nounwind ssp {
|
|
|
|
entry:
|
|
|
|
%add = add nsw i64 %x, 7
|
|
|
|
ret i64 %add
|
|
|
|
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: test8:
|
2011-04-18 14:22:33 +08:00
|
|
|
; CHECK: addq $7, %rdi
|
|
|
|
}
|
|
|
|
|
|
|
|
define i64 @test9(i64 %x) nounwind ssp {
|
|
|
|
entry:
|
|
|
|
%add = mul nsw i64 %x, 7
|
|
|
|
ret i64 %add
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: test9:
|
2011-04-18 14:22:33 +08:00
|
|
|
; CHECK: imulq $7, %rdi, %rax
|
|
|
|
}
|
2011-04-18 14:55:51 +08:00
|
|
|
|
|
|
|
; rdar://9297011 - Don't reject udiv by a power of 2.
|
|
|
|
define i32 @test10(i32 %X) nounwind {
|
|
|
|
%Y = udiv i32 %X, 8
|
|
|
|
ret i32 %Y
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: test10:
|
2011-04-18 14:55:51 +08:00
|
|
|
; CHECK: shrl $3,
|
|
|
|
}
|
2011-04-18 15:00:40 +08:00
|
|
|
|
|
|
|
define i32 @test11(i32 %X) nounwind {
|
|
|
|
%Y = sdiv exact i32 %X, 8
|
|
|
|
ret i32 %Y
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: test11:
|
2011-04-18 15:00:40 +08:00
|
|
|
; CHECK: sarl $3,
|
|
|
|
}
|
|
|
|
|
2011-04-19 12:22:17 +08:00
|
|
|
|
|
|
|
; rdar://9297006 - Trunc to bool.
|
|
|
|
define void @test12(i8 %tmp) nounwind ssp noredzone {
|
|
|
|
entry:
|
|
|
|
%tobool = trunc i8 %tmp to i1
|
|
|
|
br i1 %tobool, label %if.then, label %if.end
|
|
|
|
|
|
|
|
if.then: ; preds = %entry
|
|
|
|
call void @test12(i8 0) noredzone
|
|
|
|
br label %if.end
|
|
|
|
|
|
|
|
if.end: ; preds = %if.then, %entry
|
|
|
|
ret void
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: test12:
|
2011-04-19 12:22:17 +08:00
|
|
|
; CHECK: testb $1,
|
2011-04-19 12:26:32 +08:00
|
|
|
; CHECK-NEXT: je L
|
2014-08-15 03:56:28 +08:00
|
|
|
; CHECK-NEXT: movl $0, %edi
|
2011-04-19 12:42:38 +08:00
|
|
|
; CHECK-NEXT: callq
|
|
|
|
}
|
|
|
|
|
|
|
|
declare void @test13f(i1 %X)
|
|
|
|
|
|
|
|
define void @test13() nounwind {
|
|
|
|
call void @test13f(i1 0)
|
|
|
|
ret void
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: test13:
|
2014-08-15 03:56:28 +08:00
|
|
|
; CHECK: movl $0, %edi
|
2011-04-19 12:42:38 +08:00
|
|
|
; CHECK-NEXT: callq
|
2011-04-19 12:22:17 +08:00
|
|
|
}
|
|
|
|
|
2011-04-19 13:09:50 +08:00
|
|
|
|
|
|
|
|
|
|
|
; rdar://9297003 - fast isel bails out on all functions taking bools
|
|
|
|
define void @test14(i8 %tmp) nounwind ssp noredzone {
|
|
|
|
entry:
|
|
|
|
%tobool = trunc i8 %tmp to i1
|
|
|
|
call void @test13f(i1 zeroext %tobool) noredzone
|
|
|
|
ret void
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: test14:
|
2011-04-19 13:09:50 +08:00
|
|
|
; CHECK: andb $1,
|
|
|
|
; CHECK: callq
|
|
|
|
}
|
|
|
|
|
2011-04-19 13:52:03 +08:00
|
|
|
declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i32, i1)
|
|
|
|
|
|
|
|
; rdar://9289488 - fast-isel shouldn't bail out on llvm.memcpy
|
|
|
|
define void @test15(i8* %a, i8* %b) nounwind {
|
|
|
|
call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* %b, i64 4, i32 4, i1 false)
|
|
|
|
ret void
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: test15:
|
2011-04-19 13:52:03 +08:00
|
|
|
; CHECK-NEXT: movl (%rsi), %eax
|
|
|
|
; CHECK-NEXT: movl %eax, (%rdi)
|
|
|
|
; CHECK-NEXT: ret
|
|
|
|
}
|
2011-04-20 01:22:22 +08:00
|
|
|
|
|
|
|
; Handling for varargs calls
|
|
|
|
declare void @test16callee(...) nounwind
|
|
|
|
define void @test16() nounwind {
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: test16:
|
2011-04-20 01:22:22 +08:00
|
|
|
; CHECK: movl $1, %edi
|
|
|
|
; CHECK: movb $0, %al
|
|
|
|
; CHECK: callq _test16callee
|
|
|
|
call void (...)* @test16callee(i32 1)
|
|
|
|
br label %block2
|
|
|
|
|
|
|
|
block2:
|
2014-08-15 03:56:28 +08:00
|
|
|
; CHECK: movabsq $1
|
|
|
|
; CHECK: cvtsi2sdq {{.*}} %xmm0
|
2011-04-20 01:22:22 +08:00
|
|
|
; CHECK: movb $1, %al
|
|
|
|
; CHECK: callq _test16callee
|
Introduce 'UseSSEx' to force SSE legacy encoding
- Add 'UseSSEx' to force SSE legacy insn not being selected when AVX is
enabled.
As the penalty of inter-mixing SSE and AVX instructions, we need
prevent SSE legacy insn from being generated except explicitly
specified through some intrinsics. For patterns supported by both
SSE and AVX, so far, we force AVX insn will be tried first relying on
AddedComplexity or position in td file. It's error-prone and
introduces bugs accidentally.
'UseSSEx' is disabled when AVX is turned on. For SSE insns inherited
by AVX, we need this predicate to force VEX encoding or SSE legacy
encoding only.
For insns not inherited by AVX, we still use the previous predicates,
i.e. 'HasSSEx'. So far, these insns fall into the following
categories:
* SSE insns with MMX operands
* SSE insns with GPR/MEM operands only (xFENCE, PREFETCH, CLFLUSH,
CRC, and etc.)
* SSE4A insns.
* MMX insns.
* x87 insns added by SSE.
2 test cases are modified:
- test/CodeGen/X86/fast-isel-x86-64.ll
AVX code generation is different from SSE one. 'vcvtsi2sdq' cannot be
selected by fast-isel due to complicated pattern and fast-isel
fallback to materialize it from constant pool.
- test/CodeGen/X86/widen_load-1.ll
AVX code generation is different from SSE one after fixing SSE/AVX
inter-mixing. Exec-domain fixing prefers 'vmovapd' instead of
'vmovaps'.
llvm-svn: 162919
2012-08-31 00:54:46 +08:00
|
|
|
|
2014-08-15 03:56:28 +08:00
|
|
|
; AVX: movabsq $1
|
Introduce 'UseSSEx' to force SSE legacy encoding
- Add 'UseSSEx' to force SSE legacy insn not being selected when AVX is
enabled.
As the penalty of inter-mixing SSE and AVX instructions, we need
prevent SSE legacy insn from being generated except explicitly
specified through some intrinsics. For patterns supported by both
SSE and AVX, so far, we force AVX insn will be tried first relying on
AddedComplexity or position in td file. It's error-prone and
introduces bugs accidentally.
'UseSSEx' is disabled when AVX is turned on. For SSE insns inherited
by AVX, we need this predicate to force VEX encoding or SSE legacy
encoding only.
For insns not inherited by AVX, we still use the previous predicates,
i.e. 'HasSSEx'. So far, these insns fall into the following
categories:
* SSE insns with MMX operands
* SSE insns with GPR/MEM operands only (xFENCE, PREFETCH, CLFLUSH,
CRC, and etc.)
* SSE4A insns.
* MMX insns.
* x87 insns added by SSE.
2 test cases are modified:
- test/CodeGen/X86/fast-isel-x86-64.ll
AVX code generation is different from SSE one. 'vcvtsi2sdq' cannot be
selected by fast-isel due to complicated pattern and fast-isel
fallback to materialize it from constant pool.
- test/CodeGen/X86/widen_load-1.ll
AVX code generation is different from SSE one after fixing SSE/AVX
inter-mixing. Exec-domain fixing prefers 'vmovapd' instead of
'vmovaps'.
llvm-svn: 162919
2012-08-31 00:54:46 +08:00
|
|
|
; AVX: vmovsd LCP{{.*}}_{{.*}}(%rip), %xmm0
|
|
|
|
; AVX: movb $1, %al
|
|
|
|
; AVX: callq _test16callee
|
2011-04-20 01:22:22 +08:00
|
|
|
call void (...)* @test16callee(double 1.000000e+00)
|
|
|
|
ret void
|
|
|
|
}
|
2011-04-23 05:59:37 +08:00
|
|
|
|
|
|
|
|
|
|
|
declare void @foo() unnamed_addr ssp align 2
|
|
|
|
|
|
|
|
; Verify that we don't fold the load into the compare here. That would move it
|
|
|
|
; w.r.t. the call.
|
|
|
|
define i32 @test17(i32 *%P) ssp nounwind {
|
|
|
|
entry:
|
|
|
|
%tmp = load i32* %P
|
|
|
|
%cmp = icmp ne i32 %tmp, 5
|
|
|
|
call void @foo()
|
|
|
|
br i1 %cmp, label %if.then, label %if.else
|
|
|
|
|
|
|
|
if.then: ; preds = %entry
|
|
|
|
ret i32 1
|
|
|
|
|
|
|
|
if.else: ; preds = %entry
|
|
|
|
ret i32 2
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: test17:
|
2011-04-23 05:59:37 +08:00
|
|
|
; CHECK: movl (%rdi), %eax
|
|
|
|
; CHECK: callq _foo
|
|
|
|
; CHECK: cmpl $5, %eax
|
|
|
|
; CHECK-NEXT: je
|
|
|
|
}
|
|
|
|
|
2011-11-30 06:27:25 +08:00
|
|
|
; Check that 0.0 is materialized using xorps
|
2011-04-28 06:41:55 +08:00
|
|
|
define void @test18(float* %p1) {
|
|
|
|
store float 0.0, float* %p1
|
|
|
|
ret void
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: test18:
|
2011-11-30 06:27:25 +08:00
|
|
|
; CHECK: xorps
|
2011-04-28 06:41:55 +08:00
|
|
|
}
|
2011-11-30 06:27:25 +08:00
|
|
|
|
|
|
|
; Without any type hints, doubles use the smaller xorps instead of xorpd.
|
2011-04-28 06:41:55 +08:00
|
|
|
define void @test19(double* %p1) {
|
|
|
|
store double 0.0, double* %p1
|
|
|
|
ret void
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: test19:
|
2011-11-30 06:27:25 +08:00
|
|
|
; CHECK: xorps
|
2011-04-28 06:41:55 +08:00
|
|
|
}
|
2011-04-28 07:58:52 +08:00
|
|
|
|
2011-04-29 04:19:12 +08:00
|
|
|
; Check that we fast-isel sret
|
|
|
|
%struct.a = type { i64, i64, i64 }
|
|
|
|
define void @test20() nounwind ssp {
|
|
|
|
entry:
|
|
|
|
%tmp = alloca %struct.a, align 8
|
|
|
|
call void @test20sret(%struct.a* sret %tmp)
|
|
|
|
ret void
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: test20:
|
2011-04-29 04:19:12 +08:00
|
|
|
; CHECK: leaq (%rsp), %rdi
|
|
|
|
; CHECK: callq _test20sret
|
|
|
|
}
|
|
|
|
declare void @test20sret(%struct.a* sret)
|
|
|
|
|
2011-11-30 06:27:25 +08:00
|
|
|
; Check that -0.0 is not materialized using xor
|
2011-04-28 08:42:03 +08:00
|
|
|
define void @test21(double* %p1) {
|
|
|
|
store double -0.0, double* %p1
|
|
|
|
ret void
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: test21:
|
2011-11-30 06:27:25 +08:00
|
|
|
; CHECK-NOT: xor
|
2011-04-28 08:42:03 +08:00
|
|
|
; CHECK: movsd LCPI
|
2011-08-19 06:06:10 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
; Check that immediate arguments to a function
|
|
|
|
; do not cause massive spilling and are used
|
|
|
|
; as immediates just before the call.
|
|
|
|
define void @test22() nounwind {
|
|
|
|
entry:
|
|
|
|
call void @foo22(i32 0)
|
|
|
|
call void @foo22(i32 1)
|
|
|
|
call void @foo22(i32 2)
|
|
|
|
call void @foo22(i32 3)
|
|
|
|
ret void
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: test22:
|
2014-08-15 03:56:28 +08:00
|
|
|
; CHECK: movl $0, %edi
|
2011-08-19 06:06:10 +08:00
|
|
|
; CHECK: callq _foo22
|
|
|
|
; CHECK: movl $1, %edi
|
|
|
|
; CHECK: callq _foo22
|
|
|
|
; CHECK: movl $2, %edi
|
|
|
|
; CHECK: callq _foo22
|
|
|
|
; CHECK: movl $3, %edi
|
|
|
|
; CHECK: callq _foo22
|
|
|
|
}
|
|
|
|
|
|
|
|
declare void @foo22(i32)
|
2012-10-03 06:45:06 +08:00
|
|
|
|
|
|
|
; PR13563
|
|
|
|
define void @test23(i8* noalias sret %result) {
|
|
|
|
%a = alloca i8
|
|
|
|
%b = call i8* @foo23()
|
|
|
|
ret void
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: test23:
|
2012-10-03 06:45:06 +08:00
|
|
|
; CHECK: call
|
|
|
|
; CHECK: movq %rdi, %rax
|
|
|
|
; CHECK: ret
|
|
|
|
}
|
|
|
|
|
|
|
|
declare i8* @foo23()
|