2017-06-17 01:32:43 +08:00
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//===- AArch64.cpp --------------------------------------------------------===//
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//
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// The LLVM Linker
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "Symbols.h"
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#include "SyntheticSections.h"
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#include "Target.h"
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#include "Thunks.h"
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[lld] unified COFF and ELF error handling on new Common/ErrorHandler
Summary:
The COFF linker and the ELF linker have long had similar but separate
Error.h and Error.cpp files to implement error handling. This change
introduces new error handling code in Common/ErrorHandler.h, changes the
COFF and ELF linkers to use it, and removes the old, separate
implementations.
Reviewers: ruiu
Reviewed By: ruiu
Subscribers: smeenai, jyknight, emaste, sdardis, nemanjai, nhaehnle, mgorny, javed.absar, kbarton, fedor.sergeev, llvm-commits
Differential Revision: https://reviews.llvm.org/D39259
llvm-svn: 316624
2017-10-26 06:28:38 +08:00
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#include "lld/Common/ErrorHandler.h"
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2017-06-17 01:32:43 +08:00
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#include "llvm/Object/ELF.h"
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#include "llvm/Support/Endian.h"
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using namespace llvm;
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using namespace llvm::support::endian;
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using namespace llvm::ELF;
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using namespace lld;
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using namespace lld::elf;
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// Page(Expr) is the page address of the expression Expr, defined
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// as (Expr & ~0xFFF). (This applies even if the machine page size
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// supported by the platform has a different value.)
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uint64_t elf::getAArch64Page(uint64_t Expr) {
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return Expr & ~static_cast<uint64_t>(0xFFF);
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}
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namespace {
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class AArch64 final : public TargetInfo {
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public:
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AArch64();
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2017-11-04 05:21:47 +08:00
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RelExpr getRelExpr(RelType Type, const Symbol &S,
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2017-06-17 01:32:43 +08:00
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const uint8_t *Loc) const override;
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2018-04-05 20:07:20 +08:00
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RelType getDynRel(RelType Type) const override;
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2017-11-04 05:21:47 +08:00
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void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
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2017-06-17 01:32:43 +08:00
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void writePltHeader(uint8_t *Buf) const override;
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void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
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int32_t Index, unsigned RelOff) const override;
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2017-11-29 19:15:12 +08:00
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bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
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uint64_t BranchAddr, const Symbol &S) const override;
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2018-08-20 17:37:50 +08:00
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uint32_t getThunkSectionSpacing() const override;
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2017-11-29 19:15:12 +08:00
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bool inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const override;
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2017-10-12 06:49:24 +08:00
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bool usesOnlyLowPageBits(RelType Type) const override;
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void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
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RelExpr adjustRelaxExpr(RelType Type, const uint8_t *Data,
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2017-06-17 01:32:43 +08:00
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RelExpr Expr) const override;
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2017-10-12 06:49:24 +08:00
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void relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
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void relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
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void relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
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2017-06-17 01:32:43 +08:00
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};
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} // namespace
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AArch64::AArch64() {
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CopyRel = R_AARCH64_COPY;
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RelativeRel = R_AARCH64_RELATIVE;
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IRelativeRel = R_AARCH64_IRELATIVE;
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GotRel = R_AARCH64_GLOB_DAT;
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PltRel = R_AARCH64_JUMP_SLOT;
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TlsDescRel = R_AARCH64_TLSDESC;
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TlsGotRel = R_AARCH64_TLS_TPREL64;
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GotEntrySize = 8;
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GotPltEntrySize = 8;
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PltEntrySize = 16;
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PltHeaderSize = 32;
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DefaultMaxPageSize = 65536;
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Align AArch64 and i386 image base to superpage
Summary:
As for x86_64, the default image base for AArch64 and i386 should be
aligned to a superpage appropriate for the architecture.
On AArch64, this is 2 MiB, on i386 it is 4 MiB.
Reviewers: emaste, grimar, javed.absar, espindola, ruiu, peter.smith, srhines, rprichard
Reviewed By: ruiu, peter.smith
Subscribers: jfb, markj, arichardson, krytarowski, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D50297
llvm-svn: 342746
2018-09-22 00:58:13 +08:00
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// Align to the 2 MiB page size (known as a superpage or huge page).
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// FreeBSD automatically promotes 2 MiB-aligned allocations.
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DefaultImageBase = 0x200000;
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2017-06-17 01:32:43 +08:00
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// It doesn't seem to be documented anywhere, but tls on aarch64 uses variant
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// 1 of the tls structures and the tcb size is 16.
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TcbSize = 16;
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2017-11-29 19:15:12 +08:00
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NeedsThunks = true;
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2017-06-17 01:32:43 +08:00
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}
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2017-11-04 05:21:47 +08:00
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RelExpr AArch64::getRelExpr(RelType Type, const Symbol &S,
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2017-10-12 11:14:06 +08:00
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const uint8_t *Loc) const {
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2017-06-17 01:32:43 +08:00
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switch (Type) {
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case R_AARCH64_TLSDESC_ADR_PAGE21:
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return R_TLSDESC_PAGE;
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case R_AARCH64_TLSDESC_LD64_LO12:
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case R_AARCH64_TLSDESC_ADD_LO12:
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return R_TLSDESC;
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case R_AARCH64_TLSDESC_CALL:
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return R_TLSDESC_CALL;
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case R_AARCH64_TLSLE_ADD_TPREL_HI12:
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case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
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2018-05-04 16:53:34 +08:00
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case R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC:
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case R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC:
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case R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC:
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case R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC:
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case R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC:
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2017-06-17 01:32:43 +08:00
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return R_TLS;
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case R_AARCH64_CALL26:
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case R_AARCH64_CONDBR19:
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case R_AARCH64_JUMP26:
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case R_AARCH64_TSTBR14:
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return R_PLT_PC;
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case R_AARCH64_PREL16:
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case R_AARCH64_PREL32:
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case R_AARCH64_PREL64:
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case R_AARCH64_ADR_PREL_LO21:
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2017-09-21 07:49:50 +08:00
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case R_AARCH64_LD_PREL_LO19:
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2017-06-17 01:32:43 +08:00
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return R_PC;
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case R_AARCH64_ADR_PREL_PG_HI21:
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return R_PAGE_PC;
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case R_AARCH64_LD64_GOT_LO12_NC:
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case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
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return R_GOT;
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case R_AARCH64_ADR_GOT_PAGE:
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case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
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return R_GOT_PAGE_PC;
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case R_AARCH64_NONE:
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return R_NONE;
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2017-10-12 11:14:06 +08:00
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default:
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return R_ABS;
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2017-06-17 01:32:43 +08:00
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}
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}
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2017-10-12 06:49:24 +08:00
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RelExpr AArch64::adjustRelaxExpr(RelType Type, const uint8_t *Data,
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2017-06-17 01:32:43 +08:00
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RelExpr Expr) const {
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if (Expr == R_RELAX_TLS_GD_TO_IE) {
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if (Type == R_AARCH64_TLSDESC_ADR_PAGE21)
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return R_RELAX_TLS_GD_TO_IE_PAGE_PC;
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return R_RELAX_TLS_GD_TO_IE_ABS;
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}
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return Expr;
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}
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2017-10-12 06:49:24 +08:00
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bool AArch64::usesOnlyLowPageBits(RelType Type) const {
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2017-06-17 01:32:43 +08:00
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switch (Type) {
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default:
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return false;
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case R_AARCH64_ADD_ABS_LO12_NC:
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case R_AARCH64_LD64_GOT_LO12_NC:
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case R_AARCH64_LDST128_ABS_LO12_NC:
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case R_AARCH64_LDST16_ABS_LO12_NC:
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case R_AARCH64_LDST32_ABS_LO12_NC:
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case R_AARCH64_LDST64_ABS_LO12_NC:
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case R_AARCH64_LDST8_ABS_LO12_NC:
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case R_AARCH64_TLSDESC_ADD_LO12:
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case R_AARCH64_TLSDESC_LD64_LO12:
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case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
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return true;
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}
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}
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2018-04-05 20:07:20 +08:00
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RelType AArch64::getDynRel(RelType Type) const {
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if (Type == R_AARCH64_ABS32 || Type == R_AARCH64_ABS64)
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return Type;
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return R_AARCH64_NONE;
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2017-06-17 01:32:43 +08:00
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}
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2017-11-04 05:21:47 +08:00
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void AArch64::writeGotPlt(uint8_t *Buf, const Symbol &) const {
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2017-06-17 01:32:43 +08:00
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write64le(Buf, InX::Plt->getVA());
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}
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void AArch64::writePltHeader(uint8_t *Buf) const {
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const uint8_t PltData[] = {
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0xf0, 0x7b, 0xbf, 0xa9, // stp x16, x30, [sp,#-16]!
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0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[2]))
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0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[2]))]
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0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[2]))
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0x20, 0x02, 0x1f, 0xd6, // br x17
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0x1f, 0x20, 0x03, 0xd5, // nop
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0x1f, 0x20, 0x03, 0xd5, // nop
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0x1f, 0x20, 0x03, 0xd5 // nop
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};
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memcpy(Buf, PltData, sizeof(PltData));
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uint64_t Got = InX::GotPlt->getVA();
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uint64_t Plt = InX::Plt->getVA();
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relocateOne(Buf + 4, R_AARCH64_ADR_PREL_PG_HI21,
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getAArch64Page(Got + 16) - getAArch64Page(Plt + 4));
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relocateOne(Buf + 8, R_AARCH64_LDST64_ABS_LO12_NC, Got + 16);
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relocateOne(Buf + 12, R_AARCH64_ADD_ABS_LO12_NC, Got + 16);
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}
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void AArch64::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
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uint64_t PltEntryAddr, int32_t Index,
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unsigned RelOff) const {
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const uint8_t Inst[] = {
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0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[n]))
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0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[n]))]
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0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[n]))
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0x20, 0x02, 0x1f, 0xd6 // br x17
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};
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memcpy(Buf, Inst, sizeof(Inst));
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relocateOne(Buf, R_AARCH64_ADR_PREL_PG_HI21,
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getAArch64Page(GotPltEntryAddr) - getAArch64Page(PltEntryAddr));
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relocateOne(Buf + 4, R_AARCH64_LDST64_ABS_LO12_NC, GotPltEntryAddr);
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relocateOne(Buf + 8, R_AARCH64_ADD_ABS_LO12_NC, GotPltEntryAddr);
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}
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2017-11-29 19:15:12 +08:00
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bool AArch64::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
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uint64_t BranchAddr, const Symbol &S) const {
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// ELF for the ARM 64-bit architecture, section Call and Jump relocations
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// only permits range extension thunks for R_AARCH64_CALL26 and
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// R_AARCH64_JUMP26 relocation types.
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if (Type != R_AARCH64_CALL26 && Type != R_AARCH64_JUMP26)
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return false;
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uint64_t Dst = (Expr == R_PLT_PC) ? S.getPltVA() : S.getVA();
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return !inBranchRange(Type, BranchAddr, Dst);
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}
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2018-08-20 17:37:50 +08:00
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uint32_t AArch64::getThunkSectionSpacing() const {
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// See comment in Arch/ARM.cpp for a more detailed explanation of
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// getThunkSectionSpacing(). For AArch64 the only branches we are permitted to
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// Thunk have a range of +/- 128 MiB
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return (128 * 1024 * 1024) - 0x30000;
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}
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2017-11-29 19:15:12 +08:00
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bool AArch64::inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const {
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if (Type != R_AARCH64_CALL26 && Type != R_AARCH64_JUMP26)
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return true;
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// The AArch64 call and unconditional branch instructions have a range of
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// +/- 128 MiB.
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uint64_t Range = 128 * 1024 * 1024;
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if (Dst > Src) {
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// Immediate of branch is signed.
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Range -= 4;
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return Dst - Src <= Range;
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}
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return Src - Dst <= Range;
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}
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2017-06-17 01:32:43 +08:00
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static void write32AArch64Addr(uint8_t *L, uint64_t Imm) {
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uint32_t ImmLo = (Imm & 0x3) << 29;
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uint32_t ImmHi = (Imm & 0x1FFFFC) << 3;
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uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3);
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write32le(L, (read32le(L) & ~Mask) | ImmLo | ImmHi);
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}
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// Return the bits [Start, End] from Val shifted Start bits.
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// For instance, getBits(0xF0, 4, 8) returns 0xF.
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static uint64_t getBits(uint64_t Val, int Start, int End) {
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uint64_t Mask = ((uint64_t)1 << (End + 1 - Start)) - 1;
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return (Val >> Start) & Mask;
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}
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static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); }
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// Update the immediate field in a AARCH64 ldr, str, and add instruction.
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static void or32AArch64Imm(uint8_t *L, uint64_t Imm) {
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or32le(L, (Imm & 0xFFF) << 10);
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}
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2017-10-12 06:49:24 +08:00
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void AArch64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
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2017-06-17 01:32:43 +08:00
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switch (Type) {
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case R_AARCH64_ABS16:
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case R_AARCH64_PREL16:
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2018-03-30 06:40:52 +08:00
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checkIntUInt(Loc, Val, 16, Type);
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2017-06-17 01:32:43 +08:00
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write16le(Loc, Val);
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break;
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case R_AARCH64_ABS32:
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case R_AARCH64_PREL32:
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2018-03-30 06:40:52 +08:00
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checkIntUInt(Loc, Val, 32, Type);
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2017-06-17 01:32:43 +08:00
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write32le(Loc, Val);
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break;
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case R_AARCH64_ABS64:
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case R_AARCH64_GLOB_DAT:
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case R_AARCH64_PREL64:
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write64le(Loc, Val);
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|
|
|
break;
|
|
|
|
case R_AARCH64_ADD_ABS_LO12_NC:
|
|
|
|
or32AArch64Imm(Loc, Val);
|
|
|
|
break;
|
|
|
|
case R_AARCH64_ADR_GOT_PAGE:
|
|
|
|
case R_AARCH64_ADR_PREL_PG_HI21:
|
|
|
|
case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
|
|
|
|
case R_AARCH64_TLSDESC_ADR_PAGE21:
|
2018-03-30 06:40:52 +08:00
|
|
|
checkInt(Loc, Val, 33, Type);
|
2017-06-17 01:32:43 +08:00
|
|
|
write32AArch64Addr(Loc, Val >> 12);
|
|
|
|
break;
|
|
|
|
case R_AARCH64_ADR_PREL_LO21:
|
2018-03-30 06:40:52 +08:00
|
|
|
checkInt(Loc, Val, 21, Type);
|
2017-06-17 01:32:43 +08:00
|
|
|
write32AArch64Addr(Loc, Val);
|
|
|
|
break;
|
|
|
|
case R_AARCH64_JUMP26:
|
2017-09-08 00:29:52 +08:00
|
|
|
// Normally we would just write the bits of the immediate field, however
|
|
|
|
// when patching instructions for the cpu errata fix -fix-cortex-a53-843419
|
|
|
|
// we want to replace a non-branch instruction with a branch immediate
|
|
|
|
// instruction. By writing all the bits of the instruction including the
|
|
|
|
// opcode and the immediate (0 001 | 01 imm26) we can do this
|
|
|
|
// transformation by placing a R_AARCH64_JUMP26 relocation at the offset of
|
|
|
|
// the instruction we want to patch.
|
|
|
|
write32le(Loc, 0x14000000);
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
case R_AARCH64_CALL26:
|
2018-03-30 06:40:52 +08:00
|
|
|
checkInt(Loc, Val, 28, Type);
|
2017-06-17 01:32:43 +08:00
|
|
|
or32le(Loc, (Val & 0x0FFFFFFC) >> 2);
|
|
|
|
break;
|
|
|
|
case R_AARCH64_CONDBR19:
|
2017-09-21 07:49:50 +08:00
|
|
|
case R_AARCH64_LD_PREL_LO19:
|
2018-03-30 06:40:52 +08:00
|
|
|
checkAlignment(Loc, Val, 4, Type);
|
|
|
|
checkInt(Loc, Val, 21, Type);
|
2017-06-17 01:32:43 +08:00
|
|
|
or32le(Loc, (Val & 0x1FFFFC) << 3);
|
|
|
|
break;
|
|
|
|
case R_AARCH64_LDST8_ABS_LO12_NC:
|
2018-05-04 16:53:34 +08:00
|
|
|
case R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC:
|
2017-06-17 01:32:43 +08:00
|
|
|
or32AArch64Imm(Loc, getBits(Val, 0, 11));
|
|
|
|
break;
|
|
|
|
case R_AARCH64_LDST16_ABS_LO12_NC:
|
2018-05-04 16:53:34 +08:00
|
|
|
case R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC:
|
2018-03-30 06:40:52 +08:00
|
|
|
checkAlignment(Loc, Val, 2, Type);
|
2017-06-17 01:32:43 +08:00
|
|
|
or32AArch64Imm(Loc, getBits(Val, 1, 11));
|
|
|
|
break;
|
|
|
|
case R_AARCH64_LDST32_ABS_LO12_NC:
|
2018-05-04 16:53:34 +08:00
|
|
|
case R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC:
|
2018-03-30 06:40:52 +08:00
|
|
|
checkAlignment(Loc, Val, 4, Type);
|
2017-06-17 01:32:43 +08:00
|
|
|
or32AArch64Imm(Loc, getBits(Val, 2, 11));
|
|
|
|
break;
|
|
|
|
case R_AARCH64_LDST64_ABS_LO12_NC:
|
2018-05-03 20:59:52 +08:00
|
|
|
case R_AARCH64_LD64_GOT_LO12_NC:
|
|
|
|
case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
|
2018-05-04 16:53:34 +08:00
|
|
|
case R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC:
|
2018-05-03 20:59:52 +08:00
|
|
|
case R_AARCH64_TLSDESC_LD64_LO12:
|
2018-03-30 06:40:52 +08:00
|
|
|
checkAlignment(Loc, Val, 8, Type);
|
2017-06-17 01:32:43 +08:00
|
|
|
or32AArch64Imm(Loc, getBits(Val, 3, 11));
|
|
|
|
break;
|
|
|
|
case R_AARCH64_LDST128_ABS_LO12_NC:
|
2018-05-04 16:53:34 +08:00
|
|
|
case R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC:
|
2018-03-30 06:40:52 +08:00
|
|
|
checkAlignment(Loc, Val, 16, Type);
|
2017-06-17 01:32:43 +08:00
|
|
|
or32AArch64Imm(Loc, getBits(Val, 4, 11));
|
|
|
|
break;
|
|
|
|
case R_AARCH64_MOVW_UABS_G0_NC:
|
|
|
|
or32le(Loc, (Val & 0xFFFF) << 5);
|
|
|
|
break;
|
|
|
|
case R_AARCH64_MOVW_UABS_G1_NC:
|
|
|
|
or32le(Loc, (Val & 0xFFFF0000) >> 11);
|
|
|
|
break;
|
|
|
|
case R_AARCH64_MOVW_UABS_G2_NC:
|
|
|
|
or32le(Loc, (Val & 0xFFFF00000000) >> 27);
|
|
|
|
break;
|
|
|
|
case R_AARCH64_MOVW_UABS_G3:
|
|
|
|
or32le(Loc, (Val & 0xFFFF000000000000) >> 43);
|
|
|
|
break;
|
|
|
|
case R_AARCH64_TSTBR14:
|
2018-03-30 06:40:52 +08:00
|
|
|
checkInt(Loc, Val, 16, Type);
|
2017-06-17 01:32:43 +08:00
|
|
|
or32le(Loc, (Val & 0xFFFC) << 3);
|
|
|
|
break;
|
|
|
|
case R_AARCH64_TLSLE_ADD_TPREL_HI12:
|
2018-03-30 06:40:52 +08:00
|
|
|
checkInt(Loc, Val, 24, Type);
|
2017-06-17 01:32:43 +08:00
|
|
|
or32AArch64Imm(Loc, Val >> 12);
|
|
|
|
break;
|
|
|
|
case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
|
|
|
|
case R_AARCH64_TLSDESC_ADD_LO12:
|
|
|
|
or32AArch64Imm(Loc, Val);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-10-12 06:49:24 +08:00
|
|
|
void AArch64::relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
|
2017-06-17 01:32:43 +08:00
|
|
|
// TLSDESC Global-Dynamic relocation are in the form:
|
|
|
|
// adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21]
|
|
|
|
// ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12]
|
|
|
|
// add x0, x0, :tlsdesc_los:v [R_AARCH64_TLSDESC_ADD_LO12]
|
|
|
|
// .tlsdesccall [R_AARCH64_TLSDESC_CALL]
|
|
|
|
// blr x1
|
|
|
|
// And it can optimized to:
|
|
|
|
// movz x0, #0x0, lsl #16
|
|
|
|
// movk x0, #0x10
|
|
|
|
// nop
|
|
|
|
// nop
|
2018-03-30 06:40:52 +08:00
|
|
|
checkUInt(Loc, Val, 32, Type);
|
2017-06-17 01:32:43 +08:00
|
|
|
|
|
|
|
switch (Type) {
|
|
|
|
case R_AARCH64_TLSDESC_ADD_LO12:
|
|
|
|
case R_AARCH64_TLSDESC_CALL:
|
|
|
|
write32le(Loc, 0xd503201f); // nop
|
|
|
|
return;
|
|
|
|
case R_AARCH64_TLSDESC_ADR_PAGE21:
|
|
|
|
write32le(Loc, 0xd2a00000 | (((Val >> 16) & 0xffff) << 5)); // movz
|
|
|
|
return;
|
|
|
|
case R_AARCH64_TLSDESC_LD64_LO12:
|
|
|
|
write32le(Loc, 0xf2800000 | ((Val & 0xffff) << 5)); // movk
|
|
|
|
return;
|
|
|
|
default:
|
|
|
|
llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-10-12 06:49:24 +08:00
|
|
|
void AArch64::relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const {
|
2017-06-17 01:32:43 +08:00
|
|
|
// TLSDESC Global-Dynamic relocation are in the form:
|
|
|
|
// adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21]
|
|
|
|
// ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12]
|
|
|
|
// add x0, x0, :tlsdesc_los:v [R_AARCH64_TLSDESC_ADD_LO12]
|
|
|
|
// .tlsdesccall [R_AARCH64_TLSDESC_CALL]
|
|
|
|
// blr x1
|
|
|
|
// And it can optimized to:
|
|
|
|
// adrp x0, :gottprel:v
|
|
|
|
// ldr x0, [x0, :gottprel_lo12:v]
|
|
|
|
// nop
|
|
|
|
// nop
|
|
|
|
|
|
|
|
switch (Type) {
|
|
|
|
case R_AARCH64_TLSDESC_ADD_LO12:
|
|
|
|
case R_AARCH64_TLSDESC_CALL:
|
|
|
|
write32le(Loc, 0xd503201f); // nop
|
|
|
|
break;
|
|
|
|
case R_AARCH64_TLSDESC_ADR_PAGE21:
|
|
|
|
write32le(Loc, 0x90000000); // adrp
|
|
|
|
relocateOne(Loc, R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, Val);
|
|
|
|
break;
|
|
|
|
case R_AARCH64_TLSDESC_LD64_LO12:
|
|
|
|
write32le(Loc, 0xf9400000); // ldr
|
|
|
|
relocateOne(Loc, R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, Val);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-10-12 06:49:24 +08:00
|
|
|
void AArch64::relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
|
2018-03-30 06:40:52 +08:00
|
|
|
checkUInt(Loc, Val, 32, Type);
|
2017-06-17 01:32:43 +08:00
|
|
|
|
|
|
|
if (Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) {
|
|
|
|
// Generate MOVZ.
|
|
|
|
uint32_t RegNo = read32le(Loc) & 0x1f;
|
|
|
|
write32le(Loc, (0xd2a00000 | RegNo) | (((Val >> 16) & 0xffff) << 5));
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) {
|
|
|
|
// Generate MOVK.
|
|
|
|
uint32_t RegNo = read32le(Loc) & 0x1f;
|
|
|
|
write32le(Loc, (0xf2800000 | RegNo) | ((Val & 0xffff) << 5));
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
llvm_unreachable("invalid relocation for TLS IE to LE relaxation");
|
|
|
|
}
|
|
|
|
|
2017-06-17 04:15:03 +08:00
|
|
|
TargetInfo *elf::getAArch64TargetInfo() {
|
|
|
|
static AArch64 Target;
|
|
|
|
return &Target;
|
|
|
|
}
|