2015-06-30 07:51:55 +08:00
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//==- WebAssemblyMCTargetDesc.h - WebAssembly Target Descriptions -*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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2018-05-01 23:54:18 +08:00
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/// This file provides WebAssembly-specific target descriptions.
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2015-06-30 07:51:55 +08:00
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
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#define LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
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2017-06-07 11:48:56 +08:00
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#include "llvm/BinaryFormat/Wasm.h"
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2016-01-12 11:09:16 +08:00
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#include "llvm/MC/MCInstrDesc.h"
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2015-06-30 07:51:55 +08:00
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#include "llvm/Support/DataTypes.h"
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2017-10-11 01:31:43 +08:00
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#include <memory>
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2015-06-30 07:51:55 +08:00
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namespace llvm {
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class MCAsmBackend;
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class MCCodeEmitter;
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class MCContext;
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class MCInstrInfo;
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2018-05-22 03:20:29 +08:00
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class MCObjectTargetWriter;
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2015-06-30 07:51:55 +08:00
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class MCSubtargetInfo;
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2016-10-25 07:27:49 +08:00
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class MVT;
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2015-06-30 07:51:55 +08:00
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class Target;
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class Triple;
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2015-11-24 00:50:18 +08:00
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class raw_pwrite_stream;
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2015-06-30 07:51:55 +08:00
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2016-10-10 07:00:34 +08:00
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Target &getTheWebAssemblyTarget32();
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Target &getTheWebAssemblyTarget64();
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2015-06-30 07:51:55 +08:00
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2017-06-17 07:59:10 +08:00
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MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII);
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2015-11-24 00:50:18 +08:00
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2016-01-08 08:43:54 +08:00
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MCAsmBackend *createWebAssemblyAsmBackend(const Triple &TT);
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2015-06-30 07:51:55 +08:00
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2018-05-22 03:20:29 +08:00
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std::unique_ptr<MCObjectTargetWriter>
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createWebAssemblyWasmObjectWriter(bool Is64Bit);
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2017-02-22 09:23:18 +08:00
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2016-01-12 11:09:16 +08:00
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namespace WebAssembly {
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enum OperandType {
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/// Basic block label in a branch construct.
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OPERAND_BASIC_BLOCK = MCOI::OPERAND_FIRST_TARGET,
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2016-10-25 03:49:43 +08:00
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/// Local index.
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OPERAND_LOCAL,
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2017-02-03 03:29:44 +08:00
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/// Global index.
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OPERAND_GLOBAL,
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2016-10-06 05:24:08 +08:00
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/// 32-bit integer immediates.
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OPERAND_I32IMM,
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/// 64-bit integer immediates.
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OPERAND_I64IMM,
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2016-02-16 23:14:23 +08:00
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/// 32-bit floating-point immediates.
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2016-10-04 05:31:31 +08:00
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OPERAND_F32IMM,
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2016-02-16 23:14:23 +08:00
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/// 64-bit floating-point immediates.
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2016-10-04 05:31:31 +08:00
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OPERAND_F64IMM,
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2016-12-23 11:23:52 +08:00
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/// 32-bit unsigned function indices.
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OPERAND_FUNCTION32,
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/// 32-bit unsigned memory offsets.
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OPERAND_OFFSET32,
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2016-01-26 11:39:31 +08:00
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/// p2align immediate for load and store address alignment.
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2016-10-07 06:29:32 +08:00
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OPERAND_P2ALIGN,
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/// signature immediate for block/loop.
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2017-02-25 07:18:00 +08:00
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OPERAND_SIGNATURE,
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/// type signature immediate for call_indirect.
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OPERAND_TYPEINDEX,
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2016-01-12 11:09:16 +08:00
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};
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} // end namespace WebAssembly
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namespace WebAssemblyII {
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enum {
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// For variadic instructions, this flag indicates whether an operand
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// in the variable_ops range is an immediate value.
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2016-01-13 04:30:51 +08:00
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VariableOpIsImmediate = (1 << 0),
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[WebAssembly] Make CFG stackification independent of basic-block labels.
This patch changes the way labels are referenced. Instead of referencing the
basic-block label name (eg. .LBB0_0), instructions now just have an immediate
which indicates the depth in the control-flow stack to find a label to jump to.
This makes them much closer to what we expect to have in the binary encoding,
and avoids the problem of basic-block label names not being explicit in the
binary encoding.
Also, it terminates blocks and loops with end_block and end_loop instructions,
rather than basic-block label names, for similar reasons.
This will also fix problems where two constructs appear to have the same label,
because we no longer explicitly use labels, so consumers that need labels will
presumably create their own labels, and presumably they won't reuse labels
when they do.
This patch does make the code a little more awkward to read; as a partial
mitigation, this patch also introduces comments showing where the labels are,
and comments on each branch showing where it's branching to.
llvm-svn: 257505
2016-01-13 03:14:46 +08:00
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// For immediate values in the variable_ops range, this flag indicates
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// whether the value represents a control-flow label.
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2016-10-25 07:27:49 +08:00
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VariableOpImmediateIsLabel = (1 << 1)
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2016-01-12 11:09:16 +08:00
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};
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} // end namespace WebAssemblyII
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2015-06-30 07:51:55 +08:00
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} // end namespace llvm
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// Defines symbolic names for WebAssembly registers. This defines a mapping from
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// register name to register number.
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//
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2015-07-11 02:23:10 +08:00
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#define GET_REGINFO_ENUM
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#include "WebAssemblyGenRegisterInfo.inc"
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2015-07-23 05:28:15 +08:00
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// Defines symbolic names for the WebAssembly instructions.
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//
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#define GET_INSTRINFO_ENUM
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#include "WebAssemblyGenInstrInfo.inc"
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2015-06-30 07:51:55 +08:00
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#define GET_SUBTARGETINFO_ENUM
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#include "WebAssemblyGenSubtargetInfo.inc"
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2016-01-26 11:39:31 +08:00
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namespace llvm {
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namespace WebAssembly {
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/// Return the default p2align value for a load or store with the given opcode.
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inline unsigned GetDefaultP2Align(unsigned Opcode) {
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switch (Opcode) {
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case WebAssembly::LOAD8_S_I32:
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2018-06-19 05:22:44 +08:00
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case WebAssembly::LOAD8_S_I32_S:
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2016-01-26 11:39:31 +08:00
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case WebAssembly::LOAD8_U_I32:
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2018-06-19 05:22:44 +08:00
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case WebAssembly::LOAD8_U_I32_S:
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2016-01-26 11:39:31 +08:00
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case WebAssembly::LOAD8_S_I64:
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2018-06-19 05:22:44 +08:00
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case WebAssembly::LOAD8_S_I64_S:
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2016-01-26 11:39:31 +08:00
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case WebAssembly::LOAD8_U_I64:
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2018-06-19 05:22:44 +08:00
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case WebAssembly::LOAD8_U_I64_S:
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2017-10-06 05:18:42 +08:00
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case WebAssembly::ATOMIC_LOAD8_U_I32:
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2018-06-19 05:22:44 +08:00
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case WebAssembly::ATOMIC_LOAD8_U_I32_S:
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2017-10-06 05:18:42 +08:00
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case WebAssembly::ATOMIC_LOAD8_U_I64:
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2018-06-19 05:22:44 +08:00
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case WebAssembly::ATOMIC_LOAD8_U_I64_S:
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2016-01-26 11:39:31 +08:00
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case WebAssembly::STORE8_I32:
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2018-06-19 05:22:44 +08:00
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case WebAssembly::STORE8_I32_S:
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2016-01-26 11:39:31 +08:00
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case WebAssembly::STORE8_I64:
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2018-06-19 05:22:44 +08:00
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case WebAssembly::STORE8_I64_S:
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2018-07-03 05:22:59 +08:00
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case WebAssembly::ATOMIC_STORE8_I32:
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2018-07-06 05:27:09 +08:00
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case WebAssembly::ATOMIC_STORE8_I32_S:
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2018-07-03 05:22:59 +08:00
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case WebAssembly::ATOMIC_STORE8_I64:
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2018-07-06 05:27:09 +08:00
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case WebAssembly::ATOMIC_STORE8_I64_S:
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[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
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case WebAssembly::ATOMIC_RMW8_U_ADD_I32:
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case WebAssembly::ATOMIC_RMW8_U_ADD_I32_S:
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case WebAssembly::ATOMIC_RMW8_U_ADD_I64:
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case WebAssembly::ATOMIC_RMW8_U_ADD_I64_S:
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case WebAssembly::ATOMIC_RMW8_U_SUB_I32:
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case WebAssembly::ATOMIC_RMW8_U_SUB_I32_S:
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case WebAssembly::ATOMIC_RMW8_U_SUB_I64:
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case WebAssembly::ATOMIC_RMW8_U_SUB_I64_S:
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case WebAssembly::ATOMIC_RMW8_U_AND_I32:
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case WebAssembly::ATOMIC_RMW8_U_AND_I32_S:
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case WebAssembly::ATOMIC_RMW8_U_AND_I64:
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case WebAssembly::ATOMIC_RMW8_U_AND_I64_S:
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case WebAssembly::ATOMIC_RMW8_U_OR_I32:
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case WebAssembly::ATOMIC_RMW8_U_OR_I32_S:
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case WebAssembly::ATOMIC_RMW8_U_OR_I64:
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case WebAssembly::ATOMIC_RMW8_U_OR_I64_S:
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case WebAssembly::ATOMIC_RMW8_U_XOR_I32:
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case WebAssembly::ATOMIC_RMW8_U_XOR_I32_S:
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case WebAssembly::ATOMIC_RMW8_U_XOR_I64:
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case WebAssembly::ATOMIC_RMW8_U_XOR_I64_S:
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case WebAssembly::ATOMIC_RMW8_U_XCHG_I32:
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case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_S:
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case WebAssembly::ATOMIC_RMW8_U_XCHG_I64:
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case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_S:
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2018-08-02 03:40:28 +08:00
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case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32:
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case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_S:
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case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64:
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case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_S:
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2016-01-26 11:39:31 +08:00
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return 0;
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case WebAssembly::LOAD16_S_I32:
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2018-06-19 05:22:44 +08:00
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case WebAssembly::LOAD16_S_I32_S:
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2016-01-26 11:39:31 +08:00
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case WebAssembly::LOAD16_U_I32:
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2018-06-19 05:22:44 +08:00
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case WebAssembly::LOAD16_U_I32_S:
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2016-01-26 11:39:31 +08:00
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case WebAssembly::LOAD16_S_I64:
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2018-06-19 05:22:44 +08:00
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case WebAssembly::LOAD16_S_I64_S:
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2016-01-26 11:39:31 +08:00
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case WebAssembly::LOAD16_U_I64:
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2018-06-19 05:22:44 +08:00
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case WebAssembly::LOAD16_U_I64_S:
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2017-10-06 05:18:42 +08:00
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case WebAssembly::ATOMIC_LOAD16_U_I32:
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2018-06-19 05:22:44 +08:00
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case WebAssembly::ATOMIC_LOAD16_U_I32_S:
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2017-10-06 05:18:42 +08:00
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case WebAssembly::ATOMIC_LOAD16_U_I64:
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2018-06-19 05:22:44 +08:00
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case WebAssembly::ATOMIC_LOAD16_U_I64_S:
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2016-01-26 11:39:31 +08:00
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case WebAssembly::STORE16_I32:
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2018-06-19 05:22:44 +08:00
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case WebAssembly::STORE16_I32_S:
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2016-01-26 11:39:31 +08:00
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case WebAssembly::STORE16_I64:
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2018-06-19 05:22:44 +08:00
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case WebAssembly::STORE16_I64_S:
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2018-07-03 05:22:59 +08:00
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case WebAssembly::ATOMIC_STORE16_I32:
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2018-07-06 05:27:09 +08:00
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case WebAssembly::ATOMIC_STORE16_I32_S:
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2018-07-03 05:22:59 +08:00
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case WebAssembly::ATOMIC_STORE16_I64:
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2018-07-06 05:27:09 +08:00
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case WebAssembly::ATOMIC_STORE16_I64_S:
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[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
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case WebAssembly::ATOMIC_RMW16_U_ADD_I32:
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case WebAssembly::ATOMIC_RMW16_U_ADD_I32_S:
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case WebAssembly::ATOMIC_RMW16_U_ADD_I64:
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case WebAssembly::ATOMIC_RMW16_U_ADD_I64_S:
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case WebAssembly::ATOMIC_RMW16_U_SUB_I32:
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case WebAssembly::ATOMIC_RMW16_U_SUB_I32_S:
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case WebAssembly::ATOMIC_RMW16_U_SUB_I64:
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case WebAssembly::ATOMIC_RMW16_U_SUB_I64_S:
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case WebAssembly::ATOMIC_RMW16_U_AND_I32:
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case WebAssembly::ATOMIC_RMW16_U_AND_I32_S:
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case WebAssembly::ATOMIC_RMW16_U_AND_I64:
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case WebAssembly::ATOMIC_RMW16_U_AND_I64_S:
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case WebAssembly::ATOMIC_RMW16_U_OR_I32:
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case WebAssembly::ATOMIC_RMW16_U_OR_I32_S:
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case WebAssembly::ATOMIC_RMW16_U_OR_I64:
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case WebAssembly::ATOMIC_RMW16_U_OR_I64_S:
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case WebAssembly::ATOMIC_RMW16_U_XOR_I32:
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case WebAssembly::ATOMIC_RMW16_U_XOR_I32_S:
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case WebAssembly::ATOMIC_RMW16_U_XOR_I64:
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case WebAssembly::ATOMIC_RMW16_U_XOR_I64_S:
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case WebAssembly::ATOMIC_RMW16_U_XCHG_I32:
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case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_S:
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case WebAssembly::ATOMIC_RMW16_U_XCHG_I64:
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case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_S:
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2018-08-02 03:40:28 +08:00
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case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32:
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case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_S:
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case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64:
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case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_S:
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2016-01-26 11:39:31 +08:00
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return 1;
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case WebAssembly::LOAD_I32:
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2018-06-19 05:22:44 +08:00
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case WebAssembly::LOAD_I32_S:
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2016-01-26 11:39:31 +08:00
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case WebAssembly::LOAD_F32:
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2018-06-19 05:22:44 +08:00
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case WebAssembly::LOAD_F32_S:
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2016-01-26 11:39:31 +08:00
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case WebAssembly::STORE_I32:
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2018-06-19 05:22:44 +08:00
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case WebAssembly::STORE_I32_S:
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2016-01-26 11:39:31 +08:00
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case WebAssembly::STORE_F32:
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2018-06-19 05:22:44 +08:00
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case WebAssembly::STORE_F32_S:
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2016-01-26 11:39:31 +08:00
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case WebAssembly::LOAD32_S_I64:
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2018-06-19 05:22:44 +08:00
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case WebAssembly::LOAD32_S_I64_S:
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2016-01-26 11:39:31 +08:00
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case WebAssembly::LOAD32_U_I64:
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2018-06-19 05:22:44 +08:00
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case WebAssembly::LOAD32_U_I64_S:
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2016-01-26 11:39:31 +08:00
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case WebAssembly::STORE32_I64:
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2018-06-19 05:22:44 +08:00
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case WebAssembly::STORE32_I64_S:
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2017-08-31 02:07:45 +08:00
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case WebAssembly::ATOMIC_LOAD_I32:
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2018-06-19 05:22:44 +08:00
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case WebAssembly::ATOMIC_LOAD_I32_S:
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2017-10-06 05:18:42 +08:00
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case WebAssembly::ATOMIC_LOAD32_U_I64:
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2018-06-19 05:22:44 +08:00
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case WebAssembly::ATOMIC_LOAD32_U_I64_S:
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2018-07-03 05:22:59 +08:00
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case WebAssembly::ATOMIC_STORE_I32:
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2018-07-06 05:27:09 +08:00
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|
|
case WebAssembly::ATOMIC_STORE_I32_S:
|
2018-07-03 05:22:59 +08:00
|
|
|
case WebAssembly::ATOMIC_STORE32_I64:
|
2018-07-06 05:27:09 +08:00
|
|
|
case WebAssembly::ATOMIC_STORE32_I64_S:
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
case WebAssembly::ATOMIC_RMW_ADD_I32:
|
|
|
|
case WebAssembly::ATOMIC_RMW_ADD_I32_S:
|
|
|
|
case WebAssembly::ATOMIC_RMW32_U_ADD_I64:
|
|
|
|
case WebAssembly::ATOMIC_RMW32_U_ADD_I64_S:
|
|
|
|
case WebAssembly::ATOMIC_RMW_SUB_I32:
|
|
|
|
case WebAssembly::ATOMIC_RMW_SUB_I32_S:
|
|
|
|
case WebAssembly::ATOMIC_RMW32_U_SUB_I64:
|
|
|
|
case WebAssembly::ATOMIC_RMW32_U_SUB_I64_S:
|
|
|
|
case WebAssembly::ATOMIC_RMW_AND_I32:
|
|
|
|
case WebAssembly::ATOMIC_RMW_AND_I32_S:
|
|
|
|
case WebAssembly::ATOMIC_RMW32_U_AND_I64:
|
|
|
|
case WebAssembly::ATOMIC_RMW32_U_AND_I64_S:
|
|
|
|
case WebAssembly::ATOMIC_RMW_OR_I32:
|
|
|
|
case WebAssembly::ATOMIC_RMW_OR_I32_S:
|
|
|
|
case WebAssembly::ATOMIC_RMW32_U_OR_I64:
|
|
|
|
case WebAssembly::ATOMIC_RMW32_U_OR_I64_S:
|
|
|
|
case WebAssembly::ATOMIC_RMW_XOR_I32:
|
|
|
|
case WebAssembly::ATOMIC_RMW_XOR_I32_S:
|
|
|
|
case WebAssembly::ATOMIC_RMW32_U_XOR_I64:
|
|
|
|
case WebAssembly::ATOMIC_RMW32_U_XOR_I64_S:
|
|
|
|
case WebAssembly::ATOMIC_RMW_XCHG_I32:
|
|
|
|
case WebAssembly::ATOMIC_RMW_XCHG_I32_S:
|
|
|
|
case WebAssembly::ATOMIC_RMW32_U_XCHG_I64:
|
|
|
|
case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_S:
|
2018-08-02 03:40:28 +08:00
|
|
|
case WebAssembly::ATOMIC_RMW_CMPXCHG_I32:
|
|
|
|
case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_S:
|
|
|
|
case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64:
|
|
|
|
case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_S:
|
2016-01-26 11:39:31 +08:00
|
|
|
return 2;
|
|
|
|
case WebAssembly::LOAD_I64:
|
2018-06-19 05:22:44 +08:00
|
|
|
case WebAssembly::LOAD_I64_S:
|
2016-01-26 11:39:31 +08:00
|
|
|
case WebAssembly::LOAD_F64:
|
2018-06-19 05:22:44 +08:00
|
|
|
case WebAssembly::LOAD_F64_S:
|
2016-01-26 11:39:31 +08:00
|
|
|
case WebAssembly::STORE_I64:
|
2018-06-19 05:22:44 +08:00
|
|
|
case WebAssembly::STORE_I64_S:
|
2016-01-26 11:39:31 +08:00
|
|
|
case WebAssembly::STORE_F64:
|
2018-06-19 05:22:44 +08:00
|
|
|
case WebAssembly::STORE_F64_S:
|
2017-10-06 05:18:42 +08:00
|
|
|
case WebAssembly::ATOMIC_LOAD_I64:
|
2018-06-19 05:22:44 +08:00
|
|
|
case WebAssembly::ATOMIC_LOAD_I64_S:
|
2018-07-03 05:22:59 +08:00
|
|
|
case WebAssembly::ATOMIC_STORE_I64:
|
2018-07-06 05:27:09 +08:00
|
|
|
case WebAssembly::ATOMIC_STORE_I64_S:
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
case WebAssembly::ATOMIC_RMW_ADD_I64:
|
|
|
|
case WebAssembly::ATOMIC_RMW_ADD_I64_S:
|
|
|
|
case WebAssembly::ATOMIC_RMW_SUB_I64:
|
|
|
|
case WebAssembly::ATOMIC_RMW_SUB_I64_S:
|
|
|
|
case WebAssembly::ATOMIC_RMW_AND_I64:
|
|
|
|
case WebAssembly::ATOMIC_RMW_AND_I64_S:
|
|
|
|
case WebAssembly::ATOMIC_RMW_OR_I64:
|
|
|
|
case WebAssembly::ATOMIC_RMW_OR_I64_S:
|
|
|
|
case WebAssembly::ATOMIC_RMW_XOR_I64:
|
|
|
|
case WebAssembly::ATOMIC_RMW_XOR_I64_S:
|
|
|
|
case WebAssembly::ATOMIC_RMW_XCHG_I64:
|
|
|
|
case WebAssembly::ATOMIC_RMW_XCHG_I64_S:
|
2018-08-02 03:40:28 +08:00
|
|
|
case WebAssembly::ATOMIC_RMW_CMPXCHG_I64:
|
|
|
|
case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_S:
|
2016-01-26 11:39:31 +08:00
|
|
|
return 3;
|
2016-08-02 06:25:02 +08:00
|
|
|
default:
|
|
|
|
llvm_unreachable("Only loads and stores have p2align values");
|
2016-01-26 11:39:31 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-01-31 05:43:08 +08:00
|
|
|
/// The operand number of the load or store address in load/store instructions.
|
2016-10-25 08:17:11 +08:00
|
|
|
static const unsigned LoadAddressOperandNo = 3;
|
|
|
|
static const unsigned StoreAddressOperandNo = 2;
|
2016-10-07 06:08:28 +08:00
|
|
|
|
|
|
|
/// The operand number of the load or store p2align in load/store instructions.
|
2016-10-25 08:17:11 +08:00
|
|
|
static const unsigned LoadP2AlignOperandNo = 1;
|
|
|
|
static const unsigned StoreP2AlignOperandNo = 0;
|
2016-01-26 11:39:31 +08:00
|
|
|
|
2016-10-07 06:29:32 +08:00
|
|
|
/// This is used to indicate block signatures.
|
2018-03-03 04:52:59 +08:00
|
|
|
enum class ExprType : unsigned {
|
2018-03-08 12:05:37 +08:00
|
|
|
Void = 0x40,
|
|
|
|
I32 = 0x7F,
|
|
|
|
I64 = 0x7E,
|
|
|
|
F32 = 0x7D,
|
|
|
|
F64 = 0x7C,
|
|
|
|
I8x16 = 0x7B,
|
|
|
|
I16x8 = 0x7A,
|
|
|
|
I32x4 = 0x79,
|
|
|
|
F32x4 = 0x78,
|
|
|
|
B8x16 = 0x77,
|
|
|
|
B16x8 = 0x76,
|
|
|
|
B32x4 = 0x75,
|
|
|
|
ExceptRef = 0x68
|
2016-10-25 03:49:43 +08:00
|
|
|
};
|
|
|
|
|
2016-10-25 07:27:49 +08:00
|
|
|
/// Instruction opcodes emitted via means other than CodeGen.
|
|
|
|
static const unsigned Nop = 0x01;
|
|
|
|
static const unsigned End = 0x0b;
|
|
|
|
|
2017-03-15 04:23:22 +08:00
|
|
|
wasm::ValType toValType(const MVT &Ty);
|
2016-10-25 07:27:49 +08:00
|
|
|
|
2016-01-26 11:39:31 +08:00
|
|
|
} // end namespace WebAssembly
|
|
|
|
} // end namespace llvm
|
|
|
|
|
2015-06-30 07:51:55 +08:00
|
|
|
#endif
|