2012-02-19 10:03:36 +08:00
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//===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
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2010-02-10 07:52:19 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2012-02-18 20:03:15 +08:00
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//
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2010-02-10 07:52:19 +08:00
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//===----------------------------------------------------------------------===//
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//
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// This file provides pattern fragments useful for SIMD instructions.
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//
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//===----------------------------------------------------------------------===//
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2015-02-05 21:22:50 +08:00
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//===----------------------------------------------------------------------===//
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// MMX specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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// Low word of MMX to GPR.
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def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
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[SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
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2015-02-05 21:23:07 +08:00
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// GPR to low word of MMX.
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def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
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[SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
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2015-02-05 21:22:50 +08:00
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2010-02-10 07:52:19 +08:00
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//===----------------------------------------------------------------------===//
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// MMX Pattern Fragments
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//===----------------------------------------------------------------------===//
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2010-10-01 07:57:10 +08:00
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def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
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2015-02-23 23:23:14 +08:00
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def load_mvmmx : PatFrag<(ops node:$ptr),
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(x86mmx (MMX_X86movw2d (load node:$ptr)))>;
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2010-10-01 07:57:10 +08:00
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def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
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2010-07-13 07:41:28 +08:00
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//===----------------------------------------------------------------------===//
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// SSE specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
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SDTCisFP<0>, SDTCisInt<2> ]>;
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def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
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2014-01-26 12:59:39 +08:00
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SDTCisFP<1>, SDTCisVT<3, i8>,
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SDTCisVec<1>]>;
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2010-07-13 07:41:28 +08:00
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2012-12-21 22:04:55 +08:00
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def X86umin : SDNode<"X86ISD::UMIN", SDTIntBinOp>;
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def X86umax : SDNode<"X86ISD::UMAX", SDTIntBinOp>;
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def X86smin : SDNode<"X86ISD::SMIN", SDTIntBinOp>;
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def X86smax : SDNode<"X86ISD::SMAX", SDTIntBinOp>;
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2010-07-13 07:41:28 +08:00
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def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
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def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
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2012-08-19 21:06:16 +08:00
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// Commutative and Associative FMIN and FMAX.
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def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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2010-07-13 07:41:28 +08:00
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def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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X86: Turn fp selects into mask operations.
double test(double a, double b, double c, double d) { return a<b ? c : d; }
before:
_test:
ucomisd %xmm0, %xmm1
ja LBB0_2
movaps %xmm3, %xmm2
LBB0_2:
movaps %xmm2, %xmm0
after:
_test:
cmpltsd %xmm1, %xmm0
andpd %xmm0, %xmm2
andnpd %xmm3, %xmm0
orpd %xmm2, %xmm0
Small speedup on Benchmarks/SmallPT
llvm-svn: 187706
2013-08-04 20:05:16 +08:00
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def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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2010-07-13 07:41:28 +08:00
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def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
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def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
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def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
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2011-06-01 12:39:42 +08:00
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def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
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2011-09-23 04:15:48 +08:00
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def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
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def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
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2011-11-19 17:02:40 +08:00
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def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
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def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
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2010-07-13 07:41:28 +08:00
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def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
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def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
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2013-12-16 21:52:35 +08:00
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def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
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//def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
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2010-07-13 07:41:28 +08:00
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def X86pshufb : SDNode<"X86ISD::PSHUFB",
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2012-01-25 14:43:11 +08:00
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SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
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2010-07-13 07:41:28 +08:00
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SDTCisSameAs<0,2>]>>;
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[x86] Implement a faster vector population count based on the PSHUFB
in-register LUT technique.
Summary:
A description of this technique can be found here:
http://wm.ite.pl/articles/sse-popcount.html
The core of the idea is to use an in-register lookup table and the
PSHUFB instruction to compute the population count for the low and high
nibbles of each byte, and then to use horizontal sums to aggregate these
into vector population counts with wider element types.
On x86 there is an instruction that will directly compute the horizontal
sum for the low 8 and high 8 bytes, giving vNi64 popcount very easily.
Various tricks are used to get vNi32 and vNi16 from the vNi8 that the
LUT computes.
The base implemantion of this, and most of the work, was done by Bruno
in a follow up to D6531. See Bruno's detailed post there for lots of
timing information about these changes.
I have extended Bruno's patch in the following ways:
0) I committed the new tests with baseline sequences so this shows
a diff, and regenerated the tests using the update scripts.
1) Bruno had noticed and mentioned in IRC a redundant mask that
I removed.
2) I introduced a particular optimization for the i32 vector cases where
we use PSHL + PSADBW to compute the the low i32 popcounts, and PSHUFD
+ PSADBW to compute doubled high i32 popcounts. This takes advantage
of the fact that to line up the high i32 popcounts we have to shift
them anyways, and we can shift them by one fewer bit to effectively
divide the count by two. While the PSHUFD based horizontal add is no
faster, it doesn't require registers or load traffic the way a mask
would, and provides more ILP as it happens on different ports with
high throughput.
3) I did some code cleanups throughout to simplify the implementation
logic.
4) I refactored it to continue to use the parallel bitmath lowering when
SSSE3 is not available to preserve the performance of that version on
SSE2 targets where it is still much better than scalarizing as we'll
still do a bitmath implementation of popcount even in scalar code
there.
With #1 and #2 above, I analyzed the result in IACA for sandybridge,
ivybridge, and haswell. In every case I measured, the throughput is the
same or better using the LUT lowering, even v2i64 and v4i64, and even
compared with using the native popcnt instruction! The latency of the
LUT lowering is often higher than the latency of the scalarized popcnt
instruction sequence, but I think those latency measurements are deeply
misleading. Keeping the operation fully in the vector unit and having
many chances for increased throughput seems much more likely to win.
With this, we can lower every integer vector popcount implementation
using the LUT strategy if we have SSSE3 or better (and thus have
PSHUFB). I've updated the operation lowering to reflect this. This also
fixes an issue where we were scalarizing horribly some AVX lowerings.
Finally, there are some remaining cleanups. There is duplication between
the two techniques in how they perform the horizontal sum once the byte
population count is computed. I'm going to factor and merge those two in
a separate follow-up commit.
Differential Revision: http://reviews.llvm.org/D10084
llvm-svn: 238636
2015-05-30 11:20:59 +08:00
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def X86psadbw : SDNode<"X86ISD::PSADBW",
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SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
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SDTCisSameAs<0,2>]>>;
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2011-07-14 05:36:47 +08:00
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def X86andnp : SDNode<"X86ISD::ANDNP",
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2011-07-14 05:36:51 +08:00
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SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
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2010-12-18 06:55:37 +08:00
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SDTCisSameAs<0,2>]>>;
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2011-11-19 15:33:10 +08:00
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def X86psign : SDNode<"X86ISD::PSIGN",
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2011-11-19 15:07:26 +08:00
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SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
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2010-12-18 06:55:37 +08:00
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SDTCisSameAs<0,2>]>>;
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2010-07-13 07:41:28 +08:00
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def X86pextrb : SDNode<"X86ISD::PEXTRB",
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SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
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def X86pextrw : SDNode<"X86ISD::PEXTRW",
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SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
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def X86pinsrb : SDNode<"X86ISD::PINSRB",
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SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
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SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
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def X86pinsrw : SDNode<"X86ISD::PINSRW",
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SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
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SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
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2014-04-22 04:07:29 +08:00
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def X86insertps : SDNode<"X86ISD::INSERTPS",
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2010-07-13 07:41:28 +08:00
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SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
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[x86] Fix a pretty horrible bug and inconsistency in the x86 asm
parsing (and latent bug in the instruction definitions).
This is effectively a revert of r136287 which tried to address
a specific and narrow case of immediate operands failing to be accepted
by x86 instructions with a pretty heavy hammer: it introduced a new kind
of operand that behaved differently. All of that is removed with this
commit, but the test cases are both preserved and enhanced.
The core problem that r136287 and this commit are trying to handle is
that gas accepts both of the following instructions:
insertps $192, %xmm0, %xmm1
insertps $-64, %xmm0, %xmm1
These will encode to the same byte sequence, with the immediate
occupying an 8-bit entry. The first form was fixed by r136287 but that
broke the prior handling of the second form! =[ Ironically, we would
still emit the second form in some cases and then be unable to
re-assemble the output.
The reason why the first instruction failed to be handled is because
prior to r136287 the operands ere marked 'i32i8imm' which forces them to
be sign-extenable. Clearly, that won't work for 192 in a single byte.
However, making thim zero-extended or "unsigned" doesn't really address
the core issue either because it breaks negative immediates. The correct
fix is to make these operands 'i8imm' reflecting that they can be either
signed or unsigned but must be 8-bit immediates. This patch backs out
r136287 and then changes those places as well as some others to use
'i8imm' rather than one of the extended variants.
Naturally, this broke something else. The custom DAG nodes had to be
updated to have a much more accurate type constraint of an i8 node, and
a bunch of Pat immediates needed to be specified as i8 values.
The fallout didn't end there though. We also then ceased to be able to
match the instruction-specific intrinsics to the instructions so
modified. Digging, this is because they too used i32 rather than i8 in
their signature. So I've also switched those intrinsics to i8 arguments
in line with the instructions.
In order to make the intrinsic adjustments of course, I also had to add
auto upgrading for the intrinsics.
I suspect that the intrinsic argument types may have led everything down
this rabbit hole. Pretty happy with the result.
llvm-svn: 217310
2014-09-06 18:00:01 +08:00
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SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
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2010-07-13 07:41:28 +08:00
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def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
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SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
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2012-04-22 17:39:03 +08:00
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2010-07-13 07:41:28 +08:00
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def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
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2010-09-22 08:34:38 +08:00
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[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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2012-08-15 05:24:47 +08:00
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2012-10-24 01:34:00 +08:00
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def X86vzext : SDNode<"X86ISD::VZEXT",
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SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
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2014-01-26 12:59:39 +08:00
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SDTCisInt<0>, SDTCisInt<1>,
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SDTCisOpSmallerThanOp<1, 0>]>>;
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2012-10-24 01:34:00 +08:00
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def X86vsext : SDNode<"X86ISD::VSEXT",
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SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
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2014-01-26 12:59:39 +08:00
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SDTCisInt<0>, SDTCisInt<1>,
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SDTCisOpSmallerThanOp<1, 0>]>>;
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2012-10-24 01:34:00 +08:00
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2013-08-29 19:56:53 +08:00
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def X86vtrunc : SDNode<"X86ISD::VTRUNC",
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SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
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2014-01-26 12:59:39 +08:00
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SDTCisInt<0>, SDTCisInt<1>,
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SDTCisOpSmallerThanOp<0, 1>]>>;
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2013-12-17 16:33:15 +08:00
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def X86trunc : SDNode<"X86ISD::TRUNC",
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2014-01-26 12:59:39 +08:00
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SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
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SDTCisOpSmallerThanOp<0, 1>]>>;
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2013-08-29 19:56:53 +08:00
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def X86vtruncm : SDNode<"X86ISD::VTRUNCM",
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SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
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SDTCisInt<0>, SDTCisInt<1>,
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2014-01-26 12:59:39 +08:00
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SDTCisVec<2>, SDTCisInt<2>,
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SDTCisOpSmallerThanOp<0, 2>]>>;
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2012-08-15 05:24:47 +08:00
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def X86vfpext : SDNode<"X86ISD::VFPEXT",
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SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
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2014-01-26 12:59:39 +08:00
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SDTCisFP<0>, SDTCisFP<1>,
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SDTCisOpSmallerThanOp<1, 0>]>>;
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2012-10-11 00:53:28 +08:00
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def X86vfpround: SDNode<"X86ISD::VFPROUND",
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SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
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2014-01-26 12:59:39 +08:00
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SDTCisFP<0>, SDTCisFP<1>,
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SDTCisOpSmallerThanOp<0, 1>]>>;
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2012-08-15 05:24:47 +08:00
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2012-01-23 03:15:14 +08:00
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def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
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def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
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2012-01-23 07:36:02 +08:00
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def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
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2012-01-23 06:42:16 +08:00
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def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
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def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
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2010-07-13 07:41:28 +08:00
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2013-08-13 21:24:07 +08:00
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def X86IntCmpMask : SDTypeProfile<1, 2,
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[SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
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def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
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def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
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2013-12-16 21:52:35 +08:00
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def X86CmpMaskCC :
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2015-05-07 19:24:42 +08:00
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SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
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SDTCisVec<1>, SDTCisSameAs<2, 1>,
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SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
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def X86CmpMaskCCRound :
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SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
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SDTCisVec<1>, SDTCisSameAs<2, 1>,
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SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
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SDTCisInt<4>]>;
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2013-12-16 21:52:35 +08:00
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def X86CmpMaskCCScalar :
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SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
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2015-05-07 19:24:42 +08:00
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def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
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def X86cmpmRnd : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
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def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
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def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>;
|
2013-08-13 21:24:07 +08:00
|
|
|
|
2012-01-23 03:15:14 +08:00
|
|
|
def X86vshl : SDNode<"X86ISD::VSHL",
|
|
|
|
|
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisVec<2>]>>;
|
|
|
|
|
def X86vsrl : SDNode<"X86ISD::VSRL",
|
|
|
|
|
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisVec<2>]>>;
|
|
|
|
|
def X86vsra : SDNode<"X86ISD::VSRA",
|
|
|
|
|
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisVec<2>]>>;
|
|
|
|
|
|
|
|
|
|
def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
|
|
|
|
|
def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
|
|
|
|
|
def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
|
|
|
|
|
|
2010-07-13 07:41:28 +08:00
|
|
|
def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
|
2010-08-11 07:25:42 +08:00
|
|
|
SDTCisVec<1>,
|
|
|
|
|
SDTCisSameAs<2, 1>]>;
|
2015-05-04 20:35:55 +08:00
|
|
|
def X86addus : SDNode<"X86ISD::ADDUS", SDTIntBinOp>;
|
2012-12-16 00:47:44 +08:00
|
|
|
def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
|
2015-05-04 20:35:55 +08:00
|
|
|
def X86adds : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
|
|
|
|
|
def X86subs : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
|
2010-07-13 07:41:28 +08:00
|
|
|
def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
|
2010-08-11 07:25:42 +08:00
|
|
|
def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
|
2013-08-05 16:52:21 +08:00
|
|
|
def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
|
2013-12-16 21:52:35 +08:00
|
|
|
def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
|
2015-04-21 21:13:46 +08:00
|
|
|
SDTCisVec<1>, SDTCisSameAs<2, 1>,
|
|
|
|
|
SDTCVecEltisVT<0, i1>,
|
|
|
|
|
SDTCisSameNumEltsAs<0, 1>]>>;
|
2014-02-05 15:05:03 +08:00
|
|
|
def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
|
2015-04-21 21:13:46 +08:00
|
|
|
SDTCisVec<1>, SDTCisSameAs<2, 1>,
|
|
|
|
|
SDTCVecEltisVT<0, i1>,
|
|
|
|
|
SDTCisSameNumEltsAs<0, 1>]>>;
|
2013-12-16 21:52:35 +08:00
|
|
|
def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>;
|
2010-07-13 07:41:28 +08:00
|
|
|
|
2012-02-05 11:14:49 +08:00
|
|
|
def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
|
|
|
|
|
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
|
|
|
|
|
SDTCisSameAs<1,2>]>>;
|
2014-04-26 22:12:19 +08:00
|
|
|
def X86pmuldq : SDNode<"X86ISD::PMULDQ",
|
|
|
|
|
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
|
|
|
|
|
SDTCisSameAs<1,2>]>>;
|
2012-02-05 11:14:49 +08:00
|
|
|
|
2010-08-21 06:55:05 +08:00
|
|
|
// Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
|
|
|
|
|
// translated into one of the target nodes below during lowering.
|
|
|
|
|
// Note: this is a work in progress...
|
|
|
|
|
def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
|
|
|
|
|
def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisSameAs<0,2>]>;
|
2013-08-11 15:55:09 +08:00
|
|
|
def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
|
2010-08-21 06:55:05 +08:00
|
|
|
|
2014-09-23 18:08:29 +08:00
|
|
|
def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisVec<2>]>;
|
2010-08-21 06:55:05 +08:00
|
|
|
def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
|
|
|
|
|
SDTCisSameAs<0,1>, SDTCisInt<2>]>;
|
|
|
|
|
def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisSameAs<0,2>, SDTCisInt<3>]>;
|
2015-06-01 14:50:49 +08:00
|
|
|
def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisSameAs<0,2>, SDTCisInt<3>, SDTCisInt<4>]>;
|
2010-08-21 06:55:05 +08:00
|
|
|
|
2013-08-07 20:34:55 +08:00
|
|
|
def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
|
|
|
|
|
def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
|
|
|
|
|
|
2012-04-11 14:40:27 +08:00
|
|
|
def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
|
[x86] Fix a pretty horrible bug and inconsistency in the x86 asm
parsing (and latent bug in the instruction definitions).
This is effectively a revert of r136287 which tried to address
a specific and narrow case of immediate operands failing to be accepted
by x86 instructions with a pretty heavy hammer: it introduced a new kind
of operand that behaved differently. All of that is removed with this
commit, but the test cases are both preserved and enhanced.
The core problem that r136287 and this commit are trying to handle is
that gas accepts both of the following instructions:
insertps $192, %xmm0, %xmm1
insertps $-64, %xmm0, %xmm1
These will encode to the same byte sequence, with the immediate
occupying an 8-bit entry. The first form was fixed by r136287 but that
broke the prior handling of the second form! =[ Ironically, we would
still emit the second form in some cases and then be unable to
re-assemble the output.
The reason why the first instruction failed to be handled is because
prior to r136287 the operands ere marked 'i32i8imm' which forces them to
be sign-extenable. Clearly, that won't work for 192 in a single byte.
However, making thim zero-extended or "unsigned" doesn't really address
the core issue either because it breaks negative immediates. The correct
fix is to make these operands 'i8imm' reflecting that they can be either
signed or unsigned but must be 8-bit immediates. This patch backs out
r136287 and then changes those places as well as some others to use
'i8imm' rather than one of the extended variants.
Naturally, this broke something else. The custom DAG nodes had to be
updated to have a much more accurate type constraint of an i8 node, and
a bunch of Pat immediates needed to be specified as i8 values.
The fallout didn't end there though. We also then ceased to be able to
match the instruction-specific intrinsics to the instructions so
modified. Digging, this is because they too used i32 rather than i8 in
their signature. So I've also switched those intrinsics to i8 arguments
in line with the instructions.
In order to make the intrinsic adjustments of course, I also had to add
auto upgrading for the intrinsics.
I suspect that the intrinsic argument types may have led everything down
this rabbit hole. Pretty happy with the result.
llvm-svn: 217310
2014-09-06 18:00:01 +08:00
|
|
|
SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
|
2012-08-01 20:06:00 +08:00
|
|
|
|
2015-02-18 15:59:20 +08:00
|
|
|
def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc.
|
|
|
|
|
SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
|
|
|
|
|
|
2012-08-01 20:06:00 +08:00
|
|
|
def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
|
2015-01-28 18:21:27 +08:00
|
|
|
def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
|
2014-11-12 15:31:03 +08:00
|
|
|
def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisVec<0>, SDTCisInt<2>]>;
|
2014-11-26 18:46:49 +08:00
|
|
|
def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisVec<0>, SDTCisInt<3>]>;
|
2015-02-23 23:12:31 +08:00
|
|
|
def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisVec<0>, SDTCisInt<3>, SDTCisInt<4>]>;
|
2011-08-17 10:29:19 +08:00
|
|
|
|
2013-01-28 14:48:25 +08:00
|
|
|
def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
|
2014-08-06 01:22:55 +08:00
|
|
|
def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
|
2010-08-21 06:55:05 +08:00
|
|
|
|
|
|
|
|
def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
|
|
|
|
|
def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
|
|
|
|
|
def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
|
|
|
|
|
|
2012-01-01 07:50:21 +08:00
|
|
|
def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
|
2010-08-21 06:55:05 +08:00
|
|
|
|
|
|
|
|
def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
|
|
|
|
|
def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
|
|
|
|
|
def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
|
|
|
|
|
|
|
|
|
|
def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
|
|
|
|
|
def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
|
|
|
|
|
|
|
|
|
|
def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
|
|
|
|
|
def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
|
2010-09-01 05:15:21 +08:00
|
|
|
def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
|
2010-08-21 06:55:05 +08:00
|
|
|
|
2010-09-01 13:08:25 +08:00
|
|
|
def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
|
|
|
|
|
def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
|
2010-08-21 06:55:05 +08:00
|
|
|
|
2014-06-20 09:05:28 +08:00
|
|
|
def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>;
|
|
|
|
|
def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
|
|
|
|
|
def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
|
|
|
|
|
|
2011-12-06 16:21:25 +08:00
|
|
|
def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
|
|
|
|
|
def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
|
2010-08-21 06:55:05 +08:00
|
|
|
|
2014-09-23 18:08:29 +08:00
|
|
|
def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
|
2014-09-23 06:29:42 +08:00
|
|
|
def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
|
|
|
|
|
def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
|
|
|
|
|
def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
|
|
|
|
|
def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>;
|
2014-01-23 22:27:26 +08:00
|
|
|
def X86VPermiv3 : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
|
Add support for 256-bit versions of VPERMIL instruction. This is a new
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:
Instead of:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vextractf128 $1, %ymm0, %xmm1
shufps $1, %xmm1, %xmm1
movss %xmm1, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm1, 16(%rsp)
vextractf128 $0, %ymm0, %xmm0
shufps $1, %xmm0, %xmm0
movss %xmm0, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm0, (%rsp)
vmovaps (%rsp), %ymm0
We get:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vpermilps $85, %ymm0, %ymm0
llvm-svn: 135662
2011-07-21 09:55:47 +08:00
|
|
|
|
2011-11-30 15:47:51 +08:00
|
|
|
def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
|
2011-08-13 05:48:26 +08:00
|
|
|
|
2015-06-01 14:50:49 +08:00
|
|
|
def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPBinOpImmRound>;
|
|
|
|
|
|
2015-05-18 14:42:57 +08:00
|
|
|
def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
|
|
|
|
|
SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
|
|
|
|
|
SDTCisSubVecOfVec<1, 0>]>, []>;
|
2011-08-17 10:29:19 +08:00
|
|
|
def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
|
2013-09-12 16:55:00 +08:00
|
|
|
def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
|
|
|
|
|
[SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
|
2014-02-10 15:02:39 +08:00
|
|
|
def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2,
|
|
|
|
|
[SDTCisVec<1>, SDTCisPtrTy<2>]>, []>;
|
2011-08-17 10:29:19 +08:00
|
|
|
|
2012-12-05 17:24:57 +08:00
|
|
|
def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
|
2014-09-16 04:09:47 +08:00
|
|
|
|
|
|
|
|
def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
|
|
|
|
|
|
2015-02-18 15:59:20 +08:00
|
|
|
def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
|
|
|
|
|
def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>;
|
|
|
|
|
def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>;
|
|
|
|
|
def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>;
|
2015-05-11 14:05:05 +08:00
|
|
|
def X86fmaxRnd : SDNode<"X86ISD::FMAX_RND", SDTFPBinOpRound>;
|
|
|
|
|
def X86fminRnd : SDNode<"X86ISD::FMIN_RND", SDTFPBinOpRound>;
|
2015-02-18 15:59:20 +08:00
|
|
|
|
2012-08-01 20:06:00 +08:00
|
|
|
def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
|
|
|
|
|
def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
|
|
|
|
|
def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
|
|
|
|
|
def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
|
2012-08-29 15:18:25 +08:00
|
|
|
def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
|
|
|
|
|
def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
|
2012-04-11 14:40:27 +08:00
|
|
|
|
2015-01-28 18:21:27 +08:00
|
|
|
def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound>;
|
|
|
|
|
def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound>;
|
|
|
|
|
def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound>;
|
|
|
|
|
def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound>;
|
|
|
|
|
def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound>;
|
|
|
|
|
def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound>;
|
|
|
|
|
|
2014-11-12 15:31:03 +08:00
|
|
|
def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", STDFp1SrcRm>;
|
|
|
|
|
def X86rcp28 : SDNode<"X86ISD::RCP28", STDFp1SrcRm>;
|
2014-11-26 18:46:49 +08:00
|
|
|
def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
|
|
|
|
|
|
|
|
|
|
def X86rsqrt28s : SDNode<"X86ISD::RSQRT28", STDFp2SrcRm>;
|
|
|
|
|
def X86rcp28s : SDNode<"X86ISD::RCP28", STDFp2SrcRm>;
|
2015-02-23 23:12:31 +08:00
|
|
|
def X86RndScale : SDNode<"X86ISD::RNDSCALE", STDFp3SrcRm>;
|
2014-11-12 15:31:03 +08:00
|
|
|
|
2012-08-06 14:22:36 +08:00
|
|
|
def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
|
|
|
|
|
SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
|
|
|
|
|
SDTCisVT<4, i8>]>;
|
|
|
|
|
def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
|
|
|
|
|
SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
|
|
|
|
|
SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
|
|
|
|
|
SDTCisVT<6, i8>]>;
|
|
|
|
|
|
|
|
|
|
def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
|
|
|
|
|
def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
|
|
|
|
|
|
2014-12-11 23:02:24 +08:00
|
|
|
def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 3,
|
|
|
|
|
[SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
|
|
|
|
|
SDTCisVec<3>, SDTCisVec<1>, SDTCisInt<1>]>, []>;
|
2014-12-15 18:03:52 +08:00
|
|
|
def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 3,
|
|
|
|
|
[SDTCisSameAs<0, 3>,
|
|
|
|
|
SDTCisVec<3>, SDTCisVec<1>, SDTCisInt<1>]>, []>;
|
2014-12-11 23:02:24 +08:00
|
|
|
|
2010-07-13 07:41:28 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// SSE Complex Patterns
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
|
|
// These are 'extloads' from a scalar to the low element of a vector, zeroing
|
|
|
|
|
// the top elements. These are used for the SSE 'ss' and 'sd' instruction
|
|
|
|
|
// forms.
|
|
|
|
|
def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
|
2010-09-22 04:31:19 +08:00
|
|
|
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
|
|
|
|
|
SDNPWantRoot]>;
|
2010-07-13 07:41:28 +08:00
|
|
|
def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
|
2010-09-22 04:31:19 +08:00
|
|
|
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
|
|
|
|
|
SDNPWantRoot]>;
|
2010-07-13 07:41:28 +08:00
|
|
|
|
|
|
|
|
def ssmem : Operand<v4f32> {
|
|
|
|
|
let PrintMethod = "printf32mem";
|
|
|
|
|
let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
|
2013-08-26 08:39:04 +08:00
|
|
|
let ParserMatchClass = X86Mem32AsmOperand;
|
2011-07-15 05:47:22 +08:00
|
|
|
let OperandType = "OPERAND_MEMORY";
|
2010-07-13 07:41:28 +08:00
|
|
|
}
|
|
|
|
|
def sdmem : Operand<v2f64> {
|
|
|
|
|
let PrintMethod = "printf64mem";
|
|
|
|
|
let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
|
2013-08-26 08:39:04 +08:00
|
|
|
let ParserMatchClass = X86Mem64AsmOperand;
|
2011-07-15 05:47:22 +08:00
|
|
|
let OperandType = "OPERAND_MEMORY";
|
2010-07-13 07:41:28 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// SSE pattern fragments
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
2010-08-14 04:39:01 +08:00
|
|
|
// 128-bit load pattern fragments
|
2012-01-24 11:03:17 +08:00
|
|
|
// NOTE: all 128-bit integer vector loads are promoted to v2i64
|
2010-07-13 07:41:28 +08:00
|
|
|
def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
|
|
|
|
|
def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
|
|
|
|
|
def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
|
|
|
|
|
|
2010-08-14 04:39:01 +08:00
|
|
|
// 256-bit load pattern fragments
|
2012-01-24 11:03:17 +08:00
|
|
|
// NOTE: all 256-bit integer vector loads are promoted to v4i64
|
2010-07-13 07:41:28 +08:00
|
|
|
def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
|
|
|
|
|
def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
|
|
|
|
|
def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
|
|
|
|
|
|
2013-08-11 15:55:09 +08:00
|
|
|
// 512-bit load pattern fragments
|
|
|
|
|
def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
|
|
|
|
|
def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
|
[SKX] Enabling load/store instructions: encoding
Instructions: VMOVAPD, VMOVAPS, VMOVDQA8, VMOVDQA16, VMOVDQA32,VMOVDQA64, VMOVDQU8, VMOVDQU16, VMOVDQU32,VMOVDQU64, VMOVUPD, VMOVUPS,
Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>
llvm-svn: 214719
2014-08-04 22:35:15 +08:00
|
|
|
def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
|
|
|
|
|
def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
|
2013-10-22 17:19:28 +08:00
|
|
|
def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
|
2013-08-11 15:55:09 +08:00
|
|
|
def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
|
|
|
|
|
|
|
|
|
|
// 128-/256-/512-bit extload pattern fragments
|
2012-09-11 02:33:51 +08:00
|
|
|
def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
|
|
|
|
|
def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
|
2013-08-11 15:55:09 +08:00
|
|
|
def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
|
2012-09-11 02:33:51 +08:00
|
|
|
|
2015-02-18 04:08:21 +08:00
|
|
|
// These are needed to match a scalar load that is used in a vector-only
|
|
|
|
|
// math instruction such as the FP logical ops: andps, andnps, orps, xorps.
|
|
|
|
|
// The memory operand is required to be a 128-bit load, so it must be converted
|
|
|
|
|
// from a vector to a scalar.
|
|
|
|
|
def loadf32_128 : PatFrag<(ops node:$ptr),
|
|
|
|
|
(f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
|
|
|
|
|
def loadf64_128 : PatFrag<(ops node:$ptr),
|
|
|
|
|
(f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
|
|
|
|
|
|
2011-09-14 03:33:03 +08:00
|
|
|
// Like 'store', but always requires 128-bit vector alignment.
|
2010-07-13 07:41:28 +08:00
|
|
|
def alignedstore : PatFrag<(ops node:$val, node:$ptr),
|
|
|
|
|
(store node:$val, node:$ptr), [{
|
|
|
|
|
return cast<StoreSDNode>(N)->getAlignment() >= 16;
|
|
|
|
|
}]>;
|
|
|
|
|
|
2011-09-14 03:33:03 +08:00
|
|
|
// Like 'store', but always requires 256-bit vector alignment.
|
|
|
|
|
def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
|
|
|
|
|
(store node:$val, node:$ptr), [{
|
|
|
|
|
return cast<StoreSDNode>(N)->getAlignment() >= 32;
|
|
|
|
|
}]>;
|
|
|
|
|
|
2013-08-11 15:55:09 +08:00
|
|
|
// Like 'store', but always requires 512-bit vector alignment.
|
|
|
|
|
def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
|
|
|
|
|
(store node:$val, node:$ptr), [{
|
|
|
|
|
return cast<StoreSDNode>(N)->getAlignment() >= 64;
|
|
|
|
|
}]>;
|
|
|
|
|
|
2011-09-14 03:33:03 +08:00
|
|
|
// Like 'load', but always requires 128-bit vector alignment.
|
2010-07-13 07:41:28 +08:00
|
|
|
def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
|
|
|
|
|
return cast<LoadSDNode>(N)->getAlignment() >= 16;
|
|
|
|
|
}]>;
|
|
|
|
|
|
2012-03-09 10:00:48 +08:00
|
|
|
// Like 'X86vzload', but always requires 128-bit vector alignment.
|
|
|
|
|
def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
|
|
|
|
|
return cast<MemSDNode>(N)->getAlignment() >= 16;
|
|
|
|
|
}]>;
|
|
|
|
|
|
2011-09-14 03:33:03 +08:00
|
|
|
// Like 'load', but always requires 256-bit vector alignment.
|
|
|
|
|
def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
|
|
|
|
|
return cast<LoadSDNode>(N)->getAlignment() >= 32;
|
|
|
|
|
}]>;
|
|
|
|
|
|
2013-08-11 15:55:09 +08:00
|
|
|
// Like 'load', but always requires 512-bit vector alignment.
|
|
|
|
|
def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
|
|
|
|
|
return cast<LoadSDNode>(N)->getAlignment() >= 64;
|
|
|
|
|
}]>;
|
|
|
|
|
|
2010-07-13 07:41:28 +08:00
|
|
|
def alignedloadfsf32 : PatFrag<(ops node:$ptr),
|
|
|
|
|
(f32 (alignedload node:$ptr))>;
|
|
|
|
|
def alignedloadfsf64 : PatFrag<(ops node:$ptr),
|
|
|
|
|
(f64 (alignedload node:$ptr))>;
|
2010-08-14 04:39:01 +08:00
|
|
|
|
|
|
|
|
// 128-bit aligned load pattern fragments
|
2012-01-24 11:03:17 +08:00
|
|
|
// NOTE: all 128-bit integer vector loads are promoted to v2i64
|
2010-07-13 07:41:28 +08:00
|
|
|
def alignedloadv4f32 : PatFrag<(ops node:$ptr),
|
|
|
|
|
(v4f32 (alignedload node:$ptr))>;
|
|
|
|
|
def alignedloadv2f64 : PatFrag<(ops node:$ptr),
|
|
|
|
|
(v2f64 (alignedload node:$ptr))>;
|
|
|
|
|
def alignedloadv2i64 : PatFrag<(ops node:$ptr),
|
|
|
|
|
(v2i64 (alignedload node:$ptr))>;
|
|
|
|
|
|
2010-08-14 04:39:01 +08:00
|
|
|
// 256-bit aligned load pattern fragments
|
2012-01-24 11:03:17 +08:00
|
|
|
// NOTE: all 256-bit integer vector loads are promoted to v4i64
|
2010-07-13 07:41:28 +08:00
|
|
|
def alignedloadv8f32 : PatFrag<(ops node:$ptr),
|
2011-09-14 03:33:03 +08:00
|
|
|
(v8f32 (alignedload256 node:$ptr))>;
|
2010-07-13 07:41:28 +08:00
|
|
|
def alignedloadv4f64 : PatFrag<(ops node:$ptr),
|
2011-09-14 03:33:03 +08:00
|
|
|
(v4f64 (alignedload256 node:$ptr))>;
|
2010-07-13 07:41:28 +08:00
|
|
|
def alignedloadv4i64 : PatFrag<(ops node:$ptr),
|
2011-09-14 03:33:03 +08:00
|
|
|
(v4i64 (alignedload256 node:$ptr))>;
|
2010-07-13 07:41:28 +08:00
|
|
|
|
2013-08-11 15:55:09 +08:00
|
|
|
// 512-bit aligned load pattern fragments
|
|
|
|
|
def alignedloadv16f32 : PatFrag<(ops node:$ptr),
|
|
|
|
|
(v16f32 (alignedload512 node:$ptr))>;
|
2013-08-18 21:08:57 +08:00
|
|
|
def alignedloadv16i32 : PatFrag<(ops node:$ptr),
|
|
|
|
|
(v16i32 (alignedload512 node:$ptr))>;
|
2013-08-11 15:55:09 +08:00
|
|
|
def alignedloadv8f64 : PatFrag<(ops node:$ptr),
|
|
|
|
|
(v8f64 (alignedload512 node:$ptr))>;
|
|
|
|
|
def alignedloadv8i64 : PatFrag<(ops node:$ptr),
|
|
|
|
|
(v8i64 (alignedload512 node:$ptr))>;
|
|
|
|
|
|
2010-07-13 07:41:28 +08:00
|
|
|
// Like 'load', but uses special alignment checks suitable for use in
|
|
|
|
|
// memory operands in most SSE instructions, which are required to
|
|
|
|
|
// be naturally aligned on some targets but not on others. If the subtarget
|
|
|
|
|
// allows unaligned accesses, match any load, though this may require
|
|
|
|
|
// setting a feature bit in the processor (on startup, for example).
|
|
|
|
|
// Opteron 10h and later implement such a feature.
|
|
|
|
|
def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
|
2015-02-04 01:13:04 +08:00
|
|
|
return Subtarget->hasSSEUnalignedMem()
|
2010-07-13 07:41:28 +08:00
|
|
|
|| cast<LoadSDNode>(N)->getAlignment() >= 16;
|
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
|
|
|
|
|
def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
|
2010-08-14 04:39:01 +08:00
|
|
|
|
|
|
|
|
// 128-bit memop pattern fragments
|
2012-01-24 11:03:17 +08:00
|
|
|
// NOTE: all 128-bit integer vector loads are promoted to v2i64
|
2010-07-13 07:41:28 +08:00
|
|
|
def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
|
|
|
|
|
def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
|
|
|
|
|
def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
|
|
|
|
|
|
2015-02-18 04:08:21 +08:00
|
|
|
// These are needed to match a scalar memop that is used in a vector-only
|
|
|
|
|
// math instruction such as the FP logical ops: andps, andnps, orps, xorps.
|
|
|
|
|
// The memory operand is required to be a 128-bit load, so it must be converted
|
|
|
|
|
// from a vector to a scalar.
|
|
|
|
|
def memopfsf32_128 : PatFrag<(ops node:$ptr),
|
|
|
|
|
(f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
|
|
|
|
|
def memopfsf64_128 : PatFrag<(ops node:$ptr),
|
|
|
|
|
(f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
|
|
|
|
|
|
|
|
|
|
|
2010-07-13 07:41:28 +08:00
|
|
|
// SSSE3 uses MMX registers for some instructions. They aren't aligned on a
|
|
|
|
|
// 16-byte boundary.
|
|
|
|
|
// FIXME: 8 byte alignment for mmx reads is not required
|
|
|
|
|
def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
|
|
|
|
|
return cast<LoadSDNode>(N)->getAlignment() >= 8;
|
|
|
|
|
}]>;
|
|
|
|
|
|
2010-10-01 07:57:10 +08:00
|
|
|
def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
|
2010-07-13 07:41:28 +08:00
|
|
|
|
|
|
|
|
// MOVNT Support
|
|
|
|
|
// Like 'store', but requires the non-temporal bit to be set
|
|
|
|
|
def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
|
|
|
|
|
(st node:$val, node:$ptr), [{
|
|
|
|
|
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
|
|
|
|
|
return ST->isNonTemporal();
|
|
|
|
|
return false;
|
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
|
2012-07-19 08:11:40 +08:00
|
|
|
(st node:$val, node:$ptr), [{
|
2010-07-13 07:41:28 +08:00
|
|
|
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
|
|
|
|
|
return ST->isNonTemporal() && !ST->isTruncatingStore() &&
|
|
|
|
|
ST->getAddressingMode() == ISD::UNINDEXED &&
|
|
|
|
|
ST->getAlignment() >= 16;
|
|
|
|
|
return false;
|
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
|
2012-07-19 08:11:40 +08:00
|
|
|
(st node:$val, node:$ptr), [{
|
2010-07-13 07:41:28 +08:00
|
|
|
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
|
|
|
|
|
return ST->isNonTemporal() &&
|
|
|
|
|
ST->getAlignment() < 16;
|
|
|
|
|
return false;
|
|
|
|
|
}]>;
|
|
|
|
|
|
2015-04-30 16:38:48 +08:00
|
|
|
def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
|
|
|
|
(masked_gather node:$src1, node:$src2, node:$src3) , [{
|
|
|
|
|
if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
|
|
|
|
|
return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
|
|
|
|
|
Mgt->getBasePtr().getValueType() == MVT::v8i32);
|
|
|
|
|
return false;
|
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
|
|
|
|
(masked_gather node:$src1, node:$src2, node:$src3) , [{
|
|
|
|
|
if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
|
|
|
|
|
return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
|
|
|
|
|
Mgt->getBasePtr().getValueType() == MVT::v8i64);
|
|
|
|
|
return false;
|
|
|
|
|
}]>;
|
|
|
|
|
def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
|
|
|
|
(masked_gather node:$src1, node:$src2, node:$src3) , [{
|
|
|
|
|
if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
|
|
|
|
|
return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
|
|
|
|
|
Mgt->getBasePtr().getValueType() == MVT::v16i32);
|
|
|
|
|
return false;
|
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
|
|
|
|
(masked_scatter node:$src1, node:$src2, node:$src3) , [{
|
|
|
|
|
if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
|
|
|
|
|
return (Sc->getIndex().getValueType() == MVT::v8i32 ||
|
|
|
|
|
Sc->getBasePtr().getValueType() == MVT::v8i32);
|
|
|
|
|
return false;
|
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
|
|
|
|
(masked_scatter node:$src1, node:$src2, node:$src3) , [{
|
|
|
|
|
if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
|
|
|
|
|
return (Sc->getIndex().getValueType() == MVT::v8i64 ||
|
|
|
|
|
Sc->getBasePtr().getValueType() == MVT::v8i64);
|
|
|
|
|
return false;
|
|
|
|
|
}]>;
|
|
|
|
|
def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
|
|
|
|
(masked_scatter node:$src1, node:$src2, node:$src3) , [{
|
|
|
|
|
if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
|
|
|
|
|
return (Sc->getIndex().getValueType() == MVT::v16i32 ||
|
|
|
|
|
Sc->getBasePtr().getValueType() == MVT::v16i32);
|
|
|
|
|
return false;
|
|
|
|
|
}]>;
|
|
|
|
|
|
2010-08-14 04:39:01 +08:00
|
|
|
// 128-bit bitconvert pattern fragments
|
2010-07-13 07:41:28 +08:00
|
|
|
def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
|
|
|
|
|
def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
|
|
|
|
|
def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
|
|
|
|
|
def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
|
|
|
|
|
def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
|
|
|
|
|
def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
|
|
|
|
|
|
2010-08-14 04:39:01 +08:00
|
|
|
// 256-bit bitconvert pattern fragments
|
2011-11-02 12:42:13 +08:00
|
|
|
def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
|
|
|
|
|
def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
|
2010-07-22 07:53:50 +08:00
|
|
|
def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
|
2011-07-13 09:15:33 +08:00
|
|
|
def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
|
2014-01-06 16:45:54 +08:00
|
|
|
def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
|
2010-07-22 07:53:50 +08:00
|
|
|
|
2013-08-16 14:07:34 +08:00
|
|
|
// 512-bit bitconvert pattern fragments
|
|
|
|
|
def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
|
|
|
|
|
def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
|
2014-01-01 23:12:34 +08:00
|
|
|
def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
|
|
|
|
|
def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
|
2013-08-16 14:07:34 +08:00
|
|
|
|
2010-07-13 07:41:28 +08:00
|
|
|
def vzmovl_v2i64 : PatFrag<(ops node:$src),
|
|
|
|
|
(bitconvert (v2i64 (X86vzmovl
|
|
|
|
|
(v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
|
|
|
|
|
def vzmovl_v4i32 : PatFrag<(ops node:$src),
|
|
|
|
|
(bitconvert (v4i32 (X86vzmovl
|
|
|
|
|
(v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
|
|
|
|
|
|
|
|
|
|
def vzload_v2i64 : PatFrag<(ops node:$src),
|
|
|
|
|
(bitconvert (v2i64 (X86vzload node:$src)))>;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
def fp32imm0 : PatLeaf<(f32 fpimm), [{
|
|
|
|
|
return N->isExactlyValue(+0.0);
|
|
|
|
|
}]>;
|
|
|
|
|
|
2014-01-01 23:12:34 +08:00
|
|
|
def I8Imm : SDNodeXForm<imm, [{
|
|
|
|
|
// Transformation function: get the low 8 bits.
|
2015-04-28 22:05:47 +08:00
|
|
|
return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
|
2014-01-01 23:12:34 +08:00
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
|
2014-08-15 01:13:26 +08:00
|
|
|
def FROUND_CURRENT : ImmLeaf<i32, [{
|
|
|
|
|
return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
|
|
|
|
|
}]>;
|
2014-01-01 23:12:34 +08:00
|
|
|
|
2010-07-13 07:41:28 +08:00
|
|
|
// BYTE_imm - Transform bit immediates into byte immediates.
|
|
|
|
|
def BYTE_imm : SDNodeXForm<imm, [{
|
|
|
|
|
// Transformation function: imm >> 3
|
2015-04-28 22:05:47 +08:00
|
|
|
return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
|
2010-07-13 07:41:28 +08:00
|
|
|
}]>;
|
|
|
|
|
|
2013-07-31 19:35:14 +08:00
|
|
|
// EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
|
|
|
|
|
// to VEXTRACTF128/VEXTRACTI128 imm.
|
|
|
|
|
def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
|
2015-04-28 22:05:47 +08:00
|
|
|
return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
|
2011-02-03 23:50:00 +08:00
|
|
|
}]>;
|
|
|
|
|
|
2013-07-31 19:35:14 +08:00
|
|
|
// INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
|
|
|
|
|
// VINSERTF128/VINSERTI128 imm.
|
|
|
|
|
def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
|
2015-04-28 22:05:47 +08:00
|
|
|
return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
|
2011-02-05 00:08:29 +08:00
|
|
|
}]>;
|
|
|
|
|
|
2013-07-31 19:35:14 +08:00
|
|
|
// EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
|
|
|
|
|
// to VEXTRACTF64x4 imm.
|
|
|
|
|
def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
|
2015-04-28 22:05:47 +08:00
|
|
|
return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
|
2013-07-31 19:35:14 +08:00
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
// INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
|
|
|
|
|
// VINSERTF64x4 imm.
|
|
|
|
|
def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
|
2015-04-28 22:05:47 +08:00
|
|
|
return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
|
2013-07-31 19:35:14 +08:00
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
|
|
|
|
|
(extract_subvector node:$bigvec,
|
|
|
|
|
node:$index), [{
|
|
|
|
|
return X86::isVEXTRACT128Index(N);
|
|
|
|
|
}], EXTRACT_get_vextract128_imm>;
|
|
|
|
|
|
|
|
|
|
def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
|
|
|
|
|
node:$index),
|
|
|
|
|
(insert_subvector node:$bigvec, node:$smallvec,
|
|
|
|
|
node:$index), [{
|
|
|
|
|
return X86::isVINSERT128Index(N);
|
|
|
|
|
}], INSERT_get_vinsert128_imm>;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
|
2011-02-03 23:50:00 +08:00
|
|
|
(extract_subvector node:$bigvec,
|
|
|
|
|
node:$index), [{
|
2013-07-31 19:35:14 +08:00
|
|
|
return X86::isVEXTRACT256Index(N);
|
|
|
|
|
}], EXTRACT_get_vextract256_imm>;
|
2011-02-05 00:08:29 +08:00
|
|
|
|
2013-07-31 19:35:14 +08:00
|
|
|
def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
|
2011-02-05 00:08:29 +08:00
|
|
|
node:$index),
|
|
|
|
|
(insert_subvector node:$bigvec, node:$smallvec,
|
|
|
|
|
node:$index), [{
|
2013-07-31 19:35:14 +08:00
|
|
|
return X86::isVINSERT256Index(N);
|
|
|
|
|
}], INSERT_get_vinsert256_imm>;
|
2011-07-26 07:05:25 +08:00
|
|
|
|
2015-03-03 23:03:35 +08:00
|
|
|
def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
|
|
|
|
(masked_load node:$src1, node:$src2, node:$src3), [{
|
2015-04-10 19:24:51 +08:00
|
|
|
if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
|
|
|
|
|
return Load->getAlignment() >= 16;
|
2015-03-03 23:03:35 +08:00
|
|
|
return false;
|
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
|
|
|
|
(masked_load node:$src1, node:$src2, node:$src3), [{
|
2015-04-10 19:24:51 +08:00
|
|
|
if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
|
|
|
|
|
return Load->getAlignment() >= 32;
|
2015-03-03 23:03:35 +08:00
|
|
|
return false;
|
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
|
|
|
|
(masked_load node:$src1, node:$src2, node:$src3), [{
|
2015-04-10 19:24:51 +08:00
|
|
|
if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
|
|
|
|
|
return Load->getAlignment() >= 64;
|
2015-03-03 23:03:35 +08:00
|
|
|
return false;
|
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
|
|
|
|
(masked_load node:$src1, node:$src2, node:$src3), [{
|
2015-04-10 19:24:51 +08:00
|
|
|
return isa<MaskedLoadSDNode>(N);
|
2015-03-03 23:03:35 +08:00
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
|
|
|
|
(masked_store node:$src1, node:$src2, node:$src3), [{
|
2015-04-10 19:24:51 +08:00
|
|
|
if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
|
|
|
|
|
return Store->getAlignment() >= 16;
|
2015-03-03 23:03:35 +08:00
|
|
|
return false;
|
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
|
|
|
|
(masked_store node:$src1, node:$src2, node:$src3), [{
|
2015-04-10 19:24:51 +08:00
|
|
|
if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
|
|
|
|
|
return Store->getAlignment() >= 32;
|
2015-03-03 23:03:35 +08:00
|
|
|
return false;
|
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
|
|
|
|
(masked_store node:$src1, node:$src2, node:$src3), [{
|
2015-04-10 19:24:51 +08:00
|
|
|
if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
|
|
|
|
|
return Store->getAlignment() >= 64;
|
2015-03-03 23:03:35 +08:00
|
|
|
return false;
|
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
|
|
|
|
(masked_store node:$src1, node:$src2, node:$src3), [{
|
2015-04-10 19:24:51 +08:00
|
|
|
return isa<MaskedStoreSDNode>(N);
|
2015-03-03 23:03:35 +08:00
|
|
|
}]>;
|
|
|
|
|
|