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llvm-project/llvm/test/CodeGen/ARM/fast-isel-pic.ll

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Change the fast-isel-abort option from bool to int to enable "levels" Summary: Currently fast-isel-abort will only abort for regular instructions, and just warn for function calls, terminators, function arguments. There is already fast-isel-abort-args but nothing for calls and terminators. This change turns the fast-isel-abort options into an integer option, so that multiple levels of strictness can be defined. This will help no being surprised when the "abort" option indeed does not abort, and enables the possibility to write test that verifies that no intrinsics are forgotten by fast-isel. Reviewers: resistor, echristo Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D7941 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 230775
2015-02-28 02:32:11 +08:00
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=arm-apple-ios | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARMv7
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s --check-prefix=THUMB-ELF
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=armv7-none-linux-gnueabi | FileCheck %s --check-prefix=ARMv7-ELF
[arm-fast-isel] Add support for ARM PIC. llvm-svn: 162823
2012-08-29 10:41:21 +08:00
@g = global i32 0, align 4
define i32 @LoadGV() {
entry:
; THUMB: LoadGV
; THUMB: movw [[reg0:r[0-9]+]],
; THUMB: movt [[reg0]],
; THUMB: add [[reg0]], pc
[arm-fast-isel] Add support for ELF PIC. This is a preliminary step towards ELF support; currently ARMFastISel hasn't been used for ELF object files yet. llvm-svn: 164759
2012-09-27 13:21:41 +08:00
; THUMB-ELF: LoadGV
This adds range checking for "ldr Rn, [pc, #imm]" Thumb instructions. With this patch: 1. ldr.n is recognized as mnemonic for the short encoding 2. ldr.w is recognized as menmonic for the long encoding 3. ldr will map to either short or long encodings depending on the size of the offset llvm-svn: 186831
2013-07-22 23:49:36 +08:00
; THUMB-ELF: ldr r[[reg0:[0-9]+]],
; THUMB-ELF: ldr r[[reg1:[0-9]+]],
Track IR ordering of SelectionDAG nodes 3/4. Remove the old IR ordering mechanism and switch to new one. Fix unit test failures. llvm-svn: 182704
2013-05-25 11:08:10 +08:00
; THUMB-ELF: ldr r[[reg0]], [r[[reg0]], r[[reg1]]]
[arm-fast-isel] Add support for ARM PIC. llvm-svn: 162823
2012-08-29 10:41:21 +08:00
; ARM: LoadGV
; ARM: ldr [[reg1:r[0-9]+]],
; ARM: add [[reg1]], pc, [[reg1]]
; ARMv7: LoadGV
; ARMv7: movw [[reg2:r[0-9]+]],
; ARMv7: movt [[reg2]],
; ARMv7: add [[reg2]], pc, [[reg2]]
[arm-fast-isel] Add support for ELF PIC. This is a preliminary step towards ELF support; currently ARMFastISel hasn't been used for ELF object files yet. llvm-svn: 164759
2012-09-27 13:21:41 +08:00
; ARMv7-ELF: LoadGV
; ARMv7-ELF: ldr r[[reg2:[0-9]+]],
When initializing the PIC global base register on ARM/ELF add pc to fix the address. This unbreaks PIC with fast isel on ELF targets (PR16717). The output matches what GCC and SDag do for PIC but may not cover all of the many flavors of PIC that exist. llvm-svn: 188551
2013-08-16 20:52:08 +08:00
; ARMv7-ELF: .LPC
; ARMv7-ELF-NEXT: add r[[reg2]], pc
[arm-fast-isel] Add support for ELF PIC. This is a preliminary step towards ELF support; currently ARMFastISel hasn't been used for ELF object files yet. llvm-svn: 164759
2012-09-27 13:21:41 +08:00
; ARMv7-ELF: ldr r[[reg3:[0-9]+]],
Enable FastISel on ARM for Linux and NaCl, not MCJIT This is a resubmit of r182877, which was reverted because it broken MCJIT tests on ARM. The patch leaves MCJIT on ARM as it was before: only enabled for iOS. I've CC'ed people from the original review and revert. FastISel was only enabled for iOS ARM and Thumb2, this patch enables it for ARM (not Thumb2) on Linux and NaCl, but not MCJIT. Thumb2 support needs a bit more work, mainly around register class restrictions. The patch punts to SelectionDAG when doing TLS relocation on non-Darwin targets. I will fix this and other FastISel-to-SelectionDAG failures in a separate patch. The patch also forces FastISel to retain frame pointers: iOS always keeps them for backtracking (so emitted code won't change because of this), but Linux was getting much worse code that was incorrect when using big frames (such as test-suite's lencod). I'll also fix this in a later patch, it will probably require a peephole so that FastISel doesn't rematerialize frame pointers back-to-back. The test changes are straightforward, similar to: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html They also add a vararg test that got dropped in that change. I ran all of lnt test-suite on A15 hardware with --optimize-option=-O0 and all the tests pass. All the tests also pass on x86 make check-all. I also re-ran the check-all tests that failed on ARM, and they all seem to pass. llvm-svn: 183966
2013-06-14 10:49:43 +08:00
; ARMv7-ELF: ldr r[[reg2]], [r[[reg3]], r[[reg2]]]
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp = load i32, i32* @g
[arm-fast-isel] Add support for ARM PIC. llvm-svn: 162823
2012-08-29 10:41:21 +08:00
ret i32 %tmp
}
@i = external global i32
define i32 @LoadIndirectSymbol() {
entry:
; THUMB: LoadIndirectSymbol
; THUMB: movw r[[reg3:[0-9]+]],
; THUMB: movt r[[reg3]],
; THUMB: add r[[reg3]], pc
; THUMB: ldr r[[reg3]], [r[[reg3]]]
[arm-fast-isel] Add support for ELF PIC. This is a preliminary step towards ELF support; currently ARMFastISel hasn't been used for ELF object files yet. llvm-svn: 164759
2012-09-27 13:21:41 +08:00
; THUMB-ELF: LoadIndirectSymbol
This adds range checking for "ldr Rn, [pc, #imm]" Thumb instructions. With this patch: 1. ldr.n is recognized as mnemonic for the short encoding 2. ldr.w is recognized as menmonic for the long encoding 3. ldr will map to either short or long encodings depending on the size of the offset llvm-svn: 186831
2013-07-22 23:49:36 +08:00
; THUMB-ELF: ldr r[[reg3:[0-9]+]],
; THUMB-ELF: ldr r[[reg4:[0-9]+]],
Track IR ordering of SelectionDAG nodes 3/4. Remove the old IR ordering mechanism and switch to new one. Fix unit test failures. llvm-svn: 182704
2013-05-25 11:08:10 +08:00
; THUMB-ELF: ldr r[[reg3]], [r[[reg3]], r[[reg4]]]
[arm-fast-isel] Add support for ARM PIC. llvm-svn: 162823
2012-08-29 10:41:21 +08:00
; ARM: LoadIndirectSymbol
; ARM: ldr [[reg4:r[0-9]+]],
; ARM: ldr [[reg4]], [pc, [[reg4]]]
; ARMv7: LoadIndirectSymbol
; ARMv7: movw r[[reg5:[0-9]+]],
; ARMv7: movt r[[reg5]],
; ARMv7: add r[[reg5]], pc, r[[reg5]]
; ARMv7: ldr r[[reg5]], [r[[reg5]]]
[arm-fast-isel] Add support for ELF PIC. This is a preliminary step towards ELF support; currently ARMFastISel hasn't been used for ELF object files yet. llvm-svn: 164759
2012-09-27 13:21:41 +08:00
; ARMv7-ELF: LoadIndirectSymbol
; ARMv7-ELF: ldr r[[reg5:[0-9]+]],
When initializing the PIC global base register on ARM/ELF add pc to fix the address. This unbreaks PIC with fast isel on ELF targets (PR16717). The output matches what GCC and SDag do for PIC but may not cover all of the many flavors of PIC that exist. llvm-svn: 188551
2013-08-16 20:52:08 +08:00
; ARMv7-ELF: .LPC
; ARMv7-ELF-NEXT: add r[[reg5]], pc
[arm-fast-isel] Add support for ELF PIC. This is a preliminary step towards ELF support; currently ARMFastISel hasn't been used for ELF object files yet. llvm-svn: 164759
2012-09-27 13:21:41 +08:00
; ARMv7-ELF: ldr r[[reg6:[0-9]+]],
Enable FastISel on ARM for Linux and NaCl, not MCJIT This is a resubmit of r182877, which was reverted because it broken MCJIT tests on ARM. The patch leaves MCJIT on ARM as it was before: only enabled for iOS. I've CC'ed people from the original review and revert. FastISel was only enabled for iOS ARM and Thumb2, this patch enables it for ARM (not Thumb2) on Linux and NaCl, but not MCJIT. Thumb2 support needs a bit more work, mainly around register class restrictions. The patch punts to SelectionDAG when doing TLS relocation on non-Darwin targets. I will fix this and other FastISel-to-SelectionDAG failures in a separate patch. The patch also forces FastISel to retain frame pointers: iOS always keeps them for backtracking (so emitted code won't change because of this), but Linux was getting much worse code that was incorrect when using big frames (such as test-suite's lencod). I'll also fix this in a later patch, it will probably require a peephole so that FastISel doesn't rematerialize frame pointers back-to-back. The test changes are straightforward, similar to: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html They also add a vararg test that got dropped in that change. I ran all of lnt test-suite on A15 hardware with --optimize-option=-O0 and all the tests pass. All the tests also pass on x86 make check-all. I also re-ran the check-all tests that failed on ARM, and they all seem to pass. llvm-svn: 183966
2013-06-14 10:49:43 +08:00
; ARMv7-ELF: ldr r[[reg5]], [r[[reg6]], r[[reg5]]]
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp = load i32, i32* @i
[arm-fast-isel] Add support for ARM PIC. llvm-svn: 162823
2012-08-29 10:41:21 +08:00
ret i32 %tmp
}