2013-05-07 00:15:19 +08:00
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//===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/SystemZMCTargetDesc.h"
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2013-07-24 15:33:14 +08:00
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#include "llvm/ADT/STLExtras.h"
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2013-05-14 17:47:26 +08:00
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#include "llvm/MC/MCContext.h"
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2013-05-07 00:15:19 +08:00
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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2016-08-08 23:13:08 +08:00
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#include "llvm/MC/MCInstBuilder.h"
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2013-05-07 00:15:19 +08:00
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#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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2016-01-27 18:01:28 +08:00
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#include "llvm/MC/MCParser/MCTargetAsmParser.h"
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2013-05-07 00:15:19 +08:00
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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// Return true if Expr is in the range [MinValue, MaxValue].
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static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
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2014-03-06 19:22:58 +08:00
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if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
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2013-05-07 00:15:19 +08:00
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int64_t Value = CE->getValue();
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return Value >= MinValue && Value <= MaxValue;
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}
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return false;
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}
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namespace {
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2013-07-02 22:56:45 +08:00
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enum RegisterKind {
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GR32Reg,
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GRH32Reg,
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GR64Reg,
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GR128Reg,
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ADDR32Reg,
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ADDR64Reg,
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FP32Reg,
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FP64Reg,
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2015-05-06 03:23:40 +08:00
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FP128Reg,
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VR32Reg,
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VR64Reg,
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VR128Reg
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2013-07-02 22:56:45 +08:00
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};
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enum MemoryKind {
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BDMem,
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BDXMem,
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BDLMem,
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BDVMem
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2013-07-02 22:56:45 +08:00
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};
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2013-05-07 00:15:19 +08:00
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class SystemZOperand : public MCParsedAsmOperand {
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public:
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private:
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enum OperandKind {
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KindInvalid,
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KindToken,
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KindReg,
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KindAccessReg,
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KindImm,
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KindImmTLS,
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2013-05-07 00:15:19 +08:00
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KindMem
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};
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OperandKind Kind;
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SMLoc StartLoc, EndLoc;
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// A string of length Length, starting at Data.
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struct TokenOp {
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const char *Data;
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unsigned Length;
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};
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2013-05-24 22:14:38 +08:00
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// LLVM register Num, which has kind Kind. In some ways it might be
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// easier for this class to have a register bank (general, floating-point
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// or access) and a raw register number (0-15). This would postpone the
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// interpretation of the operand to the add*() methods and avoid the need
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// for context-dependent parsing. However, we do things the current way
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// because of the virtual getReg() method, which needs to distinguish
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// between (say) %r0 used as a single register and %r0 used as a pair.
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// Context-dependent parsing can also give us slightly better error
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// messages when invalid pairs like %r1 are used.
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2013-05-07 00:15:19 +08:00
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struct RegOp {
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RegisterKind Kind;
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unsigned Num;
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};
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// Base + Disp + Index, where Base and Index are LLVM registers or 0.
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2015-05-05 01:40:53 +08:00
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// MemKind says what type of memory this is and RegKind says what type
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// the base register has (ADDR32Reg or ADDR64Reg). Length is the operand
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// length for D(L,B)-style operands, otherwise it is null.
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2013-05-07 00:15:19 +08:00
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struct MemOp {
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2015-05-06 03:23:40 +08:00
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unsigned Base : 12;
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unsigned Index : 12;
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unsigned MemKind : 4;
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unsigned RegKind : 4;
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2013-05-07 00:15:19 +08:00
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const MCExpr *Disp;
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const MCExpr *Length;
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2013-05-07 00:15:19 +08:00
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};
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2015-02-18 17:11:36 +08:00
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// Imm is an immediate operand, and Sym is an optional TLS symbol
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// for use with a __tls_get_offset marker relocation.
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struct ImmTLSOp {
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const MCExpr *Imm;
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const MCExpr *Sym;
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};
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2013-05-07 00:15:19 +08:00
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union {
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TokenOp Token;
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RegOp Reg;
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unsigned AccessReg;
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const MCExpr *Imm;
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2015-02-18 17:11:36 +08:00
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ImmTLSOp ImmTLS;
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2013-05-07 00:15:19 +08:00
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MemOp Mem;
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};
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void addExpr(MCInst &Inst, const MCExpr *Expr) const {
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// Add as immediates when possible. Null MCExpr = 0.
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2014-04-25 13:30:21 +08:00
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if (!Expr)
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2015-05-14 02:37:00 +08:00
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Inst.addOperand(MCOperand::createImm(0));
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2014-03-06 19:22:58 +08:00
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else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
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2015-05-14 02:37:00 +08:00
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Inst.addOperand(MCOperand::createImm(CE->getValue()));
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2013-05-07 00:15:19 +08:00
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else
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2015-05-14 02:37:00 +08:00
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Inst.addOperand(MCOperand::createExpr(Expr));
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2013-05-07 00:15:19 +08:00
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}
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public:
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2014-06-09 00:18:35 +08:00
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SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
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: Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
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2013-05-07 00:15:19 +08:00
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// Create particular kinds of operand.
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2014-06-09 00:18:35 +08:00
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static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
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SMLoc EndLoc) {
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return make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
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2013-05-24 22:26:46 +08:00
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}
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2014-06-09 00:18:35 +08:00
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static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
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auto Op = make_unique<SystemZOperand>(KindToken, Loc, Loc);
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2013-05-07 00:15:19 +08:00
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Op->Token.Data = Str.data();
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Op->Token.Length = Str.size();
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return Op;
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}
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2014-06-09 00:18:35 +08:00
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static std::unique_ptr<SystemZOperand>
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createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
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auto Op = make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
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2013-05-07 00:15:19 +08:00
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Op->Reg.Kind = Kind;
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Op->Reg.Num = Num;
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return Op;
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}
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2014-06-09 00:18:35 +08:00
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static std::unique_ptr<SystemZOperand>
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createAccessReg(unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
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auto Op = make_unique<SystemZOperand>(KindAccessReg, StartLoc, EndLoc);
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2013-05-07 00:15:19 +08:00
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Op->AccessReg = Num;
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return Op;
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}
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2014-06-09 00:18:35 +08:00
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static std::unique_ptr<SystemZOperand>
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createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
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auto Op = make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
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2013-05-07 00:15:19 +08:00
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Op->Imm = Expr;
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return Op;
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}
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2014-06-09 00:18:35 +08:00
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static std::unique_ptr<SystemZOperand>
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2015-05-05 01:40:53 +08:00
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createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
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const MCExpr *Disp, unsigned Index, const MCExpr *Length,
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SMLoc StartLoc, SMLoc EndLoc) {
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2014-06-09 00:18:35 +08:00
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auto Op = make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
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2015-05-05 01:40:53 +08:00
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Op->Mem.MemKind = MemKind;
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2013-05-07 00:15:19 +08:00
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Op->Mem.RegKind = RegKind;
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Op->Mem.Base = Base;
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Op->Mem.Index = Index;
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Op->Mem.Disp = Disp;
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2013-07-02 22:56:45 +08:00
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Op->Mem.Length = Length;
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2013-05-07 00:15:19 +08:00
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return Op;
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}
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2015-02-18 17:11:36 +08:00
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static std::unique_ptr<SystemZOperand>
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createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
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SMLoc StartLoc, SMLoc EndLoc) {
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auto Op = make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
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Op->ImmTLS.Imm = Imm;
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Op->ImmTLS.Sym = Sym;
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return Op;
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}
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2013-05-07 00:15:19 +08:00
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// Token operands
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2014-03-06 20:03:36 +08:00
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bool isToken() const override {
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2013-05-07 00:15:19 +08:00
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return Kind == KindToken;
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}
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StringRef getToken() const {
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assert(Kind == KindToken && "Not a token");
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return StringRef(Token.Data, Token.Length);
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}
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// Register operands.
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2014-03-06 20:03:36 +08:00
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bool isReg() const override {
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2013-05-07 00:15:19 +08:00
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return Kind == KindReg;
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}
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bool isReg(RegisterKind RegKind) const {
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return Kind == KindReg && Reg.Kind == RegKind;
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}
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2014-03-06 20:03:36 +08:00
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unsigned getReg() const override {
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2013-05-07 00:15:19 +08:00
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assert(Kind == KindReg && "Not a register");
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return Reg.Num;
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}
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// Access register operands. Access registers aren't exposed to LLVM
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// as registers.
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bool isAccessReg() const {
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return Kind == KindAccessReg;
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}
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// Immediate operands.
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2014-03-06 20:03:36 +08:00
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bool isImm() const override {
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2013-05-07 00:15:19 +08:00
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return Kind == KindImm;
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}
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bool isImm(int64_t MinValue, int64_t MaxValue) const {
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return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
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}
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const MCExpr *getImm() const {
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assert(Kind == KindImm && "Not an immediate");
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return Imm;
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}
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2015-02-18 17:11:36 +08:00
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// Immediate operands with optional TLS symbol.
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bool isImmTLS() const {
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return Kind == KindImmTLS;
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}
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2013-05-07 00:15:19 +08:00
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// Memory operands.
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2014-03-06 20:03:36 +08:00
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bool isMem() const override {
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2013-05-07 00:15:19 +08:00
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return Kind == KindMem;
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}
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2015-05-05 01:40:53 +08:00
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bool isMem(MemoryKind MemKind) const {
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2013-05-07 00:15:19 +08:00
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return (Kind == KindMem &&
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2015-05-05 01:40:53 +08:00
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(Mem.MemKind == MemKind ||
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// A BDMem can be treated as a BDXMem in which the index
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// register field is 0.
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(Mem.MemKind == BDMem && MemKind == BDXMem)));
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2013-05-07 00:15:19 +08:00
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}
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2015-05-05 01:40:53 +08:00
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bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
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return isMem(MemKind) && Mem.RegKind == RegKind;
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2013-05-07 00:15:19 +08:00
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}
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2015-05-05 01:40:53 +08:00
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bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
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return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
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}
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bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
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return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
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2013-07-02 22:56:45 +08:00
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}
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bool isMemDisp12Len8(RegisterKind RegKind) const {
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2015-05-05 01:40:53 +08:00
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return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length, 1, 0x100);
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2013-05-07 00:15:19 +08:00
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}
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2015-05-06 03:23:40 +08:00
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void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
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assert(N == 3 && "Invalid number of operands");
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assert(isMem(BDVMem) && "Invalid operand type");
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2015-05-14 02:37:00 +08:00
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Inst.addOperand(MCOperand::createReg(Mem.Base));
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2015-05-06 03:23:40 +08:00
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addExpr(Inst, Mem.Disp);
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2015-05-14 02:37:00 +08:00
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Inst.addOperand(MCOperand::createReg(Mem.Index));
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2015-05-06 03:23:40 +08:00
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}
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2013-05-07 00:15:19 +08:00
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// Override MCParsedAsmOperand.
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2014-03-06 20:03:36 +08:00
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SMLoc getStartLoc() const override { return StartLoc; }
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SMLoc getEndLoc() const override { return EndLoc; }
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void print(raw_ostream &OS) const override;
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2013-05-07 00:15:19 +08:00
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// Used by the TableGen code to add particular types of operand
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// to an instruction.
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void addRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands");
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2015-05-14 02:37:00 +08:00
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Inst.addOperand(MCOperand::createReg(getReg()));
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2013-05-07 00:15:19 +08:00
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}
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void addAccessRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands");
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assert(Kind == KindAccessReg && "Invalid operand type");
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2015-05-14 02:37:00 +08:00
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Inst.addOperand(MCOperand::createImm(AccessReg));
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2013-05-07 00:15:19 +08:00
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}
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void addImmOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands");
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addExpr(Inst, getImm());
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}
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void addBDAddrOperands(MCInst &Inst, unsigned N) const {
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assert(N == 2 && "Invalid number of operands");
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2015-05-05 01:40:53 +08:00
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assert(isMem(BDMem) && "Invalid operand type");
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2015-05-14 02:37:00 +08:00
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Inst.addOperand(MCOperand::createReg(Mem.Base));
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2013-05-07 00:15:19 +08:00
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addExpr(Inst, Mem.Disp);
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}
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void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
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assert(N == 3 && "Invalid number of operands");
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2015-05-05 01:40:53 +08:00
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assert(isMem(BDXMem) && "Invalid operand type");
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2015-05-14 02:37:00 +08:00
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Inst.addOperand(MCOperand::createReg(Mem.Base));
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2013-05-07 00:15:19 +08:00
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addExpr(Inst, Mem.Disp);
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2015-05-14 02:37:00 +08:00
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|
Inst.addOperand(MCOperand::createReg(Mem.Index));
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
2013-07-02 22:56:45 +08:00
|
|
|
void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
|
|
|
|
assert(N == 3 && "Invalid number of operands");
|
2015-05-05 01:40:53 +08:00
|
|
|
assert(isMem(BDLMem) && "Invalid operand type");
|
2015-05-14 02:37:00 +08:00
|
|
|
Inst.addOperand(MCOperand::createReg(Mem.Base));
|
2013-07-02 22:56:45 +08:00
|
|
|
addExpr(Inst, Mem.Disp);
|
|
|
|
addExpr(Inst, Mem.Length);
|
|
|
|
}
|
2015-02-18 17:11:36 +08:00
|
|
|
void addImmTLSOperands(MCInst &Inst, unsigned N) const {
|
|
|
|
assert(N == 2 && "Invalid number of operands");
|
|
|
|
assert(Kind == KindImmTLS && "Invalid operand type");
|
|
|
|
addExpr(Inst, ImmTLS.Imm);
|
|
|
|
if (ImmTLS.Sym)
|
|
|
|
addExpr(Inst, ImmTLS.Sym);
|
|
|
|
}
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
// Used by the TableGen code to check for particular operand types.
|
|
|
|
bool isGR32() const { return isReg(GR32Reg); }
|
2013-09-30 18:45:16 +08:00
|
|
|
bool isGRH32() const { return isReg(GRH32Reg); }
|
2013-10-01 19:26:28 +08:00
|
|
|
bool isGRX32() const { return false; }
|
2013-05-07 00:15:19 +08:00
|
|
|
bool isGR64() const { return isReg(GR64Reg); }
|
|
|
|
bool isGR128() const { return isReg(GR128Reg); }
|
|
|
|
bool isADDR32() const { return isReg(ADDR32Reg); }
|
|
|
|
bool isADDR64() const { return isReg(ADDR64Reg); }
|
|
|
|
bool isADDR128() const { return false; }
|
|
|
|
bool isFP32() const { return isReg(FP32Reg); }
|
|
|
|
bool isFP64() const { return isReg(FP64Reg); }
|
|
|
|
bool isFP128() const { return isReg(FP128Reg); }
|
2015-05-06 03:23:40 +08:00
|
|
|
bool isVR32() const { return isReg(VR32Reg); }
|
|
|
|
bool isVR64() const { return isReg(VR64Reg); }
|
|
|
|
bool isVF128() const { return false; }
|
|
|
|
bool isVR128() const { return isReg(VR128Reg); }
|
2016-08-08 23:13:08 +08:00
|
|
|
bool isAnyReg() const { return (isReg() || isImm(0, 15)); }
|
2015-05-05 01:40:53 +08:00
|
|
|
bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); }
|
|
|
|
bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); }
|
|
|
|
bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, ADDR64Reg); }
|
|
|
|
bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, ADDR64Reg); }
|
|
|
|
bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, ADDR64Reg); }
|
|
|
|
bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, ADDR64Reg); }
|
2013-07-02 22:56:45 +08:00
|
|
|
bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
|
2015-05-06 03:23:40 +08:00
|
|
|
bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, ADDR64Reg); }
|
|
|
|
bool isU1Imm() const { return isImm(0, 1); }
|
|
|
|
bool isU2Imm() const { return isImm(0, 3); }
|
|
|
|
bool isU3Imm() const { return isImm(0, 7); }
|
2013-05-07 00:15:19 +08:00
|
|
|
bool isU4Imm() const { return isImm(0, 15); }
|
|
|
|
bool isU6Imm() const { return isImm(0, 63); }
|
|
|
|
bool isU8Imm() const { return isImm(0, 255); }
|
|
|
|
bool isS8Imm() const { return isImm(-128, 127); }
|
2015-05-06 03:23:40 +08:00
|
|
|
bool isU12Imm() const { return isImm(0, 4095); }
|
2013-05-07 00:15:19 +08:00
|
|
|
bool isU16Imm() const { return isImm(0, 65535); }
|
|
|
|
bool isS16Imm() const { return isImm(-32768, 32767); }
|
|
|
|
bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
|
|
|
|
bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
|
2016-08-08 23:13:08 +08:00
|
|
|
bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
|
2013-05-07 00:15:19 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
class SystemZAsmParser : public MCTargetAsmParser {
|
|
|
|
#define GET_ASSEMBLER_HEADER
|
|
|
|
#include "SystemZGenAsmMatcher.inc"
|
|
|
|
|
|
|
|
private:
|
|
|
|
MCAsmParser &Parser;
|
2013-05-24 22:14:38 +08:00
|
|
|
enum RegisterGroup {
|
|
|
|
RegGR,
|
|
|
|
RegFP,
|
2015-05-06 03:23:40 +08:00
|
|
|
RegV,
|
2013-05-24 22:14:38 +08:00
|
|
|
RegAccess
|
|
|
|
};
|
2013-05-07 00:15:19 +08:00
|
|
|
struct Register {
|
2013-05-24 22:14:38 +08:00
|
|
|
RegisterGroup Group;
|
|
|
|
unsigned Num;
|
2013-05-07 00:15:19 +08:00
|
|
|
SMLoc StartLoc, EndLoc;
|
|
|
|
};
|
|
|
|
|
|
|
|
bool parseRegister(Register &Reg);
|
|
|
|
|
2013-05-24 22:26:46 +08:00
|
|
|
bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
|
|
|
|
bool IsAddress = false);
|
2013-05-07 00:15:19 +08:00
|
|
|
|
2014-06-09 00:18:35 +08:00
|
|
|
OperandMatchResultTy parseRegister(OperandVector &Operands,
|
|
|
|
RegisterGroup Group, const unsigned *Regs,
|
|
|
|
RegisterKind Kind);
|
2013-05-07 00:15:19 +08:00
|
|
|
|
2016-08-08 23:13:08 +08:00
|
|
|
OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
|
|
|
|
|
2013-05-24 22:26:46 +08:00
|
|
|
bool parseAddress(unsigned &Base, const MCExpr *&Disp,
|
2015-05-06 03:23:40 +08:00
|
|
|
unsigned &Index, bool &IsVector, const MCExpr *&Length,
|
2013-07-02 22:56:45 +08:00
|
|
|
const unsigned *Regs, RegisterKind RegKind);
|
2013-05-24 22:26:46 +08:00
|
|
|
|
2016-08-08 23:13:08 +08:00
|
|
|
bool ParseDirectiveInsn(SMLoc L);
|
|
|
|
|
2014-06-09 00:18:35 +08:00
|
|
|
OperandMatchResultTy parseAddress(OperandVector &Operands,
|
2015-05-05 01:40:53 +08:00
|
|
|
MemoryKind MemKind, const unsigned *Regs,
|
|
|
|
RegisterKind RegKind);
|
2013-05-07 00:15:19 +08:00
|
|
|
|
2015-02-18 17:11:36 +08:00
|
|
|
OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
|
|
|
|
int64_t MaxVal, bool AllowTLS);
|
|
|
|
|
2014-06-09 00:18:35 +08:00
|
|
|
bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
public:
|
2015-11-14 14:35:56 +08:00
|
|
|
SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
|
2014-04-23 19:16:03 +08:00
|
|
|
const MCInstrInfo &MII,
|
|
|
|
const MCTargetOptions &Options)
|
2015-11-14 13:20:05 +08:00
|
|
|
: MCTargetAsmParser(Options, sti), Parser(parser) {
|
2013-05-07 00:15:19 +08:00
|
|
|
MCAsmParserExtension::Initialize(Parser);
|
|
|
|
|
2016-07-09 00:50:02 +08:00
|
|
|
// Alias the .word directive to .short.
|
|
|
|
parser.addAliasForDirective(".word", ".short");
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
// Initialize the set of available features.
|
2015-11-14 13:20:05 +08:00
|
|
|
setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Override MCTargetAsmParser.
|
2014-03-06 20:03:36 +08:00
|
|
|
bool ParseDirective(AsmToken DirectiveID) override;
|
|
|
|
bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
|
2014-06-09 00:18:35 +08:00
|
|
|
bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
|
|
|
|
SMLoc NameLoc, OperandVector &Operands) override;
|
2014-03-06 20:03:36 +08:00
|
|
|
bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
|
2014-06-09 00:18:35 +08:00
|
|
|
OperandVector &Operands, MCStreamer &Out,
|
2014-08-18 19:49:42 +08:00
|
|
|
uint64_t &ErrorInfo,
|
2014-03-06 20:03:36 +08:00
|
|
|
bool MatchingInlineAsm) override;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
// Used by the TableGen code to parse particular operand types.
|
2014-06-09 00:18:35 +08:00
|
|
|
OperandMatchResultTy parseGR32(OperandVector &Operands) {
|
2013-07-02 22:56:45 +08:00
|
|
|
return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
2014-06-09 00:18:35 +08:00
|
|
|
OperandMatchResultTy parseGRH32(OperandVector &Operands) {
|
2013-09-30 18:45:16 +08:00
|
|
|
return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg);
|
|
|
|
}
|
2014-06-09 00:18:35 +08:00
|
|
|
OperandMatchResultTy parseGRX32(OperandVector &Operands) {
|
2013-10-01 19:26:28 +08:00
|
|
|
llvm_unreachable("GRX32 should only be used for pseudo instructions");
|
|
|
|
}
|
2014-06-09 00:18:35 +08:00
|
|
|
OperandMatchResultTy parseGR64(OperandVector &Operands) {
|
2013-07-02 22:56:45 +08:00
|
|
|
return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
2014-06-09 00:18:35 +08:00
|
|
|
OperandMatchResultTy parseGR128(OperandVector &Operands) {
|
2013-07-02 22:56:45 +08:00
|
|
|
return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
2014-06-09 00:18:35 +08:00
|
|
|
OperandMatchResultTy parseADDR32(OperandVector &Operands) {
|
2013-07-02 22:56:45 +08:00
|
|
|
return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
2014-06-09 00:18:35 +08:00
|
|
|
OperandMatchResultTy parseADDR64(OperandVector &Operands) {
|
2013-07-02 22:56:45 +08:00
|
|
|
return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
2014-06-09 00:18:35 +08:00
|
|
|
OperandMatchResultTy parseADDR128(OperandVector &Operands) {
|
2013-05-07 00:15:19 +08:00
|
|
|
llvm_unreachable("Shouldn't be used as an operand");
|
|
|
|
}
|
2014-06-09 00:18:35 +08:00
|
|
|
OperandMatchResultTy parseFP32(OperandVector &Operands) {
|
2013-07-02 22:56:45 +08:00
|
|
|
return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
2014-06-09 00:18:35 +08:00
|
|
|
OperandMatchResultTy parseFP64(OperandVector &Operands) {
|
2013-07-02 22:56:45 +08:00
|
|
|
return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
2014-06-09 00:18:35 +08:00
|
|
|
OperandMatchResultTy parseFP128(OperandVector &Operands) {
|
2013-07-02 22:56:45 +08:00
|
|
|
return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
2015-05-06 03:23:40 +08:00
|
|
|
OperandMatchResultTy parseVR32(OperandVector &Operands) {
|
|
|
|
return parseRegister(Operands, RegV, SystemZMC::VR32Regs, VR32Reg);
|
|
|
|
}
|
|
|
|
OperandMatchResultTy parseVR64(OperandVector &Operands) {
|
|
|
|
return parseRegister(Operands, RegV, SystemZMC::VR64Regs, VR64Reg);
|
|
|
|
}
|
|
|
|
OperandMatchResultTy parseVF128(OperandVector &Operands) {
|
|
|
|
llvm_unreachable("Shouldn't be used as an operand");
|
|
|
|
}
|
|
|
|
OperandMatchResultTy parseVR128(OperandVector &Operands) {
|
|
|
|
return parseRegister(Operands, RegV, SystemZMC::VR128Regs, VR128Reg);
|
|
|
|
}
|
2016-08-08 23:13:08 +08:00
|
|
|
OperandMatchResultTy parseAnyReg(OperandVector &Operands) {
|
|
|
|
return parseAnyRegister(Operands);
|
|
|
|
}
|
2014-06-09 00:18:35 +08:00
|
|
|
OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
|
2015-05-05 01:40:53 +08:00
|
|
|
return parseAddress(Operands, BDMem, SystemZMC::GR32Regs, ADDR32Reg);
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
2014-06-09 00:18:35 +08:00
|
|
|
OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
|
2015-05-05 01:40:53 +08:00
|
|
|
return parseAddress(Operands, BDMem, SystemZMC::GR64Regs, ADDR64Reg);
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
2014-06-09 00:18:35 +08:00
|
|
|
OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
|
2015-05-05 01:40:53 +08:00
|
|
|
return parseAddress(Operands, BDXMem, SystemZMC::GR64Regs, ADDR64Reg);
|
2013-07-02 22:56:45 +08:00
|
|
|
}
|
2014-06-09 00:18:35 +08:00
|
|
|
OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
|
2015-05-05 01:40:53 +08:00
|
|
|
return parseAddress(Operands, BDLMem, SystemZMC::GR64Regs, ADDR64Reg);
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
2015-05-06 03:23:40 +08:00
|
|
|
OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
|
|
|
|
return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, ADDR64Reg);
|
|
|
|
}
|
2014-06-09 00:18:35 +08:00
|
|
|
OperandMatchResultTy parseAccessReg(OperandVector &Operands);
|
|
|
|
OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
|
2015-02-18 17:11:36 +08:00
|
|
|
return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
|
2013-05-14 17:47:26 +08:00
|
|
|
}
|
2014-06-09 00:18:35 +08:00
|
|
|
OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
|
2015-02-18 17:11:36 +08:00
|
|
|
return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
|
|
|
|
}
|
|
|
|
OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
|
|
|
|
return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
|
|
|
|
}
|
|
|
|
OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
|
|
|
|
return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
|
2013-05-14 17:47:26 +08:00
|
|
|
}
|
2013-05-07 00:15:19 +08:00
|
|
|
};
|
2014-03-06 18:38:30 +08:00
|
|
|
} // end anonymous namespace
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
#define GET_REGISTER_MATCHER
|
|
|
|
#define GET_SUBTARGET_FEATURE_NAME
|
|
|
|
#define GET_MATCHER_IMPLEMENTATION
|
|
|
|
#include "SystemZGenAsmMatcher.inc"
|
|
|
|
|
2016-08-08 23:13:08 +08:00
|
|
|
// Used for the .insn directives; contains information needed to parse the
|
|
|
|
// operands in the directive.
|
|
|
|
struct InsnMatchEntry {
|
|
|
|
StringRef Format;
|
|
|
|
uint64_t Opcode;
|
|
|
|
int32_t NumOperands;
|
|
|
|
MatchClassKind OperandKinds[5];
|
|
|
|
};
|
|
|
|
|
|
|
|
// For equal_range comparison.
|
|
|
|
struct CompareInsn {
|
|
|
|
bool operator() (const InsnMatchEntry &LHS, StringRef RHS) {
|
|
|
|
return LHS.Format < RHS;
|
|
|
|
}
|
|
|
|
bool operator() (StringRef LHS, const InsnMatchEntry &RHS) {
|
|
|
|
return LHS < RHS.Format;
|
|
|
|
}
|
2016-08-11 00:39:58 +08:00
|
|
|
bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
|
|
|
|
return LHS.Format < RHS.Format;
|
|
|
|
}
|
2016-08-08 23:13:08 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
// Table initializing information for parsing the .insn directive.
|
|
|
|
static struct InsnMatchEntry InsnMatchTable[] = {
|
|
|
|
/* Format, Opcode, NumOperands, OperandKinds */
|
|
|
|
{ "e", SystemZ::InsnE, 1,
|
|
|
|
{ MCK_U16Imm } },
|
|
|
|
{ "ri", SystemZ::InsnRI, 3,
|
|
|
|
{ MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
|
|
|
|
{ "rie", SystemZ::InsnRIE, 4,
|
|
|
|
{ MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
|
|
|
|
{ "ril", SystemZ::InsnRIL, 3,
|
|
|
|
{ MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
|
|
|
|
{ "rilu", SystemZ::InsnRILU, 3,
|
|
|
|
{ MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
|
|
|
|
{ "ris", SystemZ::InsnRIS, 5,
|
|
|
|
{ MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
|
|
|
|
{ "rr", SystemZ::InsnRR, 3,
|
|
|
|
{ MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
|
|
|
|
{ "rre", SystemZ::InsnRRE, 3,
|
|
|
|
{ MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
|
|
|
|
{ "rrf", SystemZ::InsnRRF, 5,
|
|
|
|
{ MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
|
|
|
|
{ "rrs", SystemZ::InsnRRS, 5,
|
|
|
|
{ MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
|
|
|
|
{ "rs", SystemZ::InsnRS, 4,
|
|
|
|
{ MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
|
|
|
|
{ "rse", SystemZ::InsnRSE, 4,
|
|
|
|
{ MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
|
|
|
|
{ "rsi", SystemZ::InsnRSI, 4,
|
|
|
|
{ MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
|
|
|
|
{ "rsy", SystemZ::InsnRSY, 4,
|
|
|
|
{ MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
|
|
|
|
{ "rx", SystemZ::InsnRX, 3,
|
|
|
|
{ MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
|
|
|
|
{ "rxe", SystemZ::InsnRXE, 3,
|
|
|
|
{ MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
|
|
|
|
{ "rxf", SystemZ::InsnRXF, 4,
|
|
|
|
{ MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
|
|
|
|
{ "rxy", SystemZ::InsnRXY, 3,
|
|
|
|
{ MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
|
|
|
|
{ "s", SystemZ::InsnS, 2,
|
|
|
|
{ MCK_U32Imm, MCK_BDAddr64Disp12 } },
|
|
|
|
{ "si", SystemZ::InsnSI, 3,
|
|
|
|
{ MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
|
|
|
|
{ "sil", SystemZ::InsnSIL, 3,
|
|
|
|
{ MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
|
|
|
|
{ "siy", SystemZ::InsnSIY, 3,
|
|
|
|
{ MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
|
|
|
|
{ "ss", SystemZ::InsnSS, 4,
|
|
|
|
{ MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
|
|
|
|
{ "sse", SystemZ::InsnSSE, 3,
|
|
|
|
{ MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
|
|
|
|
{ "ssf", SystemZ::InsnSSF, 4,
|
|
|
|
{ MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } }
|
|
|
|
};
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
void SystemZOperand::print(raw_ostream &OS) const {
|
|
|
|
llvm_unreachable("Not implemented");
|
|
|
|
}
|
|
|
|
|
|
|
|
// Parse one register of the form %<prefix><number>.
|
|
|
|
bool SystemZAsmParser::parseRegister(Register &Reg) {
|
|
|
|
Reg.StartLoc = Parser.getTok().getLoc();
|
|
|
|
|
|
|
|
// Eat the % prefix.
|
|
|
|
if (Parser.getTok().isNot(AsmToken::Percent))
|
2013-05-24 22:26:46 +08:00
|
|
|
return Error(Parser.getTok().getLoc(), "register expected");
|
2013-05-07 00:15:19 +08:00
|
|
|
Parser.Lex();
|
|
|
|
|
|
|
|
// Expect a register name.
|
|
|
|
if (Parser.getTok().isNot(AsmToken::Identifier))
|
2013-05-24 22:26:46 +08:00
|
|
|
return Error(Reg.StartLoc, "invalid register");
|
2013-05-07 00:15:19 +08:00
|
|
|
|
2013-05-24 22:14:38 +08:00
|
|
|
// Check that there's a prefix.
|
2013-05-07 00:15:19 +08:00
|
|
|
StringRef Name = Parser.getTok().getString();
|
|
|
|
if (Name.size() < 2)
|
2013-05-24 22:26:46 +08:00
|
|
|
return Error(Reg.StartLoc, "invalid register");
|
2013-05-24 22:14:38 +08:00
|
|
|
char Prefix = Name[0];
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
// Treat the rest of the register name as a register number.
|
2013-05-24 22:14:38 +08:00
|
|
|
if (Name.substr(1).getAsInteger(10, Reg.Num))
|
2013-05-24 22:26:46 +08:00
|
|
|
return Error(Reg.StartLoc, "invalid register");
|
2013-05-24 22:14:38 +08:00
|
|
|
|
|
|
|
// Look for valid combinations of prefix and number.
|
|
|
|
if (Prefix == 'r' && Reg.Num < 16)
|
|
|
|
Reg.Group = RegGR;
|
|
|
|
else if (Prefix == 'f' && Reg.Num < 16)
|
|
|
|
Reg.Group = RegFP;
|
2015-05-06 03:23:40 +08:00
|
|
|
else if (Prefix == 'v' && Reg.Num < 32)
|
|
|
|
Reg.Group = RegV;
|
2013-05-24 22:14:38 +08:00
|
|
|
else if (Prefix == 'a' && Reg.Num < 16)
|
|
|
|
Reg.Group = RegAccess;
|
|
|
|
else
|
2013-05-24 22:26:46 +08:00
|
|
|
return Error(Reg.StartLoc, "invalid register");
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
Reg.EndLoc = Parser.getTok().getLoc();
|
|
|
|
Parser.Lex();
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2013-05-24 22:14:38 +08:00
|
|
|
// Parse a register of group Group. If Regs is nonnull, use it to map
|
2015-10-09 15:19:12 +08:00
|
|
|
// the raw register number to LLVM numbering, with zero entries
|
|
|
|
// indicating an invalid register. IsAddress says whether the
|
|
|
|
// register appears in an address context. Allow FP Group if expecting
|
|
|
|
// RegV Group, since the f-prefix yields the FP group even while used
|
|
|
|
// with vector instructions.
|
2013-05-24 22:26:46 +08:00
|
|
|
bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
|
|
|
|
const unsigned *Regs, bool IsAddress) {
|
|
|
|
if (parseRegister(Reg))
|
|
|
|
return true;
|
2015-10-09 15:19:12 +08:00
|
|
|
if (Reg.Group != Group && !(Reg.Group == RegFP && Group == RegV))
|
2013-05-24 22:26:46 +08:00
|
|
|
return Error(Reg.StartLoc, "invalid operand for instruction");
|
|
|
|
if (Regs && Regs[Reg.Num] == 0)
|
|
|
|
return Error(Reg.StartLoc, "invalid register pair");
|
|
|
|
if (Reg.Num == 0 && IsAddress)
|
|
|
|
return Error(Reg.StartLoc, "%r0 used in an address");
|
2013-05-24 22:14:38 +08:00
|
|
|
if (Regs)
|
|
|
|
Reg.Num = Regs[Reg.Num];
|
2013-05-24 22:26:46 +08:00
|
|
|
return false;
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
2013-05-24 22:14:38 +08:00
|
|
|
// Parse a register and add it to Operands. The other arguments are as above.
|
2013-05-07 00:15:19 +08:00
|
|
|
SystemZAsmParser::OperandMatchResultTy
|
2014-06-09 00:18:35 +08:00
|
|
|
SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group,
|
|
|
|
const unsigned *Regs, RegisterKind Kind) {
|
2013-05-24 22:26:46 +08:00
|
|
|
if (Parser.getTok().isNot(AsmToken::Percent))
|
|
|
|
return MatchOperand_NoMatch;
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
Register Reg;
|
2013-07-02 22:56:45 +08:00
|
|
|
bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
|
2013-05-24 22:26:46 +08:00
|
|
|
if (parseRegister(Reg, Group, Regs, IsAddress))
|
|
|
|
return MatchOperand_ParseFail;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
2013-05-24 22:26:46 +08:00
|
|
|
Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
|
|
|
|
Reg.StartLoc, Reg.EndLoc));
|
|
|
|
return MatchOperand_Success;
|
|
|
|
}
|
2013-05-07 00:15:19 +08:00
|
|
|
|
2016-08-08 23:13:08 +08:00
|
|
|
// Parse any type of register (including integers) and add it to Operands.
|
|
|
|
SystemZAsmParser::OperandMatchResultTy
|
|
|
|
SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
|
|
|
|
// Handle integer values.
|
|
|
|
if (Parser.getTok().is(AsmToken::Integer)) {
|
|
|
|
const MCExpr *Register;
|
|
|
|
SMLoc StartLoc = Parser.getTok().getLoc();
|
|
|
|
if (Parser.parseExpression(Register))
|
|
|
|
return MatchOperand_ParseFail;
|
|
|
|
|
|
|
|
if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
|
|
|
|
int64_t Value = CE->getValue();
|
|
|
|
if (Value < 0 || Value > 15) {
|
|
|
|
Error(StartLoc, "invalid register");
|
|
|
|
return MatchOperand_ParseFail;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
SMLoc EndLoc =
|
|
|
|
SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
|
|
|
|
|
|
|
|
Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
Register Reg;
|
|
|
|
if (parseRegister(Reg))
|
|
|
|
return MatchOperand_ParseFail;
|
|
|
|
|
|
|
|
// Map to the correct register kind.
|
|
|
|
RegisterKind Kind;
|
|
|
|
unsigned RegNo;
|
|
|
|
if (Reg.Group == RegGR) {
|
|
|
|
Kind = GR64Reg;
|
|
|
|
RegNo = SystemZMC::GR64Regs[Reg.Num];
|
|
|
|
}
|
|
|
|
else if (Reg.Group == RegFP) {
|
|
|
|
Kind = FP64Reg;
|
|
|
|
RegNo = SystemZMC::FP64Regs[Reg.Num];
|
|
|
|
}
|
|
|
|
else if (Reg.Group == RegV) {
|
|
|
|
Kind = VR128Reg;
|
|
|
|
RegNo = SystemZMC::VR128Regs[Reg.Num];
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
return MatchOperand_ParseFail;
|
|
|
|
}
|
|
|
|
|
|
|
|
Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
|
|
|
|
Reg.StartLoc, Reg.EndLoc));
|
|
|
|
}
|
|
|
|
return MatchOperand_Success;
|
|
|
|
}
|
|
|
|
|
2013-07-02 22:56:45 +08:00
|
|
|
// Parse a memory operand into Base, Disp, Index and Length.
|
|
|
|
// Regs maps asm register numbers to LLVM register numbers and RegKind
|
|
|
|
// says what kind of address register we're using (ADDR32Reg or ADDR64Reg).
|
2013-05-24 22:26:46 +08:00
|
|
|
bool SystemZAsmParser::parseAddress(unsigned &Base, const MCExpr *&Disp,
|
2015-05-06 03:23:40 +08:00
|
|
|
unsigned &Index, bool &IsVector,
|
|
|
|
const MCExpr *&Length, const unsigned *Regs,
|
2013-07-02 22:56:45 +08:00
|
|
|
RegisterKind RegKind) {
|
2013-05-07 00:15:19 +08:00
|
|
|
// Parse the displacement, which must always be present.
|
|
|
|
if (getParser().parseExpression(Disp))
|
2013-05-24 22:26:46 +08:00
|
|
|
return true;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
// Parse the optional base and index.
|
2013-05-24 22:26:46 +08:00
|
|
|
Index = 0;
|
|
|
|
Base = 0;
|
2015-05-06 03:23:40 +08:00
|
|
|
IsVector = false;
|
2014-04-25 13:30:21 +08:00
|
|
|
Length = nullptr;
|
2013-05-07 00:15:19 +08:00
|
|
|
if (getLexer().is(AsmToken::LParen)) {
|
|
|
|
Parser.Lex();
|
|
|
|
|
2013-07-02 22:56:45 +08:00
|
|
|
if (getLexer().is(AsmToken::Percent)) {
|
|
|
|
// Parse the first register and decide whether it's a base or an index.
|
|
|
|
Register Reg;
|
2015-05-06 03:23:40 +08:00
|
|
|
if (parseRegister(Reg))
|
2013-07-02 22:56:45 +08:00
|
|
|
return true;
|
2015-05-06 03:23:40 +08:00
|
|
|
if (Reg.Group == RegV) {
|
|
|
|
// A vector index register. The base register is optional.
|
|
|
|
IsVector = true;
|
|
|
|
Index = SystemZMC::VR128Regs[Reg.Num];
|
|
|
|
} else if (Reg.Group == RegGR) {
|
|
|
|
if (Reg.Num == 0)
|
|
|
|
return Error(Reg.StartLoc, "%r0 used in an address");
|
|
|
|
// If the are two registers, the first one is the index and the
|
|
|
|
// second is the base.
|
|
|
|
if (getLexer().is(AsmToken::Comma))
|
|
|
|
Index = Regs[Reg.Num];
|
|
|
|
else
|
|
|
|
Base = Regs[Reg.Num];
|
|
|
|
} else
|
|
|
|
return Error(Reg.StartLoc, "invalid address register");
|
2013-07-02 22:56:45 +08:00
|
|
|
} else {
|
|
|
|
// Parse the length.
|
|
|
|
if (getParser().parseExpression(Length))
|
|
|
|
return true;
|
|
|
|
}
|
2013-05-07 00:15:19 +08:00
|
|
|
|
2013-07-02 22:56:45 +08:00
|
|
|
// Check whether there's a second register. It's the base if so.
|
2013-05-07 00:15:19 +08:00
|
|
|
if (getLexer().is(AsmToken::Comma)) {
|
|
|
|
Parser.Lex();
|
2013-07-02 22:56:45 +08:00
|
|
|
Register Reg;
|
2013-05-24 22:26:46 +08:00
|
|
|
if (parseRegister(Reg, RegGR, Regs, RegKind))
|
|
|
|
return true;
|
2013-07-02 22:56:45 +08:00
|
|
|
Base = Reg.Num;
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Consume the closing bracket.
|
|
|
|
if (getLexer().isNot(AsmToken::RParen))
|
2013-05-24 22:26:46 +08:00
|
|
|
return Error(Parser.getTok().getLoc(), "unexpected token in address");
|
2013-05-07 00:15:19 +08:00
|
|
|
Parser.Lex();
|
|
|
|
}
|
2013-05-24 22:26:46 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Parse a memory operand and add it to Operands. The other arguments
|
|
|
|
// are as above.
|
|
|
|
SystemZAsmParser::OperandMatchResultTy
|
2015-05-05 01:40:53 +08:00
|
|
|
SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
|
|
|
|
const unsigned *Regs, RegisterKind RegKind) {
|
2013-05-24 22:26:46 +08:00
|
|
|
SMLoc StartLoc = Parser.getTok().getLoc();
|
|
|
|
unsigned Base, Index;
|
2015-05-06 03:23:40 +08:00
|
|
|
bool IsVector;
|
2013-05-24 22:26:46 +08:00
|
|
|
const MCExpr *Disp;
|
2013-07-02 22:56:45 +08:00
|
|
|
const MCExpr *Length;
|
2015-05-06 03:23:40 +08:00
|
|
|
if (parseAddress(Base, Disp, Index, IsVector, Length, Regs, RegKind))
|
2013-05-24 22:26:46 +08:00
|
|
|
return MatchOperand_ParseFail;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
if (IsVector && MemKind != BDVMem) {
|
|
|
|
Error(StartLoc, "invalid use of vector addressing");
|
|
|
|
return MatchOperand_ParseFail;
|
|
|
|
}
|
2013-07-02 22:56:45 +08:00
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
if (!IsVector && MemKind == BDVMem) {
|
|
|
|
Error(StartLoc, "vector index required in address");
|
|
|
|
return MatchOperand_ParseFail;
|
|
|
|
}
|
2013-07-02 22:56:45 +08:00
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
if (Index && MemKind != BDXMem && MemKind != BDVMem) {
|
|
|
|
Error(StartLoc, "invalid use of indexed addressing");
|
|
|
|
return MatchOperand_ParseFail;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Length && MemKind != BDLMem) {
|
|
|
|
Error(StartLoc, "invalid use of length addressing");
|
|
|
|
return MatchOperand_ParseFail;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!Length && MemKind == BDLMem) {
|
|
|
|
Error(StartLoc, "missing length in address");
|
|
|
|
return MatchOperand_ParseFail;
|
|
|
|
}
|
2013-07-02 22:56:45 +08:00
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
SMLoc EndLoc =
|
|
|
|
SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
|
2015-05-05 01:40:53 +08:00
|
|
|
Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
|
|
|
|
Index, Length, StartLoc,
|
|
|
|
EndLoc));
|
2013-05-07 00:15:19 +08:00
|
|
|
return MatchOperand_Success;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
|
2016-08-08 23:13:08 +08:00
|
|
|
StringRef IDVal = DirectiveID.getIdentifier();
|
|
|
|
|
|
|
|
if (IDVal == ".insn")
|
|
|
|
return ParseDirectiveInsn(DirectiveID.getLoc());
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-08-08 23:13:08 +08:00
|
|
|
/// ParseDirectiveInsn
|
|
|
|
/// ::= .insn [ format, encoding, (operands (, operands)*) ]
|
|
|
|
bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
|
|
|
|
MCAsmParser &Parser = getParser();
|
|
|
|
|
|
|
|
// Expect instruction format as identifier.
|
|
|
|
StringRef Format;
|
|
|
|
SMLoc ErrorLoc = Parser.getTok().getLoc();
|
|
|
|
if (Parser.parseIdentifier(Format))
|
|
|
|
return Error(ErrorLoc, "expected instruction format");
|
|
|
|
|
|
|
|
SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands;
|
|
|
|
|
|
|
|
// Find entry for this format in InsnMatchTable.
|
|
|
|
auto EntryRange =
|
|
|
|
std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable),
|
|
|
|
Format, CompareInsn());
|
|
|
|
|
|
|
|
// If first == second, couldn't find a match in the table.
|
|
|
|
if (EntryRange.first == EntryRange.second)
|
|
|
|
return Error(ErrorLoc, "unrecognized format");
|
|
|
|
|
|
|
|
struct InsnMatchEntry *Entry = EntryRange.first;
|
|
|
|
|
|
|
|
// Format should match from equal_range.
|
|
|
|
assert(Entry->Format == Format);
|
|
|
|
|
|
|
|
// Parse the following operands using the table's information.
|
|
|
|
for (int i = 0; i < Entry->NumOperands; i++) {
|
|
|
|
MatchClassKind Kind = Entry->OperandKinds[i];
|
|
|
|
|
|
|
|
SMLoc StartLoc = Parser.getTok().getLoc();
|
|
|
|
|
|
|
|
// Always expect commas as separators for operands.
|
|
|
|
if (getLexer().isNot(AsmToken::Comma))
|
|
|
|
return Error(StartLoc, "unexpected token in directive");
|
|
|
|
Lex();
|
|
|
|
|
|
|
|
// Parse operands.
|
|
|
|
OperandMatchResultTy ResTy;
|
|
|
|
if (Kind == MCK_AnyReg)
|
|
|
|
ResTy = parseAnyReg(Operands);
|
|
|
|
else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
|
|
|
|
ResTy = parseBDXAddr64(Operands);
|
|
|
|
else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
|
|
|
|
ResTy = parseBDAddr64(Operands);
|
|
|
|
else if (Kind == MCK_PCRel32)
|
|
|
|
ResTy = parsePCRel32(Operands);
|
|
|
|
else if (Kind == MCK_PCRel16)
|
|
|
|
ResTy = parsePCRel16(Operands);
|
|
|
|
else {
|
|
|
|
// Only remaining operand kind is an immediate.
|
|
|
|
const MCExpr *Expr;
|
|
|
|
SMLoc StartLoc = Parser.getTok().getLoc();
|
|
|
|
|
|
|
|
// Expect immediate expression.
|
|
|
|
if (Parser.parseExpression(Expr))
|
|
|
|
return Error(StartLoc, "unexpected token in directive");
|
|
|
|
|
|
|
|
SMLoc EndLoc =
|
|
|
|
SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
|
|
|
|
|
|
|
|
Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
|
|
|
|
ResTy = MatchOperand_Success;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ResTy != MatchOperand_Success)
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Build the instruction with the parsed operands.
|
|
|
|
MCInst Inst = MCInstBuilder(Entry->Opcode);
|
|
|
|
|
|
|
|
for (size_t i = 0; i < Operands.size(); i++) {
|
|
|
|
MCParsedAsmOperand &Operand = *Operands[i];
|
|
|
|
MatchClassKind Kind = Entry->OperandKinds[i];
|
|
|
|
|
|
|
|
// Verify operand.
|
|
|
|
unsigned Res = validateOperandClass(Operand, Kind);
|
|
|
|
if (Res != Match_Success)
|
|
|
|
return Error(Operand.getStartLoc(), "unexpected operand type");
|
|
|
|
|
|
|
|
// Add operands to instruction.
|
|
|
|
SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand);
|
|
|
|
if (ZOperand.isReg())
|
|
|
|
ZOperand.addRegOperands(Inst, 1);
|
|
|
|
else if (ZOperand.isMem(BDMem))
|
|
|
|
ZOperand.addBDAddrOperands(Inst, 2);
|
|
|
|
else if (ZOperand.isMem(BDXMem))
|
|
|
|
ZOperand.addBDXAddrOperands(Inst, 3);
|
|
|
|
else if (ZOperand.isImm())
|
|
|
|
ZOperand.addImmOperands(Inst, 1);
|
|
|
|
else
|
|
|
|
llvm_unreachable("unexpected operand type");
|
|
|
|
}
|
|
|
|
|
|
|
|
// Emit as a regular instruction.
|
|
|
|
Parser.getStreamer().EmitInstruction(Inst, getSTI());
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
|
|
|
|
SMLoc &EndLoc) {
|
|
|
|
Register Reg;
|
|
|
|
if (parseRegister(Reg))
|
2013-05-24 22:26:46 +08:00
|
|
|
return true;
|
2013-05-24 22:14:38 +08:00
|
|
|
if (Reg.Group == RegGR)
|
|
|
|
RegNo = SystemZMC::GR64Regs[Reg.Num];
|
|
|
|
else if (Reg.Group == RegFP)
|
|
|
|
RegNo = SystemZMC::FP64Regs[Reg.Num];
|
2015-05-06 03:23:40 +08:00
|
|
|
else if (Reg.Group == RegV)
|
|
|
|
RegNo = SystemZMC::VR128Regs[Reg.Num];
|
2013-05-24 22:14:38 +08:00
|
|
|
else
|
|
|
|
// FIXME: Access registers aren't modelled as LLVM registers yet.
|
|
|
|
return Error(Reg.StartLoc, "invalid operand for instruction");
|
2013-05-07 00:15:19 +08:00
|
|
|
StartLoc = Reg.StartLoc;
|
|
|
|
EndLoc = Reg.EndLoc;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2014-06-09 00:18:35 +08:00
|
|
|
bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
|
|
|
|
StringRef Name, SMLoc NameLoc,
|
|
|
|
OperandVector &Operands) {
|
2013-05-07 00:15:19 +08:00
|
|
|
Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
|
|
|
|
|
|
|
|
// Read the remaining operands.
|
|
|
|
if (getLexer().isNot(AsmToken::EndOfStatement)) {
|
|
|
|
// Read the first operand.
|
|
|
|
if (parseOperand(Operands, Name)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Read any subsequent operands.
|
|
|
|
while (getLexer().is(AsmToken::Comma)) {
|
|
|
|
Parser.Lex();
|
|
|
|
if (parseOperand(Operands, Name)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (getLexer().isNot(AsmToken::EndOfStatement)) {
|
|
|
|
SMLoc Loc = getLexer().getLoc();
|
|
|
|
return Error(Loc, "unexpected token in argument list");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Consume the EndOfStatement.
|
|
|
|
Parser.Lex();
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2014-06-09 00:18:35 +08:00
|
|
|
bool SystemZAsmParser::parseOperand(OperandVector &Operands,
|
|
|
|
StringRef Mnemonic) {
|
2013-05-07 00:15:19 +08:00
|
|
|
// Check if the current operand has a custom associated parser, if so, try to
|
|
|
|
// custom parse the operand, or fallback to the general approach.
|
|
|
|
OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
|
|
|
|
if (ResTy == MatchOperand_Success)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// If there wasn't a custom match, try the generic matcher below. Otherwise,
|
|
|
|
// there was a match, but an error occurred, in which case, just return that
|
|
|
|
// the operand parsing failed.
|
|
|
|
if (ResTy == MatchOperand_ParseFail)
|
|
|
|
return true;
|
|
|
|
|
2013-05-24 22:26:46 +08:00
|
|
|
// Check for a register. All real register operands should have used
|
|
|
|
// a context-dependent parse routine, which gives the required register
|
|
|
|
// class. The code is here to mop up other cases, like those where
|
|
|
|
// the instruction isn't recognized.
|
|
|
|
if (Parser.getTok().is(AsmToken::Percent)) {
|
|
|
|
Register Reg;
|
|
|
|
if (parseRegister(Reg))
|
|
|
|
return true;
|
|
|
|
Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// The only other type of operand is an immediate or address. As above,
|
|
|
|
// real address operands should have used a context-dependent parse routine,
|
|
|
|
// so we treat any plain expression as an immediate.
|
2013-05-07 00:15:19 +08:00
|
|
|
SMLoc StartLoc = Parser.getTok().getLoc();
|
2013-05-24 22:26:46 +08:00
|
|
|
unsigned Base, Index;
|
2015-05-06 03:23:40 +08:00
|
|
|
bool IsVector;
|
2013-07-02 22:56:45 +08:00
|
|
|
const MCExpr *Expr, *Length;
|
2015-05-06 03:23:40 +08:00
|
|
|
if (parseAddress(Base, Expr, Index, IsVector, Length, SystemZMC::GR64Regs,
|
|
|
|
ADDR64Reg))
|
2013-05-07 00:15:19 +08:00
|
|
|
return true;
|
|
|
|
|
|
|
|
SMLoc EndLoc =
|
|
|
|
SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
|
2013-07-02 22:56:45 +08:00
|
|
|
if (Base || Index || Length)
|
2013-05-24 22:26:46 +08:00
|
|
|
Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
|
|
|
|
else
|
|
|
|
Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
|
2013-05-07 00:15:19 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2014-06-09 00:18:35 +08:00
|
|
|
bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
|
|
|
|
OperandVector &Operands,
|
|
|
|
MCStreamer &Out,
|
2014-08-18 19:49:42 +08:00
|
|
|
uint64_t &ErrorInfo,
|
2014-06-09 00:18:35 +08:00
|
|
|
bool MatchingInlineAsm) {
|
2013-05-07 00:15:19 +08:00
|
|
|
MCInst Inst;
|
|
|
|
unsigned MatchResult;
|
|
|
|
|
|
|
|
MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
|
2015-06-30 20:32:53 +08:00
|
|
|
MatchingInlineAsm);
|
2013-05-07 00:15:19 +08:00
|
|
|
switch (MatchResult) {
|
|
|
|
case Match_Success:
|
|
|
|
Inst.setLoc(IDLoc);
|
2015-11-14 13:20:05 +08:00
|
|
|
Out.EmitInstruction(Inst, getSTI());
|
2013-05-07 00:15:19 +08:00
|
|
|
return false;
|
|
|
|
|
|
|
|
case Match_MissingFeature: {
|
2015-06-30 20:32:53 +08:00
|
|
|
assert(ErrorInfo && "Unknown missing feature!");
|
2013-05-07 00:15:19 +08:00
|
|
|
// Special case the error message for the very common case where only
|
|
|
|
// a single subtarget feature is missing
|
|
|
|
std::string Msg = "instruction requires:";
|
2015-06-30 20:32:53 +08:00
|
|
|
uint64_t Mask = 1;
|
|
|
|
for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
|
|
|
|
if (ErrorInfo & Mask) {
|
2013-05-07 00:15:19 +08:00
|
|
|
Msg += " ";
|
2015-06-30 20:32:53 +08:00
|
|
|
Msg += getSubtargetFeatureName(ErrorInfo & Mask);
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
2015-06-30 20:32:53 +08:00
|
|
|
Mask <<= 1;
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
return Error(IDLoc, Msg);
|
|
|
|
}
|
|
|
|
|
|
|
|
case Match_InvalidOperand: {
|
|
|
|
SMLoc ErrorLoc = IDLoc;
|
2014-08-18 19:49:42 +08:00
|
|
|
if (ErrorInfo != ~0ULL) {
|
2013-05-07 00:15:19 +08:00
|
|
|
if (ErrorInfo >= Operands.size())
|
|
|
|
return Error(IDLoc, "too few operands for instruction");
|
|
|
|
|
2014-06-09 00:18:35 +08:00
|
|
|
ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
|
2013-05-07 00:15:19 +08:00
|
|
|
if (ErrorLoc == SMLoc())
|
|
|
|
ErrorLoc = IDLoc;
|
|
|
|
}
|
|
|
|
return Error(ErrorLoc, "invalid operand for instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
case Match_MnemonicFail:
|
|
|
|
return Error(IDLoc, "invalid instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
llvm_unreachable("Unexpected match type");
|
|
|
|
}
|
|
|
|
|
2014-06-09 00:18:35 +08:00
|
|
|
SystemZAsmParser::OperandMatchResultTy
|
|
|
|
SystemZAsmParser::parseAccessReg(OperandVector &Operands) {
|
2013-05-24 22:26:46 +08:00
|
|
|
if (Parser.getTok().isNot(AsmToken::Percent))
|
|
|
|
return MatchOperand_NoMatch;
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
Register Reg;
|
2014-04-25 13:30:21 +08:00
|
|
|
if (parseRegister(Reg, RegAccess, nullptr))
|
2013-05-24 22:26:46 +08:00
|
|
|
return MatchOperand_ParseFail;
|
|
|
|
|
|
|
|
Operands.push_back(SystemZOperand::createAccessReg(Reg.Num,
|
|
|
|
Reg.StartLoc,
|
|
|
|
Reg.EndLoc));
|
|
|
|
return MatchOperand_Success;
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
2014-06-09 00:18:35 +08:00
|
|
|
SystemZAsmParser::OperandMatchResultTy
|
|
|
|
SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
|
2015-02-18 17:11:36 +08:00
|
|
|
int64_t MaxVal, bool AllowTLS) {
|
2013-05-14 17:47:26 +08:00
|
|
|
MCContext &Ctx = getContext();
|
|
|
|
MCStreamer &Out = getStreamer();
|
|
|
|
const MCExpr *Expr;
|
|
|
|
SMLoc StartLoc = Parser.getTok().getLoc();
|
|
|
|
if (getParser().parseExpression(Expr))
|
|
|
|
return MatchOperand_NoMatch;
|
|
|
|
|
|
|
|
// For consistency with the GNU assembler, treat immediates as offsets
|
|
|
|
// from ".".
|
2014-03-06 19:22:58 +08:00
|
|
|
if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
|
2013-05-14 17:47:26 +08:00
|
|
|
int64_t Value = CE->getValue();
|
|
|
|
if ((Value & 1) || Value < MinVal || Value > MaxVal) {
|
|
|
|
Error(StartLoc, "offset out of range");
|
|
|
|
return MatchOperand_ParseFail;
|
|
|
|
}
|
2015-05-19 02:43:14 +08:00
|
|
|
MCSymbol *Sym = Ctx.createTempSymbol();
|
2013-05-14 17:47:26 +08:00
|
|
|
Out.EmitLabel(Sym);
|
2015-05-30 09:25:56 +08:00
|
|
|
const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
|
2013-05-14 17:47:26 +08:00
|
|
|
Ctx);
|
2015-05-30 09:25:56 +08:00
|
|
|
Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
|
2013-05-14 17:47:26 +08:00
|
|
|
}
|
|
|
|
|
2015-02-18 17:11:36 +08:00
|
|
|
// Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
|
|
|
|
const MCExpr *Sym = nullptr;
|
|
|
|
if (AllowTLS && getLexer().is(AsmToken::Colon)) {
|
|
|
|
Parser.Lex();
|
|
|
|
|
|
|
|
if (Parser.getTok().isNot(AsmToken::Identifier)) {
|
|
|
|
Error(Parser.getTok().getLoc(), "unexpected token");
|
|
|
|
return MatchOperand_ParseFail;
|
|
|
|
}
|
|
|
|
|
|
|
|
MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
|
|
|
|
StringRef Name = Parser.getTok().getString();
|
|
|
|
if (Name == "tls_gdcall")
|
|
|
|
Kind = MCSymbolRefExpr::VK_TLSGD;
|
|
|
|
else if (Name == "tls_ldcall")
|
|
|
|
Kind = MCSymbolRefExpr::VK_TLSLDM;
|
|
|
|
else {
|
|
|
|
Error(Parser.getTok().getLoc(), "unknown TLS tag");
|
|
|
|
return MatchOperand_ParseFail;
|
|
|
|
}
|
|
|
|
Parser.Lex();
|
|
|
|
|
|
|
|
if (Parser.getTok().isNot(AsmToken::Colon)) {
|
|
|
|
Error(Parser.getTok().getLoc(), "unexpected token");
|
|
|
|
return MatchOperand_ParseFail;
|
|
|
|
}
|
|
|
|
Parser.Lex();
|
|
|
|
|
|
|
|
if (Parser.getTok().isNot(AsmToken::Identifier)) {
|
|
|
|
Error(Parser.getTok().getLoc(), "unexpected token");
|
|
|
|
return MatchOperand_ParseFail;
|
|
|
|
}
|
|
|
|
|
|
|
|
StringRef Identifier = Parser.getTok().getString();
|
2015-05-30 09:25:56 +08:00
|
|
|
Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
|
2015-02-18 17:11:36 +08:00
|
|
|
Kind, Ctx);
|
|
|
|
Parser.Lex();
|
|
|
|
}
|
|
|
|
|
2013-05-14 17:47:26 +08:00
|
|
|
SMLoc EndLoc =
|
|
|
|
SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
|
2015-02-18 17:11:36 +08:00
|
|
|
|
|
|
|
if (AllowTLS)
|
|
|
|
Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
|
|
|
|
StartLoc, EndLoc));
|
|
|
|
else
|
|
|
|
Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
|
|
|
|
|
2013-05-14 17:47:26 +08:00
|
|
|
return MatchOperand_Success;
|
|
|
|
}
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
// Force static initialization.
|
|
|
|
extern "C" void LLVMInitializeSystemZAsmParser() {
|
|
|
|
RegisterMCAsmParser<SystemZAsmParser> X(TheSystemZTarget);
|
|
|
|
}
|